I 000037 40 271 1071604206576 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
 }
}
I 000038 40 935 1071604956185 qdecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,76,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  PIN  26, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="NET76"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,-10), (10,10), (0,0) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="NET77"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 2707 1071605043716 qdecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605043"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 62
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,83,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,83,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 45
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  61, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 60
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PhaseA"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="3"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="CE"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  60, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="UD"
    #NUMBER="5"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2637 1071605259388 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605259"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 66
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,59)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,40,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="2"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2637 1071605342091 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605259"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 66
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,59)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,40,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="2"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2721 1071605363357 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 271 1071605383185 qcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
 }
}
I 000038 40 2862 1071605383186 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2624 1071605499138 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605499"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 14
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,38,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,40,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,65,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,60,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,83,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(31:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2624 1071605545701 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605499"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 14
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,38,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,40,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,65,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,60,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,83,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(31:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2625 1071605568013 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605568"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,38,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,53,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,65,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,68,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,83,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2625 1071605574248 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605568"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,38,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,53,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,65,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,68,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,83,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071605574263 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2625 1071605747357 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605568"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,38,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,53,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,65,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,68,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,83,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2798 1071605766545 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605766"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2798 1071605841420 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605766"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071605841435 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000037 40 290 1071605845373 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
 }
}
I 000038 40 2059 1071605849404 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071605849"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,240,440)
    FREEID 10
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,240,440)
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder0"
        #VERILOG_TYPE="wire"
      }
      COORD (0,40)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 2
      ALIGN 4
      RECT (15,15,135,69)
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder0"
        #VERILOG_TYPE="wire"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 4
      ALIGN 4
      RECT (15,55,135,109)
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #VERILOG_TYPE="wire"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 6
      ALIGN 4
      RECT (15,95,135,149)
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #VERILOG_TYPE="wire"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 8
      ALIGN 4
      RECT (15,135,135,189)
    }
  }
}
I 000038 40 1856 1071605868857 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605849"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 10
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,178,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,68,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,53,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder0"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder0"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 1962 1071605882248 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605882"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 11
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder0"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder0"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
 }
}
I 000039 40 2798 1071605916013 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605766"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071605916029 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2798 1071605969107 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605766"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071605969123 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 1962 1071605981966 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605882"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 11
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder0"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder0"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
 }
}
I 000038 40 3038 1071605985701 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071605985"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,240,440)
    FREEID 14
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,240,440)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder0"
        #VERILOG_TYPE="wire"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 10
      ALIGN 4
      RECT (15,135,135,189)
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Count(23:0)"
        #VERILOG_TYPE="wire"
      }
      COORD (240,40)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 12
      ALIGN 6
      RECT (105,15,225,69)
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder0"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (15,70,178,94)
      ALIGN 4
      MARGINS (1,1)
      PARENT 2
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder0"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (15,110,178,134)
      ALIGN 4
      MARGINS (1,1)
      PARENT 4
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000038 40 2661 1071605988732 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605985"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 14
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,30,225,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder0"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2682 1071605993732 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605993"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder0"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2682 1071606117201 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605993"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder0"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2682 1071608678420 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605993"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder0"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder0"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2798 1071608678560 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605766"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071608678576 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 3037 1071608734185 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071608734"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,240,440)
    FREEID 20
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,240,440)
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Count(23:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,100)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      RECT (123,90,225,114)
      ALIGN 6
      MARGINS (1,1)
      PARENT 12
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,200)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 14
      ALIGN 4
      RECT (15,175,135,229)
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,240)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 16
      ALIGN 4
      RECT (15,215,135,269)
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,280)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 18
      ALIGN 4
      RECT (15,255,135,309)
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000038 40 2681 1071608737841 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071608734"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,178,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,270,178,294)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 2732 1071608751763 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071608751"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 21
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 2732 1071608759623 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071608751"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 21
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 2732 1071608867529 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071608751"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 21
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 3452 1071609615279 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609615"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 18
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,68,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,112,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,60,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,112,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,40,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,135,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,30,185,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,70,185,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(31:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(31:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3471 1071609739732 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609615"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 18
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,68,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,112,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,60,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,112,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,40,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,135,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,30,185,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,70,185,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(31:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(31:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3706 1071609772654 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609772"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,60)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,40)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(31:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(31:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2798 1071609790638 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605766"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071609790654 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3706 1071609790655 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609772"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,60)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,40)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(31:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(31:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 4057 1071609797529 holdreg
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071609797"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,200,960)
    FREEID 19
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,200,960)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="clk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (120,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      RECT (106,15,130,40)
      ALIGN 1
      MARGINS (1,1)
      PARENT 10
      ORIENTATION 5
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="regselect(2:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (200,520)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      RECT (65,510,185,534)
      ALIGN 6
      MARGINS (1,1)
      PARENT 12
      ORIENTATION 2
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="ready"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (200,220)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (136,210,185,234)
      ALIGN 6
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="out(7:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (200,400)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (118,390,185,414)
      ALIGN 6
      MARGINS (1,1)
      PARENT 16
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="select"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (200,260)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (132,250,185,274)
      ALIGN 6
      MARGINS (1,1)
      PARENT 2
      ORIENTATION 2
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="ch0in(23:0)"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,140)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (15,130,112,154)
      ALIGN 4
      MARGINS (1,1)
      PARENT 4
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,60)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="ch1in(23:0)"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,860)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (15,850,112,874)
      ALIGN 4
      MARGINS (1,1)
      PARENT 8
    }
  }
}
I 000039 40 3496 1071609811795 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609797"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,60)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,40)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="clk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3497 1071609826498 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609826"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2798 1071609830873 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605766"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(24:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071609830888 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3873 1071609830904 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609826"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3064 1071609892623 counter
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071609892"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,220,300)
    FREEID 15
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,220,300)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="updown"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,220)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      RECT (15,210,83,234)
      ALIGN 4
      MARGINS (1,1)
      PARENT 10
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="count(23:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,140)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      RECT (107,130,205,154)
      ALIGN 6
      MARGINS (1,1)
      PARENT 12
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="ce"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (15,110,38,134)
      ALIGN 4
      MARGINS (1,1)
      PARENT 2
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (160,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (146,15,170,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 4
      ORIENTATION 5
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="home"
        #NUMBER="0"
        #SIDE="bottom"
      }
      COORD (100,300)
      LINE 2,0,0
      {
        POINTS ((-10,0),(10,0),(0,-10),(-10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (90,235,114,285)
      ALIGN 9
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 8
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000039 40 2642 1071609898623 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071609898638 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3705 1071609898654 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609826"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071609978607 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071609978608 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3705 1071609978623 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609826"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2873 1071610089935 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071608751"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 21
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 2602 1071610098091 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071610098"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,240,440)
    FREEID 21
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,240,440)
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (15,150,162,174)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (15,70,178,94)
      ALIGN 4
      MARGINS (1,1)
      PARENT 16
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (15,110,178,134)
      ALIGN 4
      MARGINS (1,1)
      PARENT 18
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000038 40 2249 1071610103029 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071610098"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 21
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2642 1071610308623 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2799 1071610308638 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3705 1071610308654 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609826"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 19
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 3059 1071610320498 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071610320"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,240,440)
    FREEID 22
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,240,440)
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (15,150,162,174)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (15,70,178,94)
      ALIGN 4
      MARGINS (1,1)
      PARENT 16
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (15,110,178,134)
      ALIGN 4
      MARGINS (1,1)
      PARENT 18
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="CountOut(7:0)"
        #VERILOG_TYPE="wire"
      }
      COORD (240,40)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 20
      ALIGN 6
      RECT (105,15,225,69)
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000038 40 2661 1071610323279 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071610320"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 22
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,30,225,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2683 1071610329341 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071610329"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 23
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2683 1071610358216 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071610329"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 23
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000040 40 271 1071610934966 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,500)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,500)
  }
 }
}
I 000040 40 271 1071611016123 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
 }
}
I 000040 40 290 1071611048732 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
 }
}
I 000041 40 2774 1071611178982 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611178"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 35
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 2774 1071611197013 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611178"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 35
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3602 1071611227232 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071611235920 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2683 1071611235935 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071610329"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 23
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2683 1071686134879 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071610329"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 23
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 3978 1071686134880 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2683 1071686189285 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071610329"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 23
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 3097 1071686213379 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071686213"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071686218270 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3379 1071686218285 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071686213"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071686251613 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071686251629 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 4094 1071686251645 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609826"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 4073 1071686540816 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609826"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (65,510,185,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (136,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="select"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (200,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="regselect(2:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ready"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 3685 1071686579113 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071686579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 22
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071686582801 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071686582816 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3685 1071686582832 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071686579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 22
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3253 1071687190098 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071686213"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071687217348 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071687221270 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071687221285 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4068 1071687278629 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071686579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 22
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000038 40 2799 1071687278645 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071687278660 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 4047 1071687307379 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071686579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 22
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 3595 1071687311582 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000038 40 2799 1071687319488 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071687319504 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3595 1071687319505 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000041 40 3978 1071687681098 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071687681113 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071687842004 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071687842020 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000033 40 271 1071687996629 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,500)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,500)
  }
 }
}
I 000034 40 5073 1071688004582 u4
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071688004"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,220,500)
    FREEID 24
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,220,500)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,200)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 10
      ALIGN 4
      RECT (15,175,125,229)
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,240)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 12
      ALIGN 4
      RECT (15,215,125,269)
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RD"
        #VERILOG_TYPE="wire"
      }
      COORD (0,280)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 14
      ALIGN 4
      RECT (15,255,125,309)
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #VERILOG_TYPE="wire"
      }
      COORD (0,320)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 16
      ALIGN 4
      RECT (15,295,125,349)
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="SMclk"
        #VERILOG_TYPE="wire"
      }
      COORD (0,360)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 18
      ALIGN 4
      RECT (15,335,125,389)
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AS"
        #VERILOG_TYPE="wire"
      }
      COORD (0,40)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WR"
        #VERILOG_TYPE="wire"
      }
      COORD (0,400)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 20
      ALIGN 4
      RECT (15,375,125,429)
    }
    PIN 22,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AD(7:0)"
        #VERILOG_TYPE="wire"
      }
      COORD (220,40)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-20,0),(-10,-10),(0,0))
      }
    }
    TEXT 23,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 22
      ALIGN 6
      RECT (85,15,195,69)
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 2
      ALIGN 4
      RECT (15,15,125,69)
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Aclk"
        #VERILOG_TYPE="wire"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 4
      ALIGN 4
      RECT (15,55,125,109)
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 6
      ALIGN 4
      RECT (15,95,125,149)
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Mclk"
        #VERILOG_TYPE="wire"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 8
      ALIGN 4
      RECT (15,135,125,189)
    }
  }
}
I 000034 40 4576 1071688037848 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688004"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,53,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,162,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,55,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,178,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,178,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,270,45,294)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,310,68,334)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,68,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,30,195,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 22
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000034 40 4908 1071688076129 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000034 40 4908 1071688294848 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 1632 1071690162988 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (93,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (144,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (144,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="BUS140(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="NET86"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="NET95"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="NET104"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000035 40 1838 1071690193676 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071690193"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000035 40 1838 1071690209754 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071690193"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000035 40 2302 1071690226285 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071690226"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 4908 1071690301316 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2302 1071690301332 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071690226"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2396 1071690643832 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071690226"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2302 1071691176645 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071690226"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2417 1071691184879 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 4908 1071691188645 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2464 1071691188660 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 4908 1071693296051 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2443 1071693296066 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 4908 1071694558785 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2443 1071694558801 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 4908 1071694602551 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2443 1071694602552 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 4908 1071694653238 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2443 1071694653254 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071695001863 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071695001879 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071695002004 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071695002020 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3595 1071695002035 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000034 40 4908 1071695009754 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2443 1071695009755 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071695025332 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071695025348 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071695025473 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071695025474 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3595 1071695025488 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000034 40 4908 1071695025723 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071688076"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 25
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,10), (20,0), (10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2443 1071695025738 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 952 1071695749457 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000036 40 3852 1071695870285 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071696083441 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071696083457 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071696083458 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 5849 1071696088426 u4
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071696088"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,220,600)
    FREEID 26
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,220,600)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,160)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      RECT (42,150,205,174)
      ALIGN 6
      MARGINS (1,1)
      PARENT 10
      ORIENTATION 2
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,200)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      RECT (42,190,205,214)
      ALIGN 6
      MARGINS (1,1)
      PARENT 12
      ORIENTATION 2
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RD"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,380)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (15,370,45,394)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="bottom"
      }
      COORD (80,600)
      LINE 2,0,0
      {
        POINTS ((-10,0),(10,0),(0,-10),(-10,0))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (70,532,94,585)
      ALIGN 9
      MARGINS (1,1)
      PARENT 16
      ORIENTATION 8
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="SMclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (80,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (66,15,90,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 18
      ORIENTATION 5
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AS"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,360)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WR"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,400)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      RECT (15,390,50,414)
      ALIGN 4
      MARGINS (1,1)
      PARENT 20
    }
    PIN 22,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AD(7:0)"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,340)
      LINE 2,0,0
      {
        POINTS ((0,0),(10,-10),(20,0),(10,10),(0,0))
      }
    }
    TEXT 23,0,0
    {
      TEXT "$#NAME"
      RECT (25,330,93,354)
      ALIGN 4
      MARGINS (1,1)
      PARENT 22
      ORIENTATION 2
    }
    PIN 24,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="GPIO(12:0)"
        #VERILOG_TYPE="wire"
      }
      COORD (220,240)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-20,0),(-10,-10),(0,0))
      }
    }
    TEXT 25,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 24
      ALIGN 6
      RECT (85,215,195,269)
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (15,350,43,374)
      ALIGN 4
      MARGINS (1,1)
      PARENT 2
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Aclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (120,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (106,15,130,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 4
      ORIENTATION 5
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,120)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (58,110,205,134)
      ALIGN 6
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 2
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Mclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,55)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000035 40 2443 1071696122473 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 5059 1071696122488 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071696088"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000036 40 3899 1071696230441 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2443 1071698525473 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071691184"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2445 1071698533848 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 5059 1071698536832 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071696088"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1071698536848 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 949 1071698889129 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,160)
  FREEID 14
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 5986 1071699012129 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699012"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-140,0,220,160)
  FREEID 63
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-140,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,8,-62,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,28,-77,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,48,-75,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,68,-62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,88,-77,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,108,-75,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-140,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 5986 1071699212895 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699012"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-140,0,220,160)
  FREEID 63
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-140,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,8,-62,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,28,-77,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,48,-75,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,68,-62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,88,-77,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-126,108,-75,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-140,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 5966 1071699218598 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699218"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071699222098 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071699222113 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071699222129 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 5966 1071699222145 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699218"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6060 1071699229582 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699218"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 8409 1071699386410 u4
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071699386"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,220,600)
    FREEID 38
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,220,600)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,160)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      RECT (42,150,205,174)
      ALIGN 6
      MARGINS (1,1)
      PARENT 10
      ORIENTATION 2
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,200)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      RECT (42,190,205,214)
      ALIGN 6
      MARGINS (1,1)
      PARENT 12
      ORIENTATION 2
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RD"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,380)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (15,370,45,394)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="bottom"
      }
      COORD (80,600)
      LINE 2,0,0
      {
        POINTS ((-10,0),(10,0),(0,-10),(-10,0))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (70,532,94,585)
      ALIGN 9
      MARGINS (1,1)
      PARENT 16
      ORIENTATION 8
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="SMclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (80,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (66,15,90,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 18
      ORIENTATION 5
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AS"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,360)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WR"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,400)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      RECT (15,390,50,414)
      ALIGN 4
      MARGINS (1,1)
      PARENT 20
    }
    PIN 22,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AD(7:0)"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,340)
      LINE 2,0,0
      {
        POINTS ((0,0),(10,-10),(20,0),(10,10),(0,0))
      }
    }
    TEXT 23,0,0
    {
      TEXT "$#NAME"
      RECT (25,330,93,354)
      ALIGN 4
      MARGINS (1,1)
      PARENT 22
      ORIENTATION 2
    }
    PIN 24,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="GPIO(12:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,240)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-20,0),(-10,-10),(0,0))
      }
    }
    TEXT 25,0,0
    {
      TEXT "$#NAME"
      RECT (94,230,195,254)
      ALIGN 6
      MARGINS (1,1)
      PARENT 24
    }
    PIN 26,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="FLS1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,40)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 27,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 26
      ALIGN 4
      RECT (15,15,125,69)
    }
    PIN 28,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="FLS2"
        #VERILOG_TYPE="wire"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 29,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 28
      ALIGN 4
      RECT (15,55,125,109)
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (15,350,43,374)
      ALIGN 4
      MARGINS (1,1)
      PARENT 2
    }
    PIN 30,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 31,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 30
      ALIGN 4
      RECT (15,95,125,149)
    }
    PIN 32,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home2"
        #VERILOG_TYPE="wire"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 33,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 32
      ALIGN 4
      RECT (15,135,125,189)
    }
    PIN 34,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RLS1"
        #VERILOG_TYPE="wire"
      }
      COORD (0,200)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 35,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 34
      ALIGN 4
      RECT (15,175,125,229)
    }
    PIN 36,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RLS2"
        #VERILOG_TYPE="wire"
      }
      COORD (0,240)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 37,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 36
      ALIGN 4
      RECT (15,215,125,269)
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Aclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (120,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (106,15,130,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 4
      ORIENTATION 5
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,120)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (58,110,205,134)
      ALIGN 6
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 2
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Mclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,55)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000034 40 7346 1071699392098 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699386"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,64,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,64,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,79,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,79,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,66,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 34
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,66,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000034 40 7595 1071699419270 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699419"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000034 40 7595 1071699473410 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699419"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000035 40 2445 1071699473426 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 7595 1071699523754 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699419"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000035 40 2445 1071699523770 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071699581145 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071699581160 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071699581176 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 5966 1071699581177 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699218"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071699581316 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071699581332 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3595 1071699581348 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000034 40 7595 1071699581645 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699419"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000035 40 2445 1071699581646 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071699870348 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071699870363 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071699870364 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 5966 1071699870379 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699218"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071699870520 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071699870535 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3595 1071699870551 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000034 40 7595 1071699870848 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699419"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000035 40 2445 1071699870863 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 5966 1071699962598 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699218"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6082 1071699971191 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071699975754 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071699975755 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071699975770 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6129 1071699975785 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 948 1071700725160 fub1
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,200)
  FREEID 14
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000036 40 6918 1071700928238 fub1
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071700928"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 73
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071701052816 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071701052832 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071701052848 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6918 1071701052863 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071700928"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 73
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071701052879 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 12088 1071701074176 u4
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071701074"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,220,600)
    FREEID 54
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,220,600)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,160)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      RECT (42,150,205,174)
      ALIGN 6
      MARGINS (1,1)
      PARENT 10
      ORIENTATION 2
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,200)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      RECT (42,190,205,214)
      ALIGN 6
      MARGINS (1,1)
      PARENT 12
      ORIENTATION 2
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RD"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,380)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (15,370,45,394)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="bottom"
      }
      COORD (80,600)
      LINE 2,0,0
      {
        POINTS ((-10,0),(10,0),(0,-10),(-10,0))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (70,532,94,585)
      ALIGN 9
      MARGINS (1,1)
      PARENT 16
      ORIENTATION 8
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="SMclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (80,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (66,15,90,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 18
      ORIENTATION 5
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AS"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,360)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WR"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,400)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      RECT (15,390,50,414)
      ALIGN 4
      MARGINS (1,1)
      PARENT 20
    }
    PIN 22,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AD(7:0)"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,340)
      LINE 2,0,0
      {
        POINTS ((0,0),(10,-10),(20,0),(10,10),(0,0))
      }
    }
    TEXT 23,0,0
    {
      TEXT "$#NAME"
      RECT (25,330,93,354)
      ALIGN 4
      MARGINS (1,1)
      PARENT 22
      ORIENTATION 2
    }
    PIN 24,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="GPIO(12:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,240)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-20,0),(-10,-10),(0,0))
      }
    }
    TEXT 25,0,0
    {
      TEXT "$#NAME"
      RECT (94,230,195,254)
      ALIGN 6
      MARGINS (1,1)
      PARENT 24
    }
    PIN 26,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="FLS1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,40)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 27,0,0
    {
      TEXT "$#NAME"
      RECT (156,30,205,54)
      ALIGN 6
      MARGINS (1,1)
      PARENT 26
      ORIENTATION 2
    }
    PIN 28,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="FLS2"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,540)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 29,0,0
    {
      TEXT "$#NAME"
      RECT (156,530,205,554)
      ALIGN 6
      MARGINS (1,1)
      PARENT 28
      ORIENTATION 2
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (15,350,43,374)
      ALIGN 4
      MARGINS (1,1)
      PARENT 2
    }
    PIN 30,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,80)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 31,0,0
    {
      TEXT "$#NAME"
      RECT (141,70,205,94)
      ALIGN 6
      MARGINS (1,1)
      PARENT 30
      ORIENTATION 2
    }
    PIN 32,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home2"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,500)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 33,0,0
    {
      TEXT "$#NAME"
      RECT (141,490,205,514)
      ALIGN 6
      MARGINS (1,1)
      PARENT 32
      ORIENTATION 2
    }
    PIN 34,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RLS1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,60)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 35,0,0
    {
      TEXT "$#NAME"
      RECT (154,50,205,74)
      ALIGN 6
      MARGINS (1,1)
      PARENT 34
      ORIENTATION 2
    }
    PIN 36,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RLS2"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,520)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 37,0,0
    {
      TEXT "$#NAME"
      RECT (154,510,205,534)
      ALIGN 6
      MARGINS (1,1)
      PARENT 36
      ORIENTATION 2
    }
    PIN 38,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Enc133FLG"
        #VERILOG_TYPE="wire"
      }
      COORD (0,40)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 39,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 38
      ALIGN 4
      RECT (15,15,125,69)
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Aclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (120,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    PIN 40,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Enc15FLG"
        #VERILOG_TYPE="wire"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 41,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 40
      ALIGN 4
      RECT (15,55,125,109)
    }
    PIN 42,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home133FLG"
        #VERILOG_TYPE="wire"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 43,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 42
      ALIGN 4
      RECT (15,95,125,149)
    }
    PIN 44,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home15FLG"
        #VERILOG_TYPE="wire"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 45,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 44
      ALIGN 4
      RECT (15,135,125,189)
    }
    PIN 46,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Enc133ctrl"
        #VERILOG_TYPE="wire"
      }
      COORD (220,280)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 47,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 46
      ALIGN 6
      RECT (95,255,205,309)
    }
    PIN 48,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Enc15ctrl"
        #VERILOG_TYPE="wire"
      }
      COORD (220,320)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 49,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 48
      ALIGN 6
      RECT (95,295,205,349)
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (106,15,130,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 4
      ORIENTATION 5
    }
    PIN 50,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home133ctrl"
        #VERILOG_TYPE="wire"
      }
      COORD (220,360)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 51,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 50
      ALIGN 6
      RECT (95,335,205,389)
    }
    PIN 52,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home15ctrl"
        #VERILOG_TYPE="wire"
      }
      COORD (220,400)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 53,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 52
      ALIGN 6
      RECT (95,375,205,429)
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (220,120)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (58,110,205,134)
      ALIGN 6
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 2
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Mclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,55)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000035 40 10562 1071701086410 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071701074"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 54
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,121,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,110,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,139,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,128,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 10729 1071701107785 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071701107"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 3978 1071702309895 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071702309910 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071702309926 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6918 1071702309941 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071700928"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 73
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071702309957 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071702310098 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 2642 1071702310113 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3595 1071702310129 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (158,148,186,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000035 40 10729 1071702310457 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071701107"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1071702310473 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7012 1071767148075 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071700928"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 73
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6918 1071767364575 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071700928"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 73
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7385 1071767391075 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071767391"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 76
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="Address(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071767659278 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071767659294 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071767659325 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071767659341 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7479 1071767659356 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071767391"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 76
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="Address(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071768333185 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071768333200 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071768333216 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071768333231 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7437 1071768333247 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071767391"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 76
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="Address(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000037 40 269 1071768865060 const8
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,160,60)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,160,60)
  }
 }
}
I 000037 40 769 1071768887794 const8
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071768887"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,160,60)
  FREEID 5
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,160,60)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,116,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="Const8(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000037 40 769 1071768899325 const8
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071768887"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,160,60)
  FREEID 5
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,160,60)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,116,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="Const8(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7437 1071769243872 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071767391"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 76
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="Address(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6970 1071769248856 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071769252950 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071769252966 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071769252981 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071769252997 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6970 1071769253013 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 271 1071769555044 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
 }
}
I 000042 40 5320 1071769702825 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769702"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,86,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,86,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5320 1071769841419 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769702"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,86,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,86,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3356 1071770333185 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071609892"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,214,132,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 15
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,247,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (120,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Enable1"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="RF1"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000039 40 3441 1071770343497 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071770343"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,225,132,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 15
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,258,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (120,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Enable"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RF"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000038 40 2799 1071770435310 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071770435325 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 3770 1071770435341 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071770343"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,225,132,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 15
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,258,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (120,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Enable"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RF"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000042 40 5320 1071770435356 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769702"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,86,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,86,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3623 1071771232106 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071770343"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,225,132,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 15
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,258,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (120,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Enable"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RF"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000039 40 3222 1071771257216 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771257"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000038 40 2799 1071771261388 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071771261403 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 3222 1071771261419 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771257"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000042 40 5320 1071771261420 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769702"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,86,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,86,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5660 1071771388888 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769702"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,86,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,86,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 5694 1071771398419 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771398"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,68,-34,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,148,-34,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (-120,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000038 40 2799 1071771431513 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071771431514 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 3222 1071771431528 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771257"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000042 40 5741 1071771431544 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771398"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,68,-34,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,148,-34,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (-120,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 5720 1071772545841 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771398"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,68,-34,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,148,-34,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (-120,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RF2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 5273 1071772585810 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071772608622 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071772608638 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 3222 1071772608653 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771257"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000042 40 5273 1071772608654 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3222 1071772768138 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071771257"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,235,114,285)
   ALIGN 9
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 8
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="home"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000039 40 2800 1071772774419 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772774"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000038 40 2799 1071772779247 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071772779263 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 2800 1071772779278 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772774"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000042 40 5273 1071772779294 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071773114372 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071773114373 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071773114388 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4157 1071773114403 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687217"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 33
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6970 1071773114419 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071773114560 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071773114575 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000039 40 2800 1071773114576 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772774"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000042 40 5273 1071773114591 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10729 1071773114778 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071701107"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1071773114810 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5349 1071773240419 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071773240"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,240,440)
    FREEID 37
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,240,440)
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (15,150,162,174)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (15,70,178,94)
      ALIGN 4
      MARGINS (1,1)
      PARENT 16
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (15,110,178,134)
      ALIGN 4
      MARGINS (1,1)
      PARENT 18
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="CountOut(7:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,240)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-20,0),(-10,-10),(0,0))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      RECT (104,230,225,254)
      ALIGN 6
      MARGINS (1,1)
      PARENT 20
    }
    PIN 23,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LABEL="Bus In"
        #MODIFIED="1"
        #NAME="ADDR(7:0)"
        #NUMBER="1"
        #SIDE="right"
      }
      COORD (240,320)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 24,0,0
    {
      TEXT "$#NAME"
      RECT (131,308,227,332)
      ALIGN 6
      MARGINS (1,1)
      PARENT 23
    }
    PIN 26,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="RD"
        #NUMBER="2"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,180)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 27,0,0
    {
      TEXT "$#NAME"
      RECT (197,168,227,192)
      ALIGN 6
      MARGINS (1,1)
      PARENT 26
    }
    PIN 31,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="AS"
        #NUMBER="3"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,200)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 32,0,0
    {
      TEXT "$#NAME"
      RECT (199,188,227,212)
      ALIGN 6
      MARGINS (1,1)
      PARENT 31
    }
    PIN 33,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder2"
        #VERILOG_TYPE="wire"
      }
      COORD (0,200)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 34,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 33
      ALIGN 4
      RECT (15,175,135,229)
    }
    PIN 35,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WR"
        #VERILOG_TYPE="wire"
      }
      COORD (0,240)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 36,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 35
      ALIGN 4
      RECT (15,215,135,269)
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000038 40 4650 1071773252997 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071773240"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 37
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,230,50,254)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 4692 1071773260216 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071773260"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000041 40 3978 1071774284247 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071774284263 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071774284278 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6970 1071774284294 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4692 1071774284310 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071773260"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000035 40 10729 1071774325294 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071701107"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (58,110,205,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 10326 1071774333575 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774333"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1071774341122 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 11125 1071774341138 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774333"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 4692 1071774707231 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071773260"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (104,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="CountOut(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 4688 1071774724731 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000041 40 3978 1071774730919 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071774730920 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071774730935 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6970 1071774730950 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5111 1071774730966 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2800 1071774777575 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772774"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000038 40 2799 1071774777576 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071774777591 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000042 40 5273 1071774777606 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071775504716 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071775504731 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071775504747 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6970 1071775504763 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4922 1071775504778 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000041 40 3978 1071775690372 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071775690388 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071775690389 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6970 1071775690403 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4922 1071775690419 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2800 1071775690560 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772774"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000038 40 2799 1071775690575 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3233 1071775690591 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071687311"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 31
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
 }
}
I 000042 40 5273 1071775690606 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2445 1071775690731 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10768 1071775690747 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774333"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 4035 1071776065169 holdreg
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1071776065"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,200,960)
    FREEID 23
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,200,960)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (120,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      RECT (106,15,130,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 10
      ORIENTATION 5
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="out(7:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (200,400)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (118,390,185,414)
      ALIGN 6
      MARGINS (1,1)
      PARENT 16
    }
    PIN 19,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #FAMILY="Fub"
        #MODIFIED="1"
        #NAME="ADDR(7:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (200,620)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RD"
        #NUMBER="0"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,260)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 20,0,0
    {
      TEXT "$#NAME"
      RECT (90,608,186,632)
      ALIGN 6
      MARGINS (1,1)
      PARENT 19
    }
    PIN 21,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="AS"
        #VERILOG_TYPE="wire"
      }
      COORD (0,900)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 22,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 21
      ALIGN 4
      RECT (15,875,115,929)
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (155,250,185,274)
      ALIGN 6
      MARGINS (1,1)
      PARENT 2
      ORIENTATION 2
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="ch0in(23:0)"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,140)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (15,130,112,154)
      ALIGN 4
      MARGINS (1,1)
      PARENT 4
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="ch1in(23:0)"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,860)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (15,850,112,874)
      ALIGN 4
      MARGINS (1,1)
      PARENT 8
    }
  }
}
I 000039 40 3493 1071776070981 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776065"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 23
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,890,43,914)
   ALIGN 4
   MARGINS (1,1)
   PARENT 21
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (0,900)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 3535 1071776075731 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776075"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2800 1071776087075 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772774"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000038 40 2799 1071776087076 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 5273 1071776087091 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3535 1071776087106 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776075"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 6970 1071777178153 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071769248"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7060 1071777190466 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777190"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071777195169 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071777195170 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071777195185 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 4922 1071777195200 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 7060 1071777195216 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777190"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 2800 1071777759091 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772774"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,300)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,38,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,15,170,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,210,83,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,130,205,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,244,152,286)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-1), (10,-1), (0,-11) )
   }
  }
 }
}
I 000039 40 2882 1071777759153 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777759"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,200,280)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (35,110,58,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,35,170,73)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,35,110,88)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (35,210,103,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (87,130,185,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,224,152,266)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,-20) )
   }
  }
 }
}
I 000038 40 2799 1071777759263 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
I 000039 40 3535 1071777759278 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776075"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5273 1071777759294 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2799 1071777765044 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071605363"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,81,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,81,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (164,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (107,210,175,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
 }
}
V 000038 40 2908 1071777765106 decode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777765"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,300)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,180,300)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,188,101,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,48,101,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,87)
   ALIGN 1
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 5
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (144,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,35,150,73)
   ALIGN 1
   MARGINS (1,1)
   PARENT 62
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (87,210,155,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  32, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="phaseB"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="phaseA"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000039 40 3535 1071777765216 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776075"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5273 1071777765217 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3535 1071777871106 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776075"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5273 1071777871122 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071778422825 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071778422841 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071778422856 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5702 1071778422872 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7060 1071778422888 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777190"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071779185997 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071779186013 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071779186028 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5660 1071779186044 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7060 1071779186060 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777190"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3535 1071779186200 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776075"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5273 1071779186216 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10768 1071779186403 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774333"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1071779186404 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071787953200 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6108 1071787953216 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (113,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3852 1071787953231 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (33,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5660 1071787953247 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7060 1071787953263 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777190"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (153,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3978 1071854594865 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071611227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,117,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4453 1071854628474 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3854 1071854642099 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071695870"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 44
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3839 1071854655849 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 45
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6109 1071854657911 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071699971"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6094 1071854666771 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7062 1071854669240 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071777190"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7047 1071854679583 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854679"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5660 1071854681068 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774724"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000038 40 5718 1071854694208 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000041 40 4453 1071854702161 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6094 1071854702177 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5718 1071854702193 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7047 1071854702208 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854679"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3839 1071854702209 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 45
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071854911411 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6094 1071854911427 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5718 1071854911443 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7047 1071854911444 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854679"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4278 1071854911458 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (7,148,126,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000041 40 4077 1071859454365 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6413 1071859454380 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (87,128,206,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
  }
 }
}
I 000038 40 5718 1071859454396 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7047 1071859454411 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854679"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4236 1071859454427 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (7,148,126,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000039 40 6392 1071859542771 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (87,128,206,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
  }
 }
}
I 000039 40 6692 1071859578318 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859578"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED=""
    #NAME="Pin1(7:0)"
    #NUMBER="12"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6510 1071859585990 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859578"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED=""
    #NAME="Pin1(7:0)"
    #NUMBER="12"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6562 1071859613724 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859613"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071859619036 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5718 1071859619052 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7047 1071859619068 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854679"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4236 1071859619083 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (7,148,126,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000039 40 6562 1071859619099 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859613"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6562 1071859652708 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859613"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6562 1071859655740 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,68,206,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  2, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071859663740 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5718 1071859663755 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7047 1071859663771 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854679"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4236 1071859663786 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (7,148,126,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000039 40 6123 1071859663802 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7047 1071859695990 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854679"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071859707536 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071859714396 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071859714411 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5718 1071859714427 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000036 40 4236 1071859714443 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (7,148,126,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000039 40 6123 1071859714458 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 5718 1071859771193 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854694"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000038 40 6186 1071859784599 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071859804302 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071859804318 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4236 1071859804333 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (7,148,126,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000038 40 6186 1071859804349 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6123 1071859804365 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3535 1071859840552 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071776075"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 24
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="out(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 4099 1071859859083 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859859"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (78,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5273 1071859868552 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4381 1071859868583 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859859"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (78,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4255 1071860222146 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859859"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (78,390,185,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (200,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3755 1071860227490 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5273 1071860230443 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3755 1071860230458 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3755 1071860254927 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860227"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1071860265224 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1071860268724 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5273 1071860268740 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5273 1071860345240 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071772585"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 61
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,68,167,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="Data(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5724 1071860384927 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860384"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 63
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,8,167,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,28,167,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (50,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 61
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5724 1071860411724 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860384"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 63
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,8,167,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,28,167,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (50,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 61
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1071860411740 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071861592786 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071861592802 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4236 1071861592818 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (7,148,126,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="outDATA(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000038 40 6186 1071861592833 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6123 1071861592849 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10768 1071861593021 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774333"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1071861593036 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5724 1071861593208 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860384"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 63
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,8,167,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,28,167,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (50,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 61
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1071861593209 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 3865 1071870197240 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1071870209630 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071870449396 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071870449411 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1071870449427 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1071870449443 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6123 1071870449444 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071874348740 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071874348755 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1071874348771 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1071874348786 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6123 1071874348802 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071875416818 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071875416819 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1071875416833 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1071875416849 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6123 1071875416865 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 271 1071878032161 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,320)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,320)
  }
 }
}
I 000042 40 7578 1071879176458 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071879176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAM1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBM1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MSD1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAM2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MSD2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBM2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7578 1071879322193 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071879176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAM1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBM1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MSD1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAM2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MSD2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBM2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000044 40 271 1071879374724 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,320)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,320)
  }
 }
}
I 000045 40 4389 1071879480380 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071879480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 45
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PA"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PB"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDN"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4389 1071879606474 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071879480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 45
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PA"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PB"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDN"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4389 1071880427318 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071879480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 45
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PA"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PB"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDN"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4846 1071880447208 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071880447"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PA"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PB"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNA"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNB"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4846 1071880451286 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071880447"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PA"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PB"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNA"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNB"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4846 1071881422115 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071880447"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PA"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PB"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNA"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNB"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4846 1071881545365 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071880447"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PA"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PB"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNA"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SHDNB"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 3494 1071881580880 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071881580"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (56,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 49
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="Hcontrol(3:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 3494 1071881587693 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071881580"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (56,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 49
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="Hcontrol(3:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 3494 1071885980786 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071881580"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (56,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 49
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="Hcontrol(3:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4845 1071886015286 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886015"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4845 1071886020161 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886015"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7578 1071886246974 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071879176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (133,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAM1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBM1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MSD1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAM2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MSD2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBM2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1071886321505 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 4845 1071886325458 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886015"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1071886327880 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071886327896 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1071886327911 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1071886327927 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6123 1071886327943 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1071886327958 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 5176 1071886433068 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886015"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 75
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,62,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  70, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,73,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 69
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  69, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="fBRK1"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000045 40 4798 1071886442661 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886442"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 75
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  70, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,62,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 69
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  69, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000045 40 4798 1071886448724 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886442"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 75
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,63,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,50,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,65,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,108,167,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,148,167,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  70, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,62,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 69
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  69, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000045 40 4863 1071886448802 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886448"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 75
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,160,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,34,92,87)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,34,132,74)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,128,83,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,148,70,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,168,85,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,88,147,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,108,147,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,128,147,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,148,147,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  70, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,88,82,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 69
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  69, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
 }
}
I 000041 40 4077 1071886922646 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1071886922661 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1071886922677 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1071886922693 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6123 1071886922708 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,220,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,220,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,108,206,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (179,8,207,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (177,28,207,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (172,48,207,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,8,38,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,48,25,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,38,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,23,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,108,25,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,128,207,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (220,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (220,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-40,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1071886922724 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6105 1072115509531 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859655"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,220)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,220)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7003 1072115532406 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072115532"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,220)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,220)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072115566953 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072115566969 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072115567000 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072115567016 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072115567047 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7003 1072115567048 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072115532"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,220)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,220)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7003 1072116112750 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072115532"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,220)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,220)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7919 1072116134063 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116134"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,220)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,220)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072116137500 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072116137516 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072116137531 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072116137547 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072116137563 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7919 1072116137564 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116134"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,220)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,220)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7922 1072116904719 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116134"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,220)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,220)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="BUS4202(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8824 1072116926610 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116926"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="BUS4202(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072116929656 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072116929672 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072116929688 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072116929689 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072116929703 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8824 1072116929719 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116926"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="BUS4202(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8824 1072116975844 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116926"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="BUS4202(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072116990188 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072116994313 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072116994328 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 51
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072116994344 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072116994360 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072116994375 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072116994391 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072118371516 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072118371531 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072118371547 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072118371548 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072118371563 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072118371578 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 271 1072127050063 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,200)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,200)
  }
 }
}
I 000042 40 3982 1072127221938 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127221"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 40
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3982 1072127242172 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127221"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 40
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072127282094 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127282"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 53
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072127289719 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127282"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 53
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072133127828 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072133127844 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072133127860 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072133127875 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072133127891 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072133127906 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127282"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 53
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072133127922 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072133238344 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072133238360 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072133238375 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072133238391 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072133238406 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072133238422 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127282"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 53
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072133238438 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072135735078 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072135735094 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072135735110 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072135735125 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072135735141 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072135735156 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127282"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 53
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072135735172 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10768 1072135735563 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774333"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1072135735594 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072140992344 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072127282"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 53
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072141006828 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141006"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 54
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072141010969 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072141010985 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072141011000 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072141011016 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072141011031 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072141011047 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072141011048 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141006"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 54
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5338 1072141497172 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141006"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 54
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072141534797 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141534"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 66
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,128,92,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-40,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7516 1072141567953 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859707"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-100,0,260,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,68,246,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,88,246,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,8,14,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,28,3,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,48,-4,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,68,-15,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,88,27,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,108,16,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,128,9,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-86,148,-2,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7604 1072141568016 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141568"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,0,240,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (119,68,226,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,88,226,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,87)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,34,152,74)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,8,227,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,28,227,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (192,48,227,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,8,34,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,48,16,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,5,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,47,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,108,36,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,29,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,148,18,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,128,227,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #LENGTH="20"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000041 40 4077 1072141568141 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072141568156 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072141568172 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072141568173 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072141568188 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072141568203 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141534"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 66
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,128,92,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-40,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072141909203 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141534"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,-60,120,200)
  FREEID 66
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,68,33,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,88,33,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,128,92,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-40,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-40,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072141915953 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141915"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072141918375 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141915"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072141922875 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072141926281 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072141926297 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072141926313 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072141926328 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072141926344 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072141926345 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072142227781 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072142227797 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072142227813 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072142227828 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072142227829 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072142227844 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072142352906 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000036 40 4331 1072142352907 gpio
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071870209"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,140,200)
  FREEID 69
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,140,200)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (30,88,126,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (19,108,126,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 5
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,28,127,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (97,48,127,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  38, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,68,127,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,128,125,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 42
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (8,148,127,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  8, 0, 0
  {
   COORD (140,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-1,-10), (-1,10), (-11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (140,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  17, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  22, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (140,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (140,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  37, 0, 0
  {
   COORD (140,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  42, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (140,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072142352922 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072142352938 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072142352953 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072142352969 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7604 1072218614496 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1072218614"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,0,240,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (119,68,226,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,88,226,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,87)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,34,152,74)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,8,227,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,28,227,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (192,48,227,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,8,34,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,48,16,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,5,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,47,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,108,36,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,29,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,148,18,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,128,227,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #LENGTH="20"
    #NAME="inDATA(3:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="outDATA(3:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000042 40 5724 1072218888012 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860384"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 63
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,8,167,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,28,167,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (50,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 61
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5257 1072218896465 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072218896"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,8,167,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,28,167,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (50,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1072218906606 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5257 1072218906637 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072218896"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-120,0,180,220)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-120,0,180,220)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,8,167,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,28,167,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (50,128,157,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,48,-53,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,128,-53,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (71,168,167,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-106,168,41,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (-120,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (-120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5237 1072218951543 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072218896"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 64
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6149 1072219036856 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219036"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1072219043371 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6149 1072219043372 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219036"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1072219202371 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6149 1072219202387 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219036"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072219405778 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072219405793 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072219405809 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072219405840 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072219405856 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072219519856 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072219519871 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072219519872 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072219519887 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072219519903 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10768 1072219597387 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071774333"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,230,195,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (220,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="GPIO(12:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 10327 1072219602121 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219602"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1072219606481 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10327 1072219606496 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219602"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 271 1072290988643 fub1
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
 }
}
I 000036 40 3068 1072291064096 fub1
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291064"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 35
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072291091908 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291064"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 35
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072291168658 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291064"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 35
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072291176315 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072291235908 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072291235924 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072291235940 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072291235971 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072291235986 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072291236002 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 271 1072291616018 fub1
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,100)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,100)
  }
 }
}
I 000036 40 6709 1072291799018 fub1
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291799"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,-80,280,80)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,-80,280,80)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,-72,65,-48)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,-52,71,-28)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,-32,71,-8)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,-12,65,12)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,87,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,97,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,-66,172,-31)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,-66,192,-36)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,-66,212,-38)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,-66,132,-26)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,-66,152,-13)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,-40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,-20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6709 1072291817080 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291799"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,-80,280,80)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,-80,280,80)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,-72,65,-48)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,-52,71,-28)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,-32,71,-8)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,-12,65,12)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,87,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,97,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,-66,172,-31)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,-66,192,-36)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,-66,212,-38)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,-66,132,-26)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,-66,152,-13)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,-40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,-20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,-80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6895 1072292132315 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291799"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 70
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (13,108,109,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (13,148,120,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 2
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (215,8,266,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
   ORIENTATION 2
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (209,28,260,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 2
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (209,48,260,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (215,68,266,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (215,88,266,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (193,108,266,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (183,128,266,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
   ORIENTATION 2
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 7
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 7
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 7
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 7
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 7
  }
  PIN  3, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (280,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (280,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (280,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6891 1072292139158 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (13,48,109,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (13,88,120,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 2
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (215,8,266,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
   ORIENTATION 2
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (209,28,260,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 2
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (209,48,260,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (215,68,266,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (215,88,266,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (193,108,266,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (183,128,266,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 43
   ORIENTATION 2
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 7
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 7
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 7
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 7
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 7
  }
  PIN  3, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (280,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (280,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (280,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072292358596 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1072292358611 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072292358627 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072292358643 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072292358658 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072292358674 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072292358690 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072295291783 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1072295291861 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072295291877 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072295291893 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072295291908 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072295291940 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072295291971 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072295516080 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1072295516096 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072295516111 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072295516127 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072295516143 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072295516158 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072295516159 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072296958049 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072291176"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(7:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072296965486 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072296969486 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1072296969502 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072296969518 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072296969533 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072296969549 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072296969565 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072296969580 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072297444018 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1072297444033 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072297444049 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072297444065 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072297444080 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072297444096 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072297444097 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1072297457533 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1072297457549 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1072297457565 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1072297457580 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1072297457596 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1072297457611 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1072297457627 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1073342649539 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1073342649586 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1073342649617 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1073342649648 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1073342649680 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1073342649711 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1073342649742 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074616401431 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074616401494 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074616401541 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074616401572 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074616401588 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1074616401619 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074616401635 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074810836343 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1074810836437 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074810836453 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074810836468 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074810836500 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074810836515 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074810836531 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074811996687 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1074811996703 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074811996718 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074811996734 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074811996750 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074811996765 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074811996781 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074812029062 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1074812029078 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074812029093 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074812029109 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074812029125 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074812029140 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074812029156 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4077 1074866269868 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071854628"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 46
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4489 1074866294431 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074866319696 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074866319728 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074866319743 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074866319790 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074866319806 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074866319821 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4912 1074866319837 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074869810946 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074869810962 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074869810978 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074869810993 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074869811009 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074869811025 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074869811040 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074869816275 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074869816290 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074869816306 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074869816321 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074869816337 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074869816353 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074869816368 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074870500493 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074870500509 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074870500525 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074870500540 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074870500556 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074870500571 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074870500587 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074870508790 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074870508806 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074870508821 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074870508837 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074870508853 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074870508868 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074870508884 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074870675212 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074870675228 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074870675259 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074870675260 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074870675275 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074870675290 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074870675306 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074870788868 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074870788884 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074870788900 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074870788915 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074870788931 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074870788946 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074870788962 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074870884400 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074870884415 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074870884431 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074870884446 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074870884462 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074870884478 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074870884493 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074870942025 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074870942040 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074870942056 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074870942071 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074870942087 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074870942103 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074870942118 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074871010040 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074871010056 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074871010071 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074871010087 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074871010088 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074871010103 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074871010118 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074871012025 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074871012040 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074871012056 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074871012071 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074871012087 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074871012103 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074871012118 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074873819650 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074873819665 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074873819681 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074873819696 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074873819712 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074873819728 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074873819743 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074873828400 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074873828415 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074873828431 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074873828446 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074873828447 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074873828462 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074873828478 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074874519743 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074874519759 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074874519775 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074874519790 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074874519806 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074874519821 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074874519822 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 271 1074876965134 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 2
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
 }
}
I 000041 40 3659 1074877030103 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074877030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 40
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,54,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="5"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 6689 1074878073915 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072292139"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 71
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7107 1074878099853 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878099"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 73
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7107 1074878116150 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878099"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 73
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,48,267,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7107 1074878122087 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878122"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7154 1074878288962 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878122"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074878288978 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074878288979 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074878288993 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074878289009 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074878289025 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074878289040 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3659 1074878289056 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074877030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 40
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,54,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="5"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3659 1074878402759 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074877030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 40
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,54,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="5"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3711 1074878426743 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878426"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,70,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,54,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct8"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3899 1074878432150 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878426"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,70,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,54,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct8"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3068 1074880138962 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072296965"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 36
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880168134 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880168"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3711 1074880176884 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878426"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,70,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,54,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct8"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880176900 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880168"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074880176915 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878122"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074880176931 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074880176946 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074880176962 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074880176978 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074880176993 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3711 1074880473712 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878426"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,70,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,54,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct8"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="6"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3763 1074880486525 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880486"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,69,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3904 1074880491384 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880486"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,69,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880491400 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880168"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074880491415 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878122"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074880491431 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074880491446 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074880491462 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074880491478 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074880491493 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8915 1074880863228 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072116990"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074880885821 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3841 1074880899025 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880486"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,69,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074880899040 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880899056 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880168"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074880899071 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878122"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074880899087 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074880899103 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074880899118 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074880899134 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880910290 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880168"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880921540 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074880926556 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074878122"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,72)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074880935150 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3841 1074880938525 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880486"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,69,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074880938540 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074880938556 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880938571 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074880938587 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074880938603 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074880938618 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074880938634 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3841 1074880975712 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880486"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,69,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3841 1074880983353 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880983"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3841 1074880986759 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880983"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074880986775 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074880986790 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074880986806 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074880986821 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074880986837 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074880986853 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074880986868 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3841 1074881072525 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880983"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,54,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin7"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3844 1074881084493 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881084"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3844 1074881087743 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881084"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074881087759 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074881087775 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074881087790 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074881087806 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074881087821 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074881087837 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074881087853 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8422 1074881231025 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881231"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 84
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,0,240,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (119,68,226,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,88,226,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,87)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,34,152,74)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,8,227,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,28,227,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (192,48,227,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,8,34,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,48,16,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,5,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,47,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,108,36,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,29,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,148,18,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,128,227,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (192,148,237,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (187,168,237,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #LENGTH="20"
    #NAME="inDATA(3:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="outDATA(3:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  77, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="Rslct"
    #NUMBER="15"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="Wslct"
    #NUMBER="16"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000041 40 3844 1074881394400 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881084"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,54,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin8"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3870 1074881406728 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881406"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074881409790 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074881409806 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 3870 1074881409821 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881406"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074881409837 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074881409853 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074881409868 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074881409884 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074881409900 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 8424 1074881465196 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881465"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,0,240,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (119,68,226,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,88,226,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,87)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,34,152,74)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,8,227,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,28,227,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (192,48,227,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,8,34,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,48,16,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,5,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,47,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,108,36,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,29,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,148,18,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,128,227,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,148,237,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (173,168,237,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #LENGTH="20"
    #NAME="inDATA(3:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="outDATA(3:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  77, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000041 40 3870 1074881752384 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881406"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 41
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4321 1074881762853 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881762"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4321 1074881767603 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881762"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074881767618 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074881767634 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074881767650 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074881767665 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074881767681 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074881767696 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074881767712 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5802 1074881947415 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072141922"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6711 1074882007025 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (43,168,107,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4321 1074882021493 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881762"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6711 1074882021509 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-80,-60,120,200)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,-60,120,200)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,28,107,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,48,107,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (11,8,107,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,88,107,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-12,-46,12,7)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,-46,72,-6)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,-7,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,-7,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (74,128,107,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,52,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (43,168,107,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  PIN  3, 0, 0
  {
   COORD (120,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (60,-60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (-80,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (-80,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (120,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (-80,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (120,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074882021525 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074882021540 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074882021556 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074882021571 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074882021587 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074882021603 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6713 1074882391665 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074882411962 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4321 1074882414946 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881762"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074882414962 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074882414978 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074882414993 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074882415009 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074882415025 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074882415040 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074882415056 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4321 1074882465900 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074881762"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 43
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 5677 1074882513009 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882512"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 56
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,70,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct6"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 5677 1074882528571 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882512"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 56
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,70,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct6"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 5677 1074882534634 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882534"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 57
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074882542056 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074882542071 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074882542087 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 5677 1074882542103 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882534"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 57
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074882542118 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074882542134 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074882542150 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074882542165 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074882624165 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071859784"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074882629915 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882629"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,440)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,440)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 6186 1074882705665 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882629"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,240,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,150,162,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,178,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,178,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,190,162,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,177,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,177,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8954 1074882847525 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882847"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 102
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,448,227,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,428,227,452)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,408,227,432)
   ALIGN 6
   MARGINS (1,1)
   PARENT 85
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,388,227,412)
   ALIGN 6
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,368,227,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 100
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  90, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  95, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  100, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 5677 1074882889493 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882534"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 57
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 5677 1074882897821 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882534"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,260)
  FREEID 57
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,260)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8077 1074882937868 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882937"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 84
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,54,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,54,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,54,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,54,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,54,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,54,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin1"
    #NUMBER="13"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin2"
    #NUMBER="14"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin3"
    #NUMBER="15"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin4"
    #NUMBER="16"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="17"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="18"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4207 1074883019275 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071860265"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074883077993 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074883077"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 47
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6149 1074883251728 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219036"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074883251743 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074883077"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 47
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074883255650 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074883255665 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8077 1074883255681 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882937"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 84
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,54,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,54,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,54,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,54,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,54,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,54,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin1"
    #NUMBER="13"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin2"
    #NUMBER="14"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin3"
    #NUMBER="15"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin4"
    #NUMBER="16"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="17"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="18"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074883255696 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074883255712 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074883255728 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074883255743 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8954 1074883255759 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882847"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 102
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,448,227,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,428,227,452)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,408,227,432)
   ALIGN 6
   MARGINS (1,1)
   PARENT 85
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,388,227,412)
   ALIGN 6
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,368,227,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 100
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  90, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  95, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  100, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8077 1074885753368 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882937"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 84
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,54,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,54,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,54,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,54,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,54,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,54,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin1"
    #NUMBER="13"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin2"
    #NUMBER="14"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin3"
    #NUMBER="15"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin4"
    #NUMBER="16"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="17"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="18"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8077 1074885763821 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074885763"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,54,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,54,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,54,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,54,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,54,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,54,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin1"
    #NUMBER="13"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin2"
    #NUMBER="14"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin3"
    #NUMBER="15"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin4"
    #NUMBER="16"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="17"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="18"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8077 1074885956868 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074885763"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,54,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,54,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,54,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,54,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,54,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,54,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin1"
    #NUMBER="13"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin2"
    #NUMBER="14"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin3"
    #NUMBER="15"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin4"
    #NUMBER="16"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin5"
    #NUMBER="17"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="Pin6"
    #NUMBER="18"
    #SIDE="left"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1074886007212 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074886010915 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074886010931 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074886010946 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1074886010962 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074886010978 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074886010993 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074886011009 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8954 1074886011025 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882847"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 102
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,448,227,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,428,227,452)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,408,227,432)
   ALIGN 6
   MARGINS (1,1)
   PARENT 85
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,388,227,412)
   ALIGN 6
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,368,227,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 100
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  90, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  95, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  100, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6149 1074886182353 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219036"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 83
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1074886207696 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1074886242509 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886242525 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074883077"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 47
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1074886414446 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886414462 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074883077"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 47
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1074886470368 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886470384 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074883077"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 47
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886672212 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074883077"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 47
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886696915 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1074886702009 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886702025 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1074886753712 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886753728 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1074886980056 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1074886980071 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 12306 1074886993915 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1074886993"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (-40,0,240,780)
    FREEID 114
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (-40,0,240,779)
    }
    PIN 100,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="WRslct1"
        #NUMBER="10"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,360)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 101,0,0
    {
      TEXT "$#NAME"
      RECT (152,348,227,372)
      ALIGN 6
      MARGINS (1,1)
      PARENT 100
    }
    PIN 102,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct1"
        #VERILOG_TYPE="wire"
      }
      COORD (-40,420)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 103,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 102
      ALIGN 4
      RECT (-25,395,115,449)
    }
    PIN 104,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct2"
        #VERILOG_TYPE="wire"
      }
      COORD (-40,460)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 105,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 104
      ALIGN 4
      RECT (-25,435,115,489)
    }
    PIN 106,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct3"
        #VERILOG_TYPE="wire"
      }
      COORD (-40,500)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 107,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 106
      ALIGN 4
      RECT (-25,475,115,529)
    }
    PIN 108,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct4"
        #VERILOG_TYPE="wire"
      }
      COORD (-40,540)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 109,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 108
      ALIGN 4
      RECT (-25,515,115,569)
    }
    PIN 110,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct5"
        #VERILOG_TYPE="wire"
      }
      COORD (-40,580)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 111,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 110
      ALIGN 4
      RECT (-25,555,115,609)
    }
    PIN 112,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WRslct"
        #VERILOG_TYPE="wire"
      }
      COORD (-40,620)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 113,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 112
      ALIGN 4
      RECT (-25,595,115,649)
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (-25,150,122,174)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (-25,70,138,94)
      ALIGN 4
      MARGINS (1,1)
      PARENT 16
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (-25,110,138,134)
      ALIGN 4
      MARGINS (1,1)
      PARENT 18
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LABEL="Bus In"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="inDATA(7:0)"
        #NUMBER="0"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,240)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      RECT (118,230,225,254)
      ALIGN 6
      MARGINS (1,1)
      PARENT 20
    }
    PIN 23,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LABEL="Bus In"
        #MODIFIED="1"
        #NAME="ADDR(7:0)"
        #NUMBER="1"
        #SIDE="right"
      }
      COORD (240,280)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 24,0,0
    {
      TEXT "$#NAME"
      RECT (131,268,227,292)
      ALIGN 6
      MARGINS (1,1)
      PARENT 23
    }
    PIN 26,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="RD"
        #NUMBER="2"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,180)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 27,0,0
    {
      TEXT "$#NAME"
      RECT (197,168,227,192)
      ALIGN 6
      MARGINS (1,1)
      PARENT 26
    }
    PIN 31,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="AS"
        #NUMBER="3"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,200)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 32,0,0
    {
      TEXT "$#NAME"
      RECT (199,188,227,212)
      ALIGN 6
      MARGINS (1,1)
      PARENT 31
    }
    PIN 33,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder2"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,200)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 34,0,0
    {
      TEXT "$#NAME"
      RECT (-25,190,122,214)
      ALIGN 4
      MARGINS (1,1)
      PARENT 33
    }
    PIN 35,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WR"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,160)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 36,0,0
    {
      TEXT "$#NAME"
      RECT (190,150,225,174)
      ALIGN 6
      MARGINS (1,1)
      PARENT 35
      ORIENTATION 2
    }
    PIN 38,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #FAMILY="Fub"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder2"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,300)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 39,0,0
    {
      TEXT "$#NAME"
      RECT (-26,288,137,312)
      ALIGN 4
      MARGINS (1,1)
      PARENT 38
    }
    PIN 44,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #FAMILY="Fub"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder2"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,380)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 45,0,0
    {
      TEXT "$#NAME"
      RECT (-26,368,137,392)
      ALIGN 4
      MARGINS (1,1)
      PARENT 44
    }
    PIN 47,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LABEL="Bus Out"
        #MODIFIED="1"
        #NAME="outDATA(7:0)"
        #NUMBER="4"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,320)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 48,0,0
    {
      TEXT "$#NAME"
      RECT (108,308,227,332)
      ALIGN 6
      MARGINS (1,1)
      PARENT 47
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 75,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="WRslct5"
        #NUMBER="5"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,460)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 76,0,0
    {
      TEXT "$#NAME"
      RECT (152,448,227,472)
      ALIGN 6
      MARGINS (1,1)
      PARENT 75
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    PIN 80,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="WRslct4"
        #NUMBER="6"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,440)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 81,0,0
    {
      TEXT "$#NAME"
      RECT (152,428,227,452)
      ALIGN 6
      MARGINS (1,1)
      PARENT 80
    }
    PIN 85,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="WRslct3"
        #NUMBER="7"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,420)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 86,0,0
    {
      TEXT "$#NAME"
      RECT (152,408,227,432)
      ALIGN 6
      MARGINS (1,1)
      PARENT 85
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
    PIN 90,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="WRslct2"
        #NUMBER="8"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,400)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 91,0,0
    {
      TEXT "$#NAME"
      RECT (152,388,227,412)
      ALIGN 6
      MARGINS (1,1)
      PARENT 90
    }
    PIN 95,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="RDslct"
        #NUMBER="9"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,380)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 96,0,0
    {
      TEXT "$#NAME"
      RECT (168,368,227,392)
      ALIGN 6
      MARGINS (1,1)
      PARENT 95
    }
  }
}
I 000039 40 10712 1074887009962 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886993"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,780)
  FREEID 114
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,779)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,448,227,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,428,227,452)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,408,227,432)
   ALIGN 6
   MARGINS (1,1)
   PARENT 85
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,388,227,412)
   ALIGN 6
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,368,227,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,348,227,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 100
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,410,45,434)
   ALIGN 4
   MARGINS (1,1)
   PARENT 102
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,450,45,474)
   ALIGN 4
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,490,45,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 106
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,530,45,554)
   ALIGN 4
   MARGINS (1,1)
   PARENT 108
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,570,45,594)
   ALIGN 4
   MARGINS (1,1)
   PARENT 110
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,610,39,634)
   ALIGN 4
   MARGINS (1,1)
   PARENT 112
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  75, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  85, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct3"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  95, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  100, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (-40,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (-40,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (-40,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (-40,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (-40,580)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (-40,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 8507 1074887051665 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074887051"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 9371 1074887143478 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074887143493 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074887143509 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1074887143525 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074887143540 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074887143556 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074887143571 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8507 1074887143587 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074887051"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 9371 1074889336384 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074889336400 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074889336415 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1074889336431 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074889336446 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074889336462 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074889336478 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8871 1074889336493 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074887051"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 9371 1074889711212 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074889711228 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1074889711243 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1074889711259 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074889711275 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074889711290 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074889711306 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8871 1074889711321 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074887051"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 3520 1074892647728 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1074892647743 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1074892647759 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1074892647775 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1074892647790 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1074892647806 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8871 1074892647821 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074887051"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000041 40 8389 1074892647837 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 10327 1075045877735 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1072219602"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,15,130,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 18
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Aclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SMclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000034 40 9498 1075045885485 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075045885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000034 40 9498 1075045896126 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075045885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 2445 1075045896141 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000034 40 9498 1075046619266 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075045885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 55
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,532,94,585)
   ALIGN 9
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 8
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (80,600)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="bottom"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000035 40 10179 1075046624001 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075046623"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,600)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,600)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
 }
}
I 000035 40 10181 1075046834720 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075046623"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1200)
  FREEID 67
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
 }
}
I 000035 40 24457 1075047148516 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047148"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 185
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (59,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (101,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc133FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc15FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home133FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home15FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc133ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc15ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home133ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home15ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24457 1075047154610 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047148"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 185
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (59,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (101,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc133FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc15FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home133FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home15FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc133ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc15ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home133ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home15ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2445 1075047154626 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24457 1075047186079 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047148"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 185
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (59,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (70,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (101,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc133FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc15FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home133FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home15FLG_1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc133ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Enc15ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home133ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="Home15ctrl_1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24637 1075047238126 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047238"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrll"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24637 1075047244157 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047238"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrll"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2445 1075047244173 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24637 1075047265141 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047238"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrll"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24636 1075047290720 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047290"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24636 1075047293470 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047290"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2445 1075047293485 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 24688 1075047402251 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047290"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 55
   ORIENTATION 5
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,76)
   ALIGN 1
   MARGINS (1,1)
   PARENT 61
   ORIENTATION 5
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  55, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_2"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="Mclk_3"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,10), (10,10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 23933 1075047409954 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047409"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 23933 1075047420938 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047409"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2445 1075047420939 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 23933 1075130334298 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047409"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 23933 1075130348579 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075130348"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1075130574657 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075130574704 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1075130574735 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1075130574751 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8871 1075130574782 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074887051"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 7172 1075130574813 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1075130574829 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075130574860 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 2445 1075130867516 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000035 40 23933 1075130867532 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075047409"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000035 40 23933 1075131243032 u4
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075130348"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,1320)
  FREEID 186
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,1320)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,350,43,374)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,150,205,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,190,205,214)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
   ORIENTATION 2
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,370,45,394)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,490,68,514)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,390,50,414)
   ALIGN 4
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  23, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,330,93,354)
   ALIGN 4
   MARGINS (1,1)
   PARENT 22
   ORIENTATION 2
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,30,205,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 2
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,530,205,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 2
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,70,205,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
   ORIENTATION 2
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (141,490,205,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
   ORIENTATION 2
  }
  TEXT  35, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,50,205,74)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
   ORIENTATION 2
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,510,205,534)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,290,205,314)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 2
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,330,205,354)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
   ORIENTATION 2
  }
  TEXT  43, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,370,205,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 42
   ORIENTATION 2
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,410,205,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 44
   ORIENTATION 2
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,270,205,294)
   ALIGN 6
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,310,205,334)
   ALIGN 6
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  51, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,350,205,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 50
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,390,205,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (99,610,205,634)
   ALIGN 6
   MARGINS (1,1)
   PARENT 64
   ORIENTATION 2
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (110,650,205,674)
   ALIGN 6
   MARGINS (1,1)
   PARENT 66
   ORIENTATION 2
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,690,205,714)
   ALIGN 6
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 2
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (92,730,205,754)
   ALIGN 6
   MARGINS (1,1)
   PARENT 70
   ORIENTATION 2
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,590,205,614)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (123,630,205,654)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (94,670,205,694)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (105,710,205,734)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,770,205,794)
   ALIGN 6
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 2
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (42,810,205,834)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
   ORIENTATION 2
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,868,207,892)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,888,207,912)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,908,207,932)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,928,207,952)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (156,948,207,972)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
  }
  TEXT  110, 0, 0
  {
   TEXT "$#NAME"
   RECT (134,968,207,992)
   ALIGN 6
   MARGINS (1,1)
   PARENT 109
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (130,988,207,1012)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  132, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,1028,207,1052)
   ALIGN 6
   MARGINS (1,1)
   PARENT 131
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1048,74,1072)
   ALIGN 4
   MARGINS (1,1)
   PARENT 136
  }
  TEXT  142, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1068,61,1092)
   ALIGN 4
   MARGINS (1,1)
   PARENT 141
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1088,76,1112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 146
  }
  TEXT  152, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1128,74,1152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 151
  }
  TEXT  154, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1148,61,1172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 153
  }
  TEXT  156, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,1168,76,1192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 155
  }
  TEXT  158, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1048,207,1072)
   ALIGN 6
   MARGINS (1,1)
   PARENT 157
  }
  TEXT  163, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1068,207,1092)
   ALIGN 6
   MARGINS (1,1)
   PARENT 162
  }
  TEXT  168, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1088,207,1112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 167
  }
  TEXT  173, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1108,207,1132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 172
  }
  TEXT  178, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1148,207,1172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 177
  }
  TEXT  180, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1168,207,1192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  182, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,1188,207,1212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  184, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,1208,207,1232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 183
  }
  PIN  2, 0, 0
  {
   COORD (0,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (0,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  22, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (220,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (220,540)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (220,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  32, 0, 0
  {
   COORD (220,500)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  34, 0, 0
  {
   COORD (220,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (220,520)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (220,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  40, 0, 0
  {
   COORD (220,340)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  42, 0, 0
  {
   COORD (220,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (220,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (220,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (220,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  50, 0, 0
  {
   COORD (220,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home133ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (220,400)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home15ctrl"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  64, 0, 0
  {
   COORD (220,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (220,660)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (220,700)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  70, 0, 0
  {
   COORD (220,740)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25FLG"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (220,600)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (220,640)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Enc25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  76, 0, 0
  {
   COORD (220,680)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home233ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (220,720)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home25ctrl"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  80, 0, 0
  {
   COORD (220,780)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (220,820)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED=""
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (220,880)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (220,900)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (220,920)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (220,940)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  104, 0, 0
  {
   COORD (220,960)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  109, 0, 0
  {
   COORD (220,980)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  114, 0, 0
  {
   COORD (220,1000)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwn"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  131, 0, 0
  {
   COORD (220,1040)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  136, 0, 0
  {
   COORD (0,1060)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  141, 0, 0
  {
   COORD (0,1080)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  146, 0, 0
  {
   COORD (0,1100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  151, 0, 0
  {
   COORD (0,1140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="PWM2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  153, 0, 0
  {
   COORD (0,1160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="DIR2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  155, 0, 0
  {
   COORD (0,1180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED=""
    #NAME="Brake2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  157, 0, 0
  {
   COORD (220,1060)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  162, 0, 0
  {
   COORD (220,1080)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  167, 0, 0
  {
   COORD (220,1100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  172, 0, 0
  {
   COORD (220,1120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  177, 0, 0
  {
   COORD (220,1160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAH2"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  179, 0, 0
  {
   COORD (220,1180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED=""
    #NAME="PAL2"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  181, 0, 0
  {
   COORD (220,1200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  183, 0, 0
  {
   COORD (220,1220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000035 40 2445 1075131243048 msp
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071698533"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,440)
  FREEID 26
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,220,440)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (138,148,206,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,168,206,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (176,188,206,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,208,206,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (220,160)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #FAMILY="Fub"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (220,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (220,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1075212226512 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1075212226543 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1075212588465 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1075212588528 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7059 1075215526981 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886207"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 91
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (259,8,287,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (257,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (252,48,287,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (300,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (300,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5713 1075215541262 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215541"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5713 1075215546793 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215541"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1075215546809 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 6023 1075215565840 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886696"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,250,185,274)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
   ORIENTATION 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,210,185,234)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 2
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,288,187,312)
   ALIGN 6
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  2, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  27, 0, 0
  {
   COORD (200,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4706 1075215572981 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215572"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5713 1075215596715 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215541"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4706 1075215596731 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215572"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8871 1075215635762 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074887051"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (131,268,227,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (197,168,227,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 26
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (199,188,227,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (190,150,225,174)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
   ORIENTATION 2
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (240,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  26, 0, 0
  {
   COORD (240,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  31, 0, 0
  {
   COORD (240,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (240,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000038 40 7163 1075215649231 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 4706 1075215661637 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215572"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  20, 0, 0
  {
   TEXT "$#NAME"
   RECT (90,608,186,632)
   ALIGN 6
   MARGINS (1,1)
   PARENT 19
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  19, 0, 0
  {
   COORD (200,620)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4277 1075215666340 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5713 1075215671996 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215541"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (191,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5249 1075215676621 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215676"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4277 1075215696059 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5249 1075215696075 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215676"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1075215982934 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075215982965 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7172 1075215982996 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075215983028 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1075215983043 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075215983059 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000040 40 7133 1075215983075 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1075215983106 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000039 40 6666 1075216005715 pwrctrl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216005"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-100,0,260,200)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-80,0,240,200)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (119,68,226,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,87)
   ALIGN 1
   MARGINS (1,1)
   PARENT 11
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,34,152,74)
   ALIGN 1
   MARGINS (1,1)
   PARENT 16
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,8,34,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,28,23,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,48,16,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,68,5,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,88,47,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,108,36,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  67, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,128,29,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 66
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (-66,148,18,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,128,227,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (178,148,237,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (173,168,237,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 82
  }
  PIN  2, 0, 0
  {
   COORD (260,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #LENGTH="20"
    #NAME="inDATA(3:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  11, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  36, 0, 0
  {
   COORD (-100,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33ctrl"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  41, 0, 0
  {
   COORD (-100,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5ctrl"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  46, 0, 0
  {
   COORD (-100,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33ctrl"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  51, 0, 0
  {
   COORD (-100,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5ctrl"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  56, 0, 0
  {
   COORD (-100,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home33FLG"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  61, 0, 0
  {
   COORD (-100,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Home5FLG"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  66, 0, 0
  {
   COORD (-100,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc33FLG"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  71, 0, 0
  {
   COORD (-100,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Enc5FLG"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  74, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="outDATA(3:0)"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  77, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  82, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000042 40 7172 1075216037325 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074882411"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 77
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (159,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (157,148,187,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (152,168,187,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5357 1075216046856 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1075216052809 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075216052825 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216052840 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1075216052856 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216052871 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000040 40 7133 1075216052887 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1075216052903 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5357 1075216052918 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 9371 1075216075106 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880885"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (150,108,246,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  12, 0, 0
  {
   TEXT "$#NAME"
   RECT (219,8,247,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 11
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (217,28,247,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (212,48,247,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 21
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  8, 0, 0
  {
   COORD (260,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  11, 0, 0
  {
   COORD (260,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  16, 0, 0
  {
   COORD (260,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  21, 0, 0
  {
   COORD (260,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216085434 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1075216094918 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075216094934 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216094965 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216094966 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216094981 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000040 40 7133 1075216094996 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8492 1075216095012 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5357 1075216095028 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 7133 1075216115684 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880935"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 74
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (171,68,267,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 48
   ORIENTATION 5
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,14,192,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 53
   ORIENTATION 5
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 58
   ORIENTATION 5
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,13,252,77)
   ALIGN 1
   MARGINS (1,1)
   PARENT 71
   ORIENTATION 6
  }
  PIN  3, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="10"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (180,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="11"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="12"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (240,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5615 1075216130887 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216130"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,68,266,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000040 40 5662 1075216139184 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216130"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,68,266,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000042 40 3520 1075216139200 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075216139215 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216139231 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216139246 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216139262 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 8492 1075216139278 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5357 1075216139293 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5641 1075216161512 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216130"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  75, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,68,266,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 74
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  74, 0, 0
  {
   COORD (280,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="ADDR(7:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000040 40 5274 1075216167934 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216167"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1075216171996 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075216172012 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216172028 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216172043 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216167"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216172059 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216172075 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 8492 1075216172090 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5357 1075216172106 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3520 1075216190840 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074880921"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (91,28,187,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (28,14,52,44)
   ALIGN 1
   MARGINS (1,1)
   PARENT 23
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,49)
   ALIGN 1
   MARGINS (1,1)
   PARENT 28
   ORIENTATION 5
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,42)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  8, 0, 0
  {
   COORD (200,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (40,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="6"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075216203090 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075216206856 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216206871 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216206887 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216167"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216206903 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216206918 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 8492 1075216206934 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5357 1075216206950 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075216206965 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000045 40 3932 1075216251340 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216251"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 75
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,0,160,220)
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,128,83,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,148,70,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,168,85,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,88,147,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,108,147,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,128,147,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,148,147,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  70, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,88,82,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 69
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  69, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
 }
}
I 000041 40 8389 1075216283762 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216283778 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216283793 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216167"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216283809 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216283825 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 8492 1075216283840 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1071886321"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  3, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5357 1075216283856 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075216283871 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 7865 1075216287793 pwmcontrol
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1075216287"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (-20,0,200,320)
    FREEID 93
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (-20,0,200,320)
    }
    PIN 13,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PAH1"
        #NUMBER="3"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,80)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 14,0,0
    {
      TEXT "$#NAME"
      RECT (135,68,187,92)
      ALIGN 6
      MARGINS (1,1)
      PARENT 13
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PAL1"
        #NUMBER="4"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,100)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (137,88,187,112)
      ALIGN 6
      MARGINS (1,1)
      PARENT 18
    }
    PIN 23,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PBH1"
        #NUMBER="5"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,120)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 24,0,0
    {
      TEXT "$#NAME"
      RECT (135,108,187,132)
      ALIGN 6
      MARGINS (1,1)
      PARENT 23
    }
    PIN 28,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PAH2"
        #NUMBER="6"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,220)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 29,0,0
    {
      TEXT "$#NAME"
      RECT (135,208,187,232)
      ALIGN 6
      MARGINS (1,1)
      PARENT 28
    }
    PIN 33,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PBH2"
        #NUMBER="7"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,260)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 34,0,0
    {
      TEXT "$#NAME"
      RECT (135,248,187,272)
      ALIGN 6
      MARGINS (1,1)
      PARENT 33
    }
    PIN 38,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PAL2"
        #NUMBER="8"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,240)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 39,0,0
    {
      TEXT "$#NAME"
      RECT (137,228,187,252)
      ALIGN 6
      MARGINS (1,1)
      PARENT 38
    }
    PIN 43,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="PWM1"
        #NUMBER="9"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 44,0,0
    {
      TEXT "$#NAME"
      RECT (-6,68,54,92)
      ALIGN 4
      MARGINS (1,1)
      PARENT 43
    }
    PIN 48,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="DIR1"
        #NUMBER="10"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,100)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 49,0,0
    {
      TEXT "$#NAME"
      RECT (-6,88,41,112)
      ALIGN 4
      MARGINS (1,1)
      PARENT 48
    }
    PIN 53,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="Brake1"
        #NUMBER="11"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 54,0,0
    {
      TEXT "$#NAME"
      RECT (-6,108,56,132)
      ALIGN 4
      MARGINS (1,1)
      PARENT 53
    }
    PIN 58,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="PWM2"
        #NUMBER="12"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,220)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 59,0,0
    {
      TEXT "$#NAME"
      RECT (-6,208,54,232)
      ALIGN 4
      MARGINS (1,1)
      PARENT 58
    }
    PIN 63,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="DIR2"
        #NUMBER="13"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,240)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 64,0,0
    {
      TEXT "$#NAME"
      RECT (-6,228,41,252)
      ALIGN 4
      MARGINS (1,1)
      PARENT 63
    }
    PIN 68,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="Brake2"
        #NUMBER="14"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,260)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 69,0,0
    {
      TEXT "$#NAME"
      RECT (-6,248,56,272)
      ALIGN 4
      MARGINS (1,1)
      PARENT 68
    }
    PIN 78,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="fBRK1"
        #NUMBER="16"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,40)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 79,0,0
    {
      TEXT "$#NAME"
      RECT (0,28,59,52)
      ALIGN 4
      MARGINS (1,1)
      PARENT 78
    }
    PIN 83,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LABEL="In"
        #MODIFIED="1"
        #NAME="fBRK2"
        #NUMBER="17"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (-20,180)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 84,0,0
    {
      TEXT "$#NAME"
      RECT (-6,168,53,192)
      ALIGN 4
      MARGINS (1,1)
      PARENT 83
    }
    PIN 86,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PBL1"
        #NUMBER="18"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,140)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 87,0,0
    {
      TEXT "$#NAME"
      RECT (137,128,187,152)
      ALIGN 6
      MARGINS (1,1)
      PARENT 86
    }
    PIN 91,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="PBL2"
        #NUMBER="19"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (200,280)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 92,0,0
    {
      TEXT "$#NAME"
      RECT (137,268,187,292)
      ALIGN 6
      MARGINS (1,1)
      PARENT 91
    }
  }
}
I 000042 40 6772 1075216300793 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075216300809 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216300825 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216300840 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216167"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216300856 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216300871 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5357 1075216300887 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075216300903 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075216346668 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075216346684 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216346700 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216346715 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216167"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216346731 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216346746 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5357 1075216346762 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075216346778 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216734715 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216167"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216741887 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216741"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075216746809 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075216746825 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075216746840 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075216746856 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075216746871 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5357 1075216746887 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075216746903 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216741"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075216746918 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075217143809 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216741"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075217153184 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217153"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075217157778 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075217157793 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075217157809 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075217157825 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075217157840 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217153"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075217157856 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5357 1075217157871 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075217157887 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075217185043 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075217185059 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075217185075 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075217185090 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075217185106 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217153"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075217185121 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5357 1075217185137 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075217185153 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075217227965 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217153"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075217233059 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075217237075 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075217237090 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075217237106 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075217237121 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075217237137 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7163 1075217237153 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215649"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 115
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 5357 1075217237168 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 78
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075217237169 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4277 1075217849325 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5249 1075217849340 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215676"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5249 1075217899871 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215676"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4277 1075217899887 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 8682 1075217960965 servos
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1075217960"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (-40,0,240,620)
    FREEID 118
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (-40,0,240,619)
    }
    PIN 102,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct1"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,360)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 103,0,0
    {
      TEXT "$#NAME"
      RECT (155,350,225,374)
      ALIGN 6
      MARGINS (1,1)
      PARENT 102
      ORIENTATION 2
    }
    PIN 104,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct2"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,400)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 105,0,0
    {
      TEXT "$#NAME"
      RECT (155,390,225,414)
      ALIGN 6
      MARGINS (1,1)
      PARENT 104
      ORIENTATION 2
    }
    PIN 106,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct3"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,420)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 107,0,0
    {
      TEXT "$#NAME"
      RECT (155,410,225,434)
      ALIGN 6
      MARGINS (1,1)
      PARENT 106
      ORIENTATION 2
    }
    PIN 108,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct4"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,440)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 109,0,0
    {
      TEXT "$#NAME"
      RECT (155,430,225,454)
      ALIGN 6
      MARGINS (1,1)
      PARENT 108
      ORIENTATION 2
    }
    PIN 110,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="RDslct5"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,460)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 111,0,0
    {
      TEXT "$#NAME"
      RECT (155,450,225,474)
      ALIGN 6
      MARGINS (1,1)
      PARENT 110
      ORIENTATION 2
    }
    PIN 112,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="WRslct"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (240,380)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 113,0,0
    {
      TEXT "$#NAME"
      RECT (161,370,225,394)
      ALIGN 6
      MARGINS (1,1)
      PARENT 112
      ORIENTATION 2
    }
    PIN 114,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="HF1int"
        #VERILOG_TYPE="wire"
      }
      COORD (240,500)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 115,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 114
      ALIGN 6
      RECT (85,475,225,529)
    }
    PIN 116,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="HF2int"
        #VERILOG_TYPE="wire"
      }
      COORD (240,540)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 117,0,0
    {
      TEXT "$#NAME"
      MARGINS (1,1)
      PARENT 116
      ALIGN 6
      RECT (85,515,225,569)
    }
    PIN 14,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,160)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 15,0,0
    {
      TEXT "$#NAME"
      RECT (-25,150,122,174)
      ALIGN 4
      MARGINS (1,1)
      PARENT 14
    }
    PIN 16,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,80)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 17,0,0
    {
      TEXT "$#NAME"
      RECT (-25,70,138,94)
      ALIGN 4
      MARGINS (1,1)
      PARENT 16
    }
    PIN 18,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder1"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,120)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 19,0,0
    {
      TEXT "$#NAME"
      RECT (-25,110,138,134)
      ALIGN 4
      MARGINS (1,1)
      PARENT 18
    }
    PIN 20,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #DOWNTO="1"
        #LABEL="Bus In"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="inDATA(7:0)"
        #NUMBER="0"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,240)
      LINE 2,0,0
      {
        POINTS ((0,10),(0,-10),(-10,0),(0,10))
      }
    }
    TEXT 21,0,0
    {
      TEXT "$#NAME"
      RECT (118,230,225,254)
      ALIGN 6
      MARGINS (1,1)
      PARENT 20
    }
    PIN 33,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Home_Encoder2"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,200)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 34,0,0
    {
      TEXT "$#NAME"
      RECT (-25,190,122,214)
      ALIGN 4
      MARGINS (1,1)
      PARENT 33
    }
    PIN 38,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #FAMILY="Fub"
        #MODIFIED="1"
        #NAME="PhaseA_Encoder2"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,300)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 39,0,0
    {
      TEXT "$#NAME"
      RECT (-26,288,137,312)
      ALIGN 4
      MARGINS (1,1)
      PARENT 38
    }
    PIN 44,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #FAMILY="Fub"
        #MODIFIED="1"
        #NAME="PhaseB_Encoder2"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (-40,380)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 45,0,0
    {
      TEXT "$#NAME"
      RECT (-26,368,137,392)
      ALIGN 4
      MARGINS (1,1)
      PARENT 44
    }
    PIN 47,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LABEL="Bus Out"
        #MODIFIED="1"
        #NAME="outDATA(7:0)"
        #NUMBER="4"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (240,320)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 48,0,0
    {
      TEXT "$#NAME"
      RECT (108,308,227,332)
      ALIGN 6
      MARGINS (1,1)
      PARENT 47
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Reset"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,68)
      ALIGN 1
      MARGINS (1,1)
      PARENT 6
      ORIENTATION 5
    }
    PIN 8,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Sclk"
        #NUMBER="0"
        #SIDE="top"
      }
      COORD (100,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 9,0,0
    {
      TEXT "$#NAME"
      RECT (86,15,110,53)
      ALIGN 1
      MARGINS (1,1)
      PARENT 8
      ORIENTATION 5
    }
  }
}
I 000038 40 7529 1075217965012 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217960"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,620)
  FREEID 118
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,619)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,490,225,514)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,530,225,554)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,500)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,540)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 7566 1075217978137 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 6025 1075217998918 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216046"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,98,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,98,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="NET7977"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="NET7981"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 6159 1075218011871 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218011"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 6159 1075218019700 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218011"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000040 40 5274 1075218019715 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075218019731 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075218019746 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075218019762 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075218019778 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1075218019793 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 1687 1075218019809 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4723 1075218225981 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074866294"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 49
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,368,167,392)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  47, 0, 0
  {
   COORD (180,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Enable_AD"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1075218229903 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075218239684 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218011"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000040 40 5274 1075218239700 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075218239715 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1075218239731 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075218239746 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075218239762 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1075218239778 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 1687 1075218239793 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075218291012 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218011"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000040 40 5274 1075218291028 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075218291043 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1075218291059 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075218291075 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075218291090 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1075218291106 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 1687 1075218291121 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075218473840 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218011"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 6159 1075218480840 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000040 40 5274 1075218512075 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075218512090 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1075218512106 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075218512121 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000041 40 8389 1075218512137 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075218512153 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1075218512168 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 1687 1075218512184 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5249 1075218843121 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215676"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 92
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5718 1075218860528 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218860"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 92
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  92, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="17"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4277 1075218908840 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 5718 1075218908856 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218860"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 92
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  92, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="17"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075225705856 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075225705871 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1075225705887 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075225705903 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000041 40 8389 1075225705918 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075225705934 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1075225705950 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 1687 1075225705965 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075298568986 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1074886007"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075298579908 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075298583798 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075298583799 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7565 1075298583830 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075298583845 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000040 40 5274 1075298583876 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1075298583892 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1075298583908 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075298583939 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1075299659455 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075299674455 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075299674470 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075299674486 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000041 40 4285 1075299674501 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075299674517 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075299674533 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075299674548 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 7566 1075299674549 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075305855642 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075305855658 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075305855673 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000041 40 4285 1075305855674 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075305855689 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075305855705 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075305855720 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 7566 1075305855736 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1075327085095 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1075327085111 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1075327085112 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075327085126 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000041 40 4285 1075327085142 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5274 1075327085158 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 80
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075327085173 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 7566 1075327085189 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000040 40 5629 1075817580369 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217233"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000040 40 5629 1075817596806 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 1687 1075817604619 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6159 1075817604635 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 90
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7565 1075817604650 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1075817604681 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1075817604697 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 7566 1075817604728 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1075817604744 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1075817604760 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 1687 1076008205656 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6491 1076008205750 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7565 1076008205781 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1076008205796 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1076008205828 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 6772 1076008205843 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000040 40 5676 1076008205875 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000041 40 4285 1076008205890 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6517 1076008332921 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218480"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:1)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 6517 1076008338859 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 1687 1076008342203 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1076008342218 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1076008342234 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1076008342250 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 6772 1076008342265 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000040 40 5676 1076008342281 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000041 40 4285 1076008342296 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6517 1076008342312 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 5718 1076338454208 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218860"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 94
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 92
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  92, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="17"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6626 1076338503239 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076338503"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 102
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 92
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,79,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,79,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 100
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  92, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="17"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  95, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense1"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  100, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense2"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 4277 1076338506098 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6626 1076338506114 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076338503"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 102
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 92
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,79,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,79,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 100
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  92, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="17"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  95, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense1"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  100, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense2"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 3355 1076338566520 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1076338566"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,200,280)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (35,110,58,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,35,170,73)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,35,110,88)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (35,210,103,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (87,130,185,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,224,152,266)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,223,72,277)
   ALIGN 9
   MARGINS (1,1)
   PARENT 24
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,-20) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (60,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="sense"
    #NUMBER="1"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (0,-20) )
   }
  }
 }
}
I 000039 40 4277 1076338826161 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6626 1076338826176 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076338503"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 102
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 92
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,79,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,79,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 100
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  92, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="17"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  95, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense1"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  100, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense2"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6772 1076616700665 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216287"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 93
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 7675 1076616753790 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1076616786509 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6517 1076616786525 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7565 1076616786540 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1076616786571 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1076616786603 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000038 40 7566 1076616786634 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1076616786650 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8427 1076616786665 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000045 40 4380 1076616831275 pwmtranslator
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616831"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,220)
  FREEID 75
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,0,160,220)
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,128,83,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,148,70,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,168,85,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  53, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,88,147,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 52
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,108,147,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (106,128,147,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,148,147,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  70, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,88,82,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 69
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,48,79,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  PIN  18, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PWM"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="DIR"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Brake"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  52, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PAH"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  57, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PAL"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  62, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PBH"
    #NUMBER="9"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  67, 0, 0
  {
   COORD (180,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="PBL"
    #NUMBER="10"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  69, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="fBRK"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="HBRK"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (20,0) )
   }
  }
 }
}
I 000041 40 8389 1076617022884 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075298579"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  58, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,70,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 57
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  57, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct7"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 7937 1076617030618 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 7937 1076617033962 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1076617033978 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6517 1076617033993 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7565 1076617034009 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1076617034025 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000038 40 7566 1076617034040 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1076617034056 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8091 1076617034071 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 7937 1076617091556 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1076617091557 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6517 1076617091571 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7565 1076617091587 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1076617091603 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000038 40 7566 1076617091618 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 4285 1076617091634 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 8091 1076617091650 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2627 1077320065871 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320065"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,260)
  FREEID 14
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,260)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,70,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,68,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (81,30,165,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (115,70,155,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (61,110,165,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (180,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (180,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 1628 1077320238543 negdetect
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1077316699"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,180,120)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,28,72,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,89)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (98,48,166,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Line"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Ndetect"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000039 40 2871 1077320238700 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077317453"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,740)
  FREEID 28
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,740)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,67,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2648 1077320743668 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320065"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 14
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,70,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,68,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (235,70,275,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2749 1077320820559 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320820"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,55,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,98,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (235,70,275,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2749 1077320831496 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320820"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,70,55,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,110,98,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (235,70,275,94)
   ALIGN 6
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2834 1077320849950 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320849"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 7937 1077320854512 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077320854606 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077320854778 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6517 1077320854934 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000039 40 7565 1077320855090 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077320855246 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 8091 1077320855371 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077320855559 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2834 1077320855715 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320849"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
V 000041 40 1628 1077320896137 negdetect
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320896"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,180,120)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (34,28,72,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,74)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (98,48,166,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 14
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Line"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Ndetect"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000039 40 2874 1077320905918 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077317453"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,740)
  FREEID 28
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,740)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="SCLreset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 2874 1077320916434 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320916"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,740)
  FREEID 28
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,740)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="SCLreset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000038 40 1424 1077320983856 negscl
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320983"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,180)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,180,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,34,112,89)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,70,65,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (122,90,175,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="0"
    #VERILOG_DELAY=""
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #NAME="SCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="20"
    #NAME="NSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-20,0) )
   }
  }
 }
}
I 000039 40 2874 1077321224153 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320916"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,740)
  FREEID 28
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,740)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  PIN  2, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="SCLreset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 2770 1077321360012 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321359"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 3005 1077321396356 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321359"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2762 1077321545090 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321544"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2762 1077321575684 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321544"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2762 1077321588246 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321588"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2762 1077321628200 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321588"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2762 1077321680762 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321680"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2762 1077321702153 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321680"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2762 1077321722028 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321721"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2762 1077321764700 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321764"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 2762 1077321804590 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321804"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000039 40 3044 1077322603871 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321804"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2918 1077322659918 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321804"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2918 1077322685450 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077321804"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 29
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,69)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="MCLK"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2918 1077322692168 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077322692"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 30
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2918 1077322695450 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077322692"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 30
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 2918 1077322800246 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077322692"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 30
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
 }
}
I 000042 40 3369 1077322810606 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077322810"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 32
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3369 1077322820653 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077322810"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 32
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3757 1077322905075 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077322810"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000042 40 3757 1077563082661 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077322810"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000042 40 3757 1077563092005 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563091"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000042 40 3757 1077563189568 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563091"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000038 40 2834 1077563276130 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077320849"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2847 1077563289193 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563289"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 1687 1077563293677 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 7937 1077563293708 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077563293740 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6517 1077563293771 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 8091 1077563293786 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077563293818 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077563293833 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077563293865 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2847 1077563293880 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563289"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2847 1077563313536 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563289"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 15
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 3302 1077563325958 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563325"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 17
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077563329271 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 7937 1077563329286 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077563329302 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6517 1077563329318 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 8091 1077563329333 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077563329349 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077563329365 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077563329380 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 3302 1077563329396 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563325"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 17
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3757 1077563381630 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563091"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000042 40 1687 1077563386536 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 7937 1077563386552 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077563386568 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6517 1077563386583 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 8091 1077563386599 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077563386615 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077563386630 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077563386646 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 3302 1077563386661 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563325"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 17
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (201,30,285,54)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3186 1077563392193 i2cfix
SYMB0100
HEADER
{
  VARIABLES
  {
    #DESCRIPTION=""
    #FUB="1"
    #LANGUAGE="VERILOG"
    #MODIFIED="1077563392"
  }
}
PAGE ""
{
  PAGEHEADER 
  {
    RECT (0,0,300,160)
    FREEID 17
  }
  BODY
  {
    RECT 1,-1,0
    {
      VARIABLES
      {
        #OUTLINE_FILLING="1"
      }
      AREA (0,0,300,160)
    }
    PIN 10,0,0
    {
      VARIABLES
      {
        #DIRECTION="INOUT"
        #LABEL="InOut"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="SCL"
        #NUMBER="0"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (0,100)
      LINE 2,0,0
      {
        POINTS ((0,0),(10,-10),(20,0),(10,10),(0,0))
      }
    }
    TEXT 11,0,0
    {
      TEXT "$#NAME"
      RECT (25,90,65,114)
      ALIGN 4
      MARGINS (1,1)
      PARENT 10
      ORIENTATION 2
    }
    PIN 12,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #DOWNTO="1"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="counter(5:0)"
        #NUMBER="0"
        #SIDE="right"
      }
      COORD (300,120)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 13,0,0
    {
      TEXT "$#NAME"
      RECT (181,110,285,134)
      ALIGN 6
      MARGINS (1,1)
      PARENT 12
    }
    PIN 15,0,0
    {
      VARIABLES
      {
        #DIRECTION="OUT"
        #LABEL="Out"
        #MODIFIED="1"
        #NAME="SCLint"
        #NUMBER="1"
        #SIDE="right"
        #VERILOG_DELAY=""
      }
      COORD (300,80)
      LINE 2,0,0
      {
        POINTS ((0,0),(-10,10),(-10,-10),(0,0))
      }
    }
    TEXT 16,0,0
    {
      TEXT "$#NAME"
      RECT (228,68,287,92)
      ALIGN 6
      MARGINS (1,1)
      PARENT 15
    }
    PIN 2,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Inc"
        #NUMBER="0"
        #SIDE="left"
      }
      COORD (0,40)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 3,0,0
    {
      TEXT "$#NAME"
      RECT (15,30,43,54)
      ALIGN 4
      MARGINS (1,1)
      PARENT 2
    }
    PIN 4,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="Mclk"
        #NUMBER="0"
        #SIDE="top"
        #VERILOG_DELAY=""
      }
      COORD (140,0)
      LINE 2,0,0
      {
        POINTS ((10,0),(-10,0),(0,10),(10,0))
      }
    }
    TEXT 5,0,0
    {
      TEXT "$#NAME"
      RECT (126,15,150,55)
      ALIGN 1
      MARGINS (1,1)
      PARENT 4
      ORIENTATION 5
    }
    PIN 6,0,0
    {
      VARIABLES
      {
        #DIRECTION="IN"
        #LENGTH="0"
        #MODIFIED="1"
        #NAME="SCLreset"
        #NUMBER="0"
        #SIDE="left"
        #VERILOG_DELAY=""
      }
      COORD (0,60)
      LINE 2,0,0
      {
        POINTS ((0,-10),(0,10),(10,0),(0,-10))
      }
    }
    TEXT 7,0,0
    {
      TEXT "$#NAME"
      RECT (15,50,98,74)
      ALIGN 4
      MARGINS (1,1)
      PARENT 6
    }
  }
}
I 000038 40 2748 1077563443021 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563392"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 17
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 2748 1077563445286 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563445"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 18
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 3757 1077563457286 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563091"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
 }
}
I 000042 40 4213 1077563483240 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563483"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 4213 1077563573911 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563483"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 2748 1077563614349 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563445"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 18
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000038 40 3201 1077563624646 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 7937 1077563739240 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076617030"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 85
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077563752661 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077563755927 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077563755943 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6517 1077563755958 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 8091 1077563755974 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077563755990 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077563756005 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077563756021 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1077563756036 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077563756052 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6517 1077563807411 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076008338"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
 }
}
I 000042 40 6992 1077563823490 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077564030115 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077564030130 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 8091 1077564030146 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077564030161 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077564030177 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077564030193 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1077564030208 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077564030224 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6992 1077564030240 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077564149927 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077564149943 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 8091 1077564149958 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077564149974 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077564149990 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077564150005 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1077564150021 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077564150036 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6992 1077564150052 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 4213 1077564150286 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563483"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 4213 1077564175333 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563483"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077564279458 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077564279474 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 8091 1077564279490 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077564279505 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077564279521 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077564279536 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1077564279552 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077564279568 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6992 1077564279583 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 4166 1077564391068 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563483"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  28, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,710,68,734)
   ALIGN 4
   MARGINS (1,1)
   PARENT 27
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  27, 0, 0
  {
   COORD (0,720)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 3764 1077564396552 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077564396"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000042 40 3811 1077564400708 bitcounter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077564396"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,800)
  FREEID 38
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,800)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,408,77,432)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,668,89,692)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  18, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 17
   ORIENTATION 5
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (83,348,187,372)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  26, 0, 0
  {
   TEXT "$#NAME"
   RECT (103,528,187,552)
   ALIGN 6
   MARGINS (1,1)
   PARENT 25
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,97,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  33, 0, 0
  {
   TEXT "$#NAME"
   RECT (127,448,186,472)
   ALIGN 6
   MARGINS (1,1)
   PARENT 32
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  PIN  8, 0, 0
  {
   COORD (0,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegInc"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (0,680)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="NegSCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  17, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (200,360)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  25, 0, 0
  {
   COORD (200,540)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #MODIFIED="1"
    #NAME="DriveSCL"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-20,0), (-10,-10), (0,0) )
   }
  }
  PIN  30, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  32, 0, 0
  {
   COORD (200,460)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="OUT"
    #FAMILY="Fub"
    #NAME="SCLint"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,-10), (-10,10), (0,0) )
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077564582068 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077564582083 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 8091 1077564582099 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077564582115 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077564582130 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077564582146 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000041 40 8389 1077564582161 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077564582177 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 6992 1077564582193 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077816346018 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077816346112 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077816346128 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077816346159 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077816346175 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 8091 1077816346190 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077816346221 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077816346237 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6992 1077816346253 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077817025237 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077817025253 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077817025268 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077817025284 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077817025300 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 8091 1077817025315 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077817025331 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077817025346 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6992 1077817025362 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077824972831 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077824972846 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077824972862 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077824972863 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077824972878 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 8091 1077824972893 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077824972909 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077824972925 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6992 1077824972940 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000039 40 3355 1077824973143 counter
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #LANGUAGE="VERILOG"
  #MODIFIED="1076338566"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,220,300)
  FREEID 27
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (20,20,200,280)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (35,110,58,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (146,35,170,73)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,35,110,88)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (35,210,103,234)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (87,130,185,154)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  22, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,224,152,266)
   ALIGN 9
   MARGINS (1,1)
   PARENT 21
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,223,72,277)
   ALIGN 9
   MARGINS (1,1)
   PARENT 24
   ORIENTATION 5
  }
  PIN  2, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="ce"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,20) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="updown"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (20,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (220,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="count(23:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,3, (64,92,92)
    POINTS ( (0,0), (-20,0) )
   }
  }
  PIN  21, 0, 0
  {
   COORD (140,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #LENGTH="20"
    #MODIFIED="1"
    #NAME="Zero"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (64,92,92)
    POINTS ( (0,0), (0,-20) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (60,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #LENGTH="20"
    #MODIFIED=""
    #NAME="sense"
    #NUMBER="1"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    OUTLINE 0,1, (0,0,128)
    POINTS ( (0,0), (0,-20) )
   }
  }
 }
}
V 000039 40 4277 1077824973175 holdreg
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075215666"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,960)
  FREEID 48
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,960)
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,130,112,154)
   ALIGN 4
   MARGINS (1,1)
   PARENT 4
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (46,15,70,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,850,112,874)
   ALIGN 4
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (66,15,90,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 5
  }
  TEXT  25, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,468,187,492)
   ALIGN 6
   MARGINS (1,1)
   PARENT 24
  }
  TEXT  31, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,48,187,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 30
  }
  TEXT  36, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 35
  }
  TEXT  41, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 40
  }
  TEXT  46, 0, 0
  {
   TEXT "$#NAME"
   RECT (117,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 45
  }
  PIN  4, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch0in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (0,860)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="ch1in(23:0)"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  24, 0, 0
  {
   COORD (200,480)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  30, 0, 0
  {
   COORD (200,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  35, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  40, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  45, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000042 40 6626 1077824973190 homeconfig
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076338503"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,300)
  FREEID 102
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,300)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,14,212,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 3
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (208,14,232,52)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (170,128,277,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,67,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,67,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  56, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,161,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 55
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,161,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  77, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,208,287,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 76
  }
  TEXT  82, 0, 0
  {
   TEXT "$#NAME"
   RECT (249,248,287,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  90, 0, 0
  {
   TEXT "$#NAME"
   RECT (223,88,287,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 89
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,168,287,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 92
  }
  TEXT  96, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,79,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 95
  }
  TEXT  101, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,79,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 100
  }
  PIN  3, 0, 0
  {
   COORD (200,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="1"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (220,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="2"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (300,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Zero2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  55, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  76, 0, 0
  {
   COORD (300,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF1"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  81, 0, 0
  {
   COORD (300,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="HF2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  84, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  89, 0, 0
  {
   COORD (300,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  92, 0, 0
  {
   COORD (300,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="17"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  95, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense1"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  100, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="sense2"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077825253956 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216203"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(5:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077825261378 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825261"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077825267878 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077825267893 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077825267909 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077825267940 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 8091 1077825267956 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077825267971 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077825267987 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6992 1077825268003 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077825268018 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825261"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077825909175 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563752"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 87
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,75,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctd"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077825919065 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825919"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 88
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,74,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077825923112 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077825923128 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077825923143 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 8091 1077825923159 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077825923175 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077825923190 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6992 1077825923206 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077825923221 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825919"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 88
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,74,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077825923237 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825261"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077825990565 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077825990581 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077825990596 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 8091 1077825990612 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077825990628 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077825990643 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6992 1077825990659 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077825990675 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825919"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 88
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,74,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077825990690 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825261"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077826184518 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825919"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 88
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,74,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct6"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077826191346 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077826191"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 88
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,74,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct5"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 3201 1077826206362 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 4285 1077826206378 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000038 40 7566 1077826206393 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
I 000042 40 8091 1077826206409 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000039 40 7565 1077826206425 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000040 40 5676 1077826206440 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
I 000042 40 6992 1077826206456 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000042 40 1687 1077826206471 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825261"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
I 000041 40 8389 1077826206487 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077826191"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 88
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,74,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct5"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000038 40 3201 1077826244003 i2cfix
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563624"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,300,160)
  FREEID 20
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,300,160)
  }
  TEXT  3, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,30,43,54)
   ALIGN 4
   MARGINS (1,1)
   PARENT 2
  }
  TEXT  5, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,55)
   ALIGN 1
   MARGINS (1,1)
   PARENT 4
   ORIENTATION 5
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (15,50,98,74)
   ALIGN 4
   MARGINS (1,1)
   PARENT 6
  }
  TEXT  11, 0, 0
  {
   TEXT "$#NAME"
   RECT (25,90,65,114)
   ALIGN 4
   MARGINS (1,1)
   PARENT 10
   ORIENTATION 2
  }
  TEXT  13, 0, 0
  {
   TEXT "$#NAME"
   RECT (181,110,285,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 12
  }
  TEXT  16, 0, 0
  {
   TEXT "$#NAME"
   RECT (228,68,287,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 15
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (239,28,287,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  PIN  2, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Inc"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  4, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="0"
    #SIDE="top"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  6, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCLreset"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  10, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="InOut"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="SCL"
    #NUMBER="0"
    #SIDE="left"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (10,-10), (20,0), (10,10), (0,0) )
   }
  }
  PIN  12, 0, 0
  {
   COORD (300,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="counter(5:0)"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  15, 0, 0
  {
   COORD (300,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (300,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="rdslct"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000041 40 4285 1077826244018 interface
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075218229"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,180,480)
  FREEID 50
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,180,480)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (89,228,157,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (139,48,167,72)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,167,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (132,128,167,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,110,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (24,148,131,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (48,14,72,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 36
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 41
   ORIENTATION 5
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,133,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  PIN  3, 0, 0
  {
   COORD (180,240)
   VARIABLES
   {
    #DIRECTION="INOUT"
    #LABEL="Bus InOut"
    #MODIFIED="1"
    #NAME="AD(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-20,0), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (180,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (180,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (180,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (60,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="9"
    #SIDE="top"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000038 40 7566 1077826244034 servos
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075217978"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-40,0,240,480)
  FREEID 119
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-40,0,240,479)
  }
  TEXT  7, 0, 0
  {
   TEXT "$#NAME"
   RECT (126,15,150,68)
   ALIGN 1
   MARGINS (1,1)
   PARENT 6
   ORIENTATION 5
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (86,15,110,53)
   ALIGN 1
   MARGINS (1,1)
   PARENT 8
   ORIENTATION 5
  }
  TEXT  15, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,150,122,174)
   ALIGN 4
   MARGINS (1,1)
   PARENT 14
  }
  TEXT  17, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,70,138,94)
   ALIGN 4
   MARGINS (1,1)
   PARENT 16
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,110,138,134)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  21, 0, 0
  {
   TEXT "$#NAME"
   RECT (118,230,225,254)
   ALIGN 6
   MARGINS (1,1)
   PARENT 20
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (-25,190,122,214)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,288,137,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (-26,368,137,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  48, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,308,227,332)
   ALIGN 6
   MARGINS (1,1)
   PARENT 47
  }
  TEXT  103, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,350,225,374)
   ALIGN 6
   MARGINS (1,1)
   PARENT 102
   ORIENTATION 2
  }
  TEXT  105, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,390,225,414)
   ALIGN 6
   MARGINS (1,1)
   PARENT 104
   ORIENTATION 2
  }
  TEXT  107, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,410,225,434)
   ALIGN 6
   MARGINS (1,1)
   PARENT 106
   ORIENTATION 2
  }
  TEXT  109, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,430,225,454)
   ALIGN 6
   MARGINS (1,1)
   PARENT 108
   ORIENTATION 2
  }
  TEXT  111, 0, 0
  {
   TEXT "$#NAME"
   RECT (155,450,225,474)
   ALIGN 6
   MARGINS (1,1)
   PARENT 110
   ORIENTATION 2
  }
  TEXT  113, 0, 0
  {
   TEXT "$#NAME"
   RECT (161,370,225,394)
   ALIGN 6
   MARGINS (1,1)
   PARENT 112
   ORIENTATION 2
  }
  TEXT  115, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,90,225,114)
   ALIGN 6
   MARGINS (1,1)
   PARENT 114
  }
  TEXT  117, 0, 0
  {
   TEXT "$#NAME"
   RECT (168,110,225,134)
   ALIGN 6
   MARGINS (1,1)
   PARENT 116
  }
  PIN  6, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  8, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Sclk"
    #NUMBER="0"
    #SIDE="top"
   }
   LINE  2, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
   }
  }
  PIN  14, 0, 0
  {
   COORD (-40,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  16, 0, 0
  {
   COORD (-40,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (-40,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder1"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  20, 0, 0
  {
   COORD (240,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #DOWNTO="1"
    #LABEL="Bus In"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (-40,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="Home_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (-40,300)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseA_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  44, 0, 0
  {
   COORD (-40,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="PhaseB_Encoder2"
    #NUMBER="0"
    #SIDE="left"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  47, 0, 0
  {
   COORD (240,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #DOWNTO="1"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  102, 0, 0
  {
   COORD (240,360)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct1"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  104, 0, 0
  {
   COORD (240,400)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct2"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  106, 0, 0
  {
   COORD (240,420)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct3"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  108, 0, 0
  {
   COORD (240,440)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct4"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  110, 0, 0
  {
   COORD (240,460)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="RDslct5"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  112, 0, 0
  {
   COORD (240,380)
   VARIABLES
   {
    #DIRECTION="IN"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="0"
    #SIDE="right"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,10), (0,-10), (-10,0), (0,10) )
   }
  }
  PIN  114, 0, 0
  {
   COORD (240,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  116, 0, 0
  {
   COORD (240,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LENGTH="0"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
 }
}
V 000042 40 8091 1077826244050 pwmcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1076616753"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (-20,0,200,320)
  FREEID 101
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (-20,0,200,320)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (135,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,68,54,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  49, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,88,41,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  54, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,108,56,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 53
  }
  TEXT  59, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,208,54,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 58
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,228,41,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 63
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,248,56,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 68
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (0,28,59,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,168,53,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,128,187,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (137,268,187,292)
   ALIGN 6
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,48,60,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 94
  }
  TEXT  100, 0, 0
  {
   TEXT "$#NAME"
   RECT (-6,188,60,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 99
  }
  PIN  13, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH1"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL1"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  23, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH1"
    #NUMBER="5"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  28, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAH2"
    #NUMBER="6"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  33, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBH2"
    #NUMBER="7"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  38, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PAL2"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  43, 0, 0
  {
   COORD (-20,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM1"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  48, 0, 0
  {
   COORD (-20,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  53, 0, 0
  {
   COORD (-20,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  58, 0, 0
  {
   COORD (-20,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="PWM2"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  63, 0, 0
  {
   COORD (-20,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  68, 0, 0
  {
   COORD (-20,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  78, 0, 0
  {
   COORD (-20,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  83, 0, 0
  {
   COORD (-20,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
   }
  }
  PIN  86, 0, 0
  {
   COORD (200,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL1"
    #NUMBER="18"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  91, 0, 0
  {
   COORD (200,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="PBL2"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  2, 0, 0
   {
    POINTS ( (0,0), (-10,10), (-10,-10), (0,0) )
   }
  }
  PIN  94, 0, 0
  {
   COORD (-20,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK1"
    #NUMBER="20"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  99, 0, 0
  {
   COORD (-20,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="HBRK2"
    #NUMBER="21"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000039 40 7565 1077826244065 lswitch
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075216085"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,260,240)
  FREEID 97
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,260,239)
  }
  TEXT  27, 0, 0
  {
   TEXT "$#NAME"
   RECT (148,14,172,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 26
   ORIENTATION 5
  }
  TEXT  32, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 31
   ORIENTATION 5
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,78,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 36
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,63,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,65,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,78,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  57, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,63,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 56
  }
  TEXT  62, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,65,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 61
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,128,247,152)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  71, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,61,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 70
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,61,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,148,247,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,168,247,192)
   ALIGN 6
   MARGINS (1,1)
   PARENT 83
  }
  TEXT  87, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,76,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 86
  }
  TEXT  92, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,76,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 91
  }
  TEXT  95, 0, 0
  {
   TEXT "$#NAME"
   RECT (188,88,247,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 94
  }
  PIN  26, 0, 0
  {
   COORD (160,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="4"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  31, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="5"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home1"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS1"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS1"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Home2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  56, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="FLS2"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  61, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RLS2"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (260,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="12"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  70, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR2"
    #NUMBER="13"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="DIR1"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (260,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  83, 0, 0
  {
   COORD (260,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="16"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  86, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake1"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  91, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Brake2"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  94, 0, 0
  {
   COORD (260,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="19"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000040 40 5676 1077826244081 miscouts
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1075817596"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,280,160)
  FREEID 86
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,280,160)
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (160,88,267,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,8,65,32)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,28,71,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (20,48,71,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,65,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,65,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,87,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  44, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,97,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 43
  }
  TEXT  64, 0, 0
  {
   TEXT "$#NAME"
   RECT (108,14,132,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 63
   ORIENTATION 5
  }
  TEXT  69, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 68
   ORIENTATION 5
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (203,28,267,52)
   ALIGN 6
   MARGINS (1,1)
   PARENT 71
  }
  TEXT  81, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,14,112,112)
   ALIGN 1
   MARGINS (1,1)
   PARENT 80
   ORIENTATION 5
  }
  PIN  8, 0, 0
  {
   COORD (280,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (0,20)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED1"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED2"
    #NUMBER="4"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED3"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED4"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="LED5"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwr"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  43, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="MTRpwrn"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  63, 0, 0
  {
   COORD (120,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="13"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  68, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="14"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  71, 0, 0
  {
   COORD (280,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  80, 0, 0
  {
   COORD (100,0)
   VARIABLES
   {
    #DESCRIPTION=""
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="LightSense"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,1), (10,1), (0,11) )
   }
  }
 }
}
V 000042 40 6992 1077826244096 intcontrol
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077563823"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,280)
  FREEID 96
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,280)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,88,187,112)
   ALIGN 6
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (80,108,187,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,14,92,67)
   ALIGN 1
   MARGINS (1,1)
   PARENT 33
   ORIENTATION 5
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,14,152,54)
   ALIGN 1
   MARGINS (1,1)
   PARENT 38
   ORIENTATION 5
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,73,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  47, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,73,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  52, 0, 0
  {
   TEXT "$#NAME"
   RECT (154,188,187,212)
   ALIGN 6
   MARGINS (1,1)
   PARENT 51
  }
  TEXT  65, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,132,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 64
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,208,187,232)
   ALIGN 6
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,228,187,252)
   ALIGN 6
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  76, 0, 0
  {
   TEXT "$#NAME"
   RECT (112,248,187,272)
   ALIGN 6
   MARGINS (1,1)
   PARENT 75
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,71,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 78
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,228,71,252)
   ALIGN 4
   MARGINS (1,1)
   PARENT 84
  }
  TEXT  91, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,78,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 90
  }
  TEXT  94, 0, 0
  {
   TEXT "$#NAME"
   RECT (88,208,112,267)
   ALIGN 9
   MARGINS (1,1)
   PARENT 93
   ORIENTATION 5
  }
  PIN  3, 0, 0
  {
   COORD (200,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="1"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (200,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="inDATA(7:0)"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (80,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Reset"
    #NUMBER="7"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (140,0)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="Mclk"
    #NUMBER="8"
    #SIDE="top"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (10,0), (-10,0), (0,10), (10,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK2"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  46, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="fBRK1"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  51, 0, 0
  {
   COORD (200,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="INT"
    #NUMBER="11"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  64, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="PWRflgs(7:0)"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (200,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="13"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (200,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct2"
    #NUMBER="14"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  75, 0, 0
  {
   COORD (200,260)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WRslct1"
    #NUMBER="15"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  78, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF1int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  84, 0, 0
  {
   COORD (0,240)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #MODIFIED="1"
    #NAME="HF2int"
    #NUMBER="0"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  90, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="IN"
    #FAMILY="Fub"
    #NAME="INTbus"
    #NUMBER="0"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (1,-10), (1,10), (11,0) )
   }
  }
  PIN  93, 0, 0
  {
   COORD (100,280)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="SCLint"
    #NUMBER="16"
    #SIDE="bottom"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (-10,0), (10,0), (0,-10), (-10,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000042 40 1687 1077826244112 i2caddress
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077825261"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,200,120)
  FREEID 39
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,200,120)
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,48,99,72)
   ALIGN 4
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (68,68,187,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  37, 0, 0
  {
   TEXT "$#NAME"
   RECT (128,8,187,32)
   ALIGN 6
   MARGINS (1,1)
   PARENT 36
  }
  PIN  13, 0, 0
  {
   COORD (0,60)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="I2CS(5:0)"
    #NUMBER="3"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (200,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Bus Out"
    #MODIFIED="1"
    #NAME="outDATA(7:0)"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (-10,-10), (-10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  36, 0, 0
  {
   COORD (200,20)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RDslct"
    #NUMBER="8"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}
V 000041 40 8389 1077826244128 adddecode
SYMB0100
HEADER
{
 VARIABLES
 {
  #DESCRIPTION=""
  #FUB="1"
  #LANGUAGE="VERILOG"
  #MODIFIED="1077826191"
 }
}
PAGE "" 
{
 PAGEHEADER
 {
  RECT (0,0,120,460)
  FREEID 88
 }
 
 BODY
 {
  RECT  1, -1, 0
  {
   VARIABLES
   {
    #OUTLINE_FILLING="1"
   }
   AREA (0,0,120,460)
  }
  TEXT  4, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,28,110,52)
   ALIGN 4
   MARGINS (1,1)
   PARENT 3
  }
  TEXT  9, 0, 0
  {
   TEXT "$#NAME"
   RECT (79,68,107,92)
   ALIGN 6
   MARGINS (1,1)
   PARENT 8
  }
  TEXT  14, 0, 0
  {
   TEXT "$#NAME"
   RECT (72,108,107,132)
   ALIGN 6
   MARGINS (1,1)
   PARENT 13
  }
  TEXT  19, 0, 0
  {
   TEXT "$#NAME"
   RECT (77,148,107,172)
   ALIGN 6
   MARGINS (1,1)
   PARENT 18
  }
  TEXT  24, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,68,74,92)
   ALIGN 4
   MARGINS (1,1)
   PARENT 23
  }
  TEXT  29, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,88,70,112)
   ALIGN 4
   MARGINS (1,1)
   PARENT 28
  }
  TEXT  34, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,108,70,132)
   ALIGN 4
   MARGINS (1,1)
   PARENT 33
  }
  TEXT  39, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,128,70,152)
   ALIGN 4
   MARGINS (1,1)
   PARENT 38
  }
  TEXT  42, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,148,75,172)
   ALIGN 4
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  45, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,168,75,192)
   ALIGN 4
   MARGINS (1,1)
   PARENT 44
  }
  TEXT  50, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,188,74,212)
   ALIGN 4
   MARGINS (1,1)
   PARENT 49
  }
  TEXT  55, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,208,69,232)
   ALIGN 4
   MARGINS (1,1)
   PARENT 54
  }
  TEXT  63, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,248,75,272)
   ALIGN 4
   MARGINS (1,1)
   PARENT 62
  }
  TEXT  68, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,268,70,292)
   ALIGN 4
   MARGINS (1,1)
   PARENT 67
  }
  TEXT  73, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,288,70,312)
   ALIGN 4
   MARGINS (1,1)
   PARENT 72
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,308,70,332)
   ALIGN 4
   MARGINS (1,1)
   PARENT 77
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,328,70,352)
   ALIGN 4
   MARGINS (1,1)
   PARENT 82
  }
  TEXT  86, 0, 0
  {
   TEXT "$#NAME"
   RECT (14,368,72,392)
   ALIGN 4
   MARGINS (1,1)
   PARENT 85
  }
  PIN  3, 0, 0
  {
   COORD (0,40)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="Bus In"
    #MODIFIED="1"
    #NAME="ADDR(7:0)"
    #NUMBER="1"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  8, 0, 0
  {
   COORD (120,80)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="AS"
    #NUMBER="2"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  13, 0, 0
  {
   COORD (120,120)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="WR"
    #NUMBER="3"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  18, 0, 0
  {
   COORD (120,160)
   VARIABLES
   {
    #DIRECTION="IN"
    #LABEL="In"
    #MODIFIED="1"
    #NAME="RD"
    #NUMBER="4"
    #SIDE="right"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,-10), (0,10), (-10,0), (0,-10) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  23, 0, 0
  {
   COORD (0,80)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslctc"
    #NUMBER="5"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  28, 0, 0
  {
   COORD (0,100)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslctb"
    #NUMBER="6"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  33, 0, 0
  {
   COORD (0,120)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct4"
    #NUMBER="7"
    #SIDE="left"
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  38, 0, 0
  {
   COORD (0,140)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct5"
    #NUMBER="8"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  41, 0, 0
  {
   COORD (0,160)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct5"
    #NUMBER="9"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  44, 0, 0
  {
   COORD (0,180)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct9"
    #NUMBER="10"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  49, 0, 0
  {
   COORD (0,200)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslcta"
    #NUMBER="11"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  54, 0, 0
  {
   COORD (0,220)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslcta"
    #NUMBER="12"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  62, 0, 0
  {
   COORD (0,260)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Wslct7"
    #NUMBER="14"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  67, 0, 0
  {
   COORD (0,280)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct0"
    #NUMBER="15"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  72, 0, 0
  {
   COORD (0,300)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct1"
    #NUMBER="16"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  77, 0, 0
  {
   COORD (0,320)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct2"
    #NUMBER="17"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  82, 0, 0
  {
   COORD (0,340)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="Rslct3"
    #NUMBER="18"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
  PIN  85, 0, 0
  {
   COORD (0,380)
   VARIABLES
   {
    #DIRECTION="OUT"
    #LABEL="Out"
    #MODIFIED="1"
    #NAME="RslctE"
    #NUMBER="19"
    #SIDE="left"
    #VERILOG_DELAY=""
    #VERILOG_TYPE="wire"
   }
   LINE  1, 0, 0
   {
    POINTS ( (0,0), (10,-10), (10,10), (0,0) )
    FILL (0,(0,0,0),0)
   }
  }
 }
}