//--------------------------------------------------------------------------------------------------
//
// Title       : PWMcontrol
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\compile\PWMcontrol.v
// Generated   : Thu Feb 26 13:03:04 2004
// From        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\PWMcontrol.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps
primitive PL (O, fBRK, Brake, DIR, PWM);
  output O;
  input fBRK, Brake, DIR, PWM;
  table	  					 
  //output 0 = pull up transisitor off
  //PWM = 1 then try to turn on or O = 1
  //DIR = 0 Reverse, 1= Forward
  //Brake = 1, apply brake at PWM rate
  //fBRK = 1 then hard brake
  //fBRK, Brake, DIR, PWM  O
  	0	0	0	0	:	0 ;
  	0	0	0	1	:	0 ;
	0	0	1	0	:	0 ;
	0	0	1	1	:	1 ;
	0	1	0	0	:	0 ;
	0	1	0	1	:	1 ;
	0	1	1	0	:	0 ;
	0	1	1	1	:	1 ;
	1	x	x	x	:	1 ;
  endtable
 endprimitive
 
primitive PH (O, fBRK, Brake, DIR, PWM);
  output O;
  input fBRK, Brake, DIR, PWM;
  table	  					 
  //output 0 = pull up transisitor off
  //PWM = 1 then try to turn on or O = 1
  //DIR = 0 Reverse, 1= Forward
  //Brake = 1, apply brake at PWM rate
  //fBRK = 1 then hard brake
  //fBRK, Brake, DIR, PWM  O
  	0	0	0	0	:	0 ;
  	0	0	0	1	:	0 ;
	0	0	1	0	:	0 ;
	0	0	1	1	:	1 ;
	0	1	0	0	:	0 ;
	0	1	0	1	:	0 ;
	0	1	1	0	:	0 ;
	0	1	1	1	:	0 ;
	1	x	x	x	:	0 ;
  endtable
 endprimitive

module PWMcontrol (Brake1,Brake2,DIR1,DIR2,HBRK1,HBRK2,PWM1,PWM2,fBRK1,fBRK2,
PAH1,PAH2,PAL1,PAL2,PBH1,PBH2,PBL1,PBL2) ;

// ------------ Port declarations --------- //
input Brake1;
wire Brake1;
input Brake2;
wire Brake2;
input DIR1;
wire DIR1;
input DIR2;
wire DIR2;
input HBRK1;
wire HBRK1;
input HBRK2;
wire HBRK2;
input PWM1;
wire PWM1;
input PWM2;
wire PWM2;
input fBRK1;
wire fBRK1;
input fBRK2;
wire fBRK2;
output PAH1;
wire PAH1;
output PAH2;
wire PAH2;
output PAL1;
wire PAL1;
output PAL2;
wire PAL2;
output PBH1;
wire PBH1;
output PBH2;
wire PBH2;
output PBL1;
wire PBL1;
output PBL2;
wire PBL2;

// -------- Component instantiations -------//

PWMtranslator U1
(
	.Brake(Brake1),
	.DIR(DIR1),
	.HBRK(HBRK1),
	.PAH(PAH1),
	.PAL(PAL1),
	.PBH(PBH1),
	.PBL(PBL1),
	.PWM(PWM1),
	.fBRK(fBRK1)
);



PWMtranslator U2
(
	.Brake(Brake2),
	.DIR(DIR2),
	.HBRK(HBRK2),
	.PAH(PAH2),
	.PAL(PAL2),
	.PBH(PBH2),
	.PBL(PBL2),
	.PWM(PWM2),
	.fBRK(fBRK2)
);



endmodule