//--------------------------------------------------------------------------------------------------
//
// Title       : Servos
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\compile\Servos.v
// Generated   : Thu Feb 26 11:59:27 2004
// From        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\Servos.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps

module Servos (Home_Encoder1,Home_Encoder2,PhaseA_Encoder1,PhaseA_Encoder2,PhaseB_Encoder1,PhaseB_Encoder2,RDslct1,RDslct2,RDslct3,RDslct4,
RDslct5,Reset,Sclk,WRslct,inDATA,HF1int,HF2int,outDATA) ;

// ------------ Port declarations --------- //
input Home_Encoder1;
wire Home_Encoder1;
input Home_Encoder2;
wire Home_Encoder2;
input PhaseA_Encoder1;
wire PhaseA_Encoder1;
input PhaseA_Encoder2;
wire PhaseA_Encoder2;
input PhaseB_Encoder1;
wire PhaseB_Encoder1;
input PhaseB_Encoder2;
wire PhaseB_Encoder2;
input RDslct1;
wire RDslct1;
input RDslct2;
wire RDslct2;
input RDslct3;
wire RDslct3;
input RDslct4;
wire RDslct4;
input RDslct5;
wire RDslct5;
input Reset;
wire Reset;
input Sclk;
wire Sclk;
input WRslct;
wire WRslct;
input [7:0] inDATA;
wire [7:0] inDATA;
output HF1int;
wire HF1int;
output HF2int;
wire HF2int;
output [7:0] outDATA;
wire [7:0] outDATA;

// ----------- Signal declarations -------- //
wire ce1;
wire ce2;
wire NET2937;
wire NET2948;
wire updown1;
wire updown2;
wire Zero1;
wire Zero2;
wire [23:0] Channel1;
wire [23:0] Channel2;

// -------- Component instantiations -------//

Decode U1
(
	.Reset(Reset),
	.Sclk(Sclk),
	.ce(ce1),
	.phaseA(PhaseA_Encoder1),
	.phaseB(PhaseB_Encoder1),
	.updown(updown1)
);



Counter U2
(
	.Reset(Reset),
	.Sclk(Sclk),
	.Zero(Zero1),
	.ce(ce1),
	.count(Channel1),
	.sense(NET2948),
	.updown(updown1)
);



Holdreg U3
(
	.RDslct1(RDslct1),
	.RDslct2(RDslct2),
	.RDslct3(RDslct3),
	.RDslct4(RDslct4),
	.Reset(Reset),
	.Sclk(Sclk),
	.ch0in(Channel1),
	.ch1in(Channel2),
	.outDATA(outDATA)
);



HomeConfig U4
(
	.HF1(HF1int),
	.HF2(HF2int),
	.Home_Encoder1(Home_Encoder1),
	.Home_Encoder2(Home_Encoder2),
	.RDslct(RDslct5),
	.Reset(Reset),
	.Sclk(Sclk),
	.WRslct(WRslct),
	.Zero1(Zero1),
	.Zero2(Zero2),
	.inDATA(inDATA),
	.outDATA(outDATA),
	.sense1(NET2948),
	.sense2(NET2937)
);



Counter U5
(
	.Reset(Reset),
	.Sclk(Sclk),
	.Zero(Zero2),
	.ce(ce2),
	.count(Channel2),
	.sense(NET2937),
	.updown(updown2)
);



Decode U6
(
	.Reset(Reset),
	.Sclk(Sclk),
	.ce(ce2),
	.phaseA(PhaseA_Encoder2),
	.phaseB(PhaseB_Encoder2),
	.updown(updown2)
);



endmodule