[AHDL]
Type=Implementation
Handle=197766
Project=c:\Projects\genosensor\2g\CPLDs\Core\U4\U4.adf
[Xilinx]
Path=C:\Xilinx\bin\nt
[GUI]
AutoClose=0
[Design.PartSelector]
Family=COOLRUNNER
Device=r3384xlTQ144
Speed=-7
Part=r3384xlTQ144-7
[Design.Input]
Netlist=c:\Projects\genosensor\2g\CPLDs\Core\U4\synthesis\U4.ngc
UCF=C:\Projects\genosensor\2g\CPLDs\Core\U4\src\U4.ucf
OutputPath=c:\Projects\genosensor\2g\CPLDs\Core\U4\implement
StdOutputFile=c:\Projects\genosensor\2g\CPLDs\Core\U4\log\implementation.htm
Version=ver0
Revision=rev1
Format=Verilog
EffortLevel=2
Mode=batch
InferPadEdif=0
GenerateBit=0
XON=1
Corelate=1
CPLDFitCmd= -inreg on -optimize density -inputs 32 -slew slow -loc on -nofbnand -init low -pterms 40
ExeName=ise.exe
ImplToolName=MV_ISE61
SynthToolName=MV_XST6
DirectoryList={c:\Projects\genosensor\2g\CPLDs\Core\U4\synthesis} {c:\Projects\genosensor\2g\CPLDs\Core\U4\compile} {c:\Projects\genosensor\2g\CPLDs\Core\U4\src} {C:\Program Files\Aldec\Active-HDL 6.2\vlib\XC9500\compile}
DestinationPath=c:\Projects\genosensor\2g\CPLDs\Core\U4\implement
ClbPackingStrategy=100
PackClbRegisters=Structure
PackIoRegisters=Inputs and Outputs
UseBufg=0
IgnoreRlocConstr=1
DetailedReport=0
use_ngdbuild_file=0
use_par_file=0
use_map_file=0
use_trace_file=0
use_netgen_file=0
use_cpld_ndg2vhdl_file=0
use_cgsm_ndg2vhdl_file=0
use_bitgen_file=0
use_use_cpldfit_file=0
use_hprep6_file=0
use_tsim_file=0
prog_gnd_pins=1
NPL_File=implement.npl
[Engine.Command]
Command=Implement
[Ngdbuild]
Switches=   
[Map]
Switches=   
[Par]
Switches= 
[Netgen]
Switches= 
[Cpldfit]
Switches=    -blkfanin  36 
[Engine.Implement.Output]
Changed=1
Stage=Bitstream
State=OK
Netlist=C:/PROJECTS/GENOSENSOR/2G/CPLDS/CORE/U4/IMPLEMENT/TIME_SIM.V
SDF=C:/PROJECTS/GENOSENSOR/2G/CPLDS/CORE/U4/IMPLEMENT/TIME_SIM.SDF
Abort=NO
Errors=0
Warnings=55
Status=Warning
[Engine.Reports.Output]
Path=c:/Projects/genosensor/2g/CPLDs/Core/U4/implement/ver0/rev1
Files=U4.bld U4.rpt implementation.htm
Names=Translation Fitting {Implement Log}