//--------------------------------------------------------------------------------------------------
//
// Title       : BitCounter
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\genosensor\2g\cplds\core\u4\src\BitCounter.v
// Generated   : Fri Feb 20 16:17:40 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {BitCounter}}
module BitCounter ( counter ,DriveSCL ,rdslct ,NegSCL ,NegInc ,SCLint ,SCLreset ,Mclk );

input rdslct ;
wire rdslct ;
input NegSCL ;
wire NegSCL ;
input NegInc ;
wire NegInc ;
input SCLreset ;
wire SCLreset ;
input Mclk ;
wire Mclk ;

output [5:0] counter ;
wire [5:0] counter ;
output SCLint ;
wire SCLint ;

inout DriveSCL ;
wire DriveSCL ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [5:0] counterr;

assign SCLint = (counterr == 6'b0) ? 1'b1 : 1'b0;

assign DriveSCL = (counterr == 6'b0) ? 1'b0 : 1'bz;

assign counter = (rdslct) ? counterr : 6'bz;

always @ (posedge Mclk)
	begin
		if (SCLreset) counterr <= 6'd9;  //reset to 9 which releases SCL and prepares for counting
		else
		case ({SCLreset,NegInc,NegSCL})
			3'b100,
			3'b101,
			3'b110,
			3'b111 : counterr <= 6'd9;   //reset when Reset high
			3'b000 : counterr <= counterr; //do nothing condition
			3'b001 : counterr <= ((counterr == 6'b0) ? 6'b0 : (counterr - 6'd1));  //subtract one	if not 0
			3'b010 : counterr <= counterr + 6'd9; //add 9 more
			3'b011 : counterr <= counterr + 6'd8; //add 9 , subtract 1
	 	endcase
	end

endmodule