//--------------------------------------------------------------------------------------------------
//
// Title       : Holdreg
// Design      : quaddecode
// Author      : mbari585
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\genosensor\ESP 2003\quaddecode\quaddecode\src\Holdreg.v
// Generated   : Mon Oct 21 08:20:12 2002
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {Holdreg}}
module Holdreg ( RDslct4 ,outDATA ,ch0in ,ch1in ,Reset ,Sclk ,RDslct1 ,RDslct2 ,RDslct3 );

input RDslct4 ;
wire RDslct4 ;
input [23:0] ch0in ;
wire [23:0] ch0in ;
input [23:0] ch1in ;
wire [23:0] ch1in ;
input Reset ;
wire Reset ;
input Sclk ;
wire Sclk ;
input RDslct1 ;
wire RDslct1 ;
input RDslct2 ;
wire RDslct2 ;
input RDslct3 ;
wire RDslct3 ;

output [7:0] outDATA ;
wire [7:0] outDATA ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

//how this works
//read from register 0 loads into holding register ch0 counter
//read from register 1 loads into holding register ch1 counter
//read from reg 0 or 1 makes holding reg 7:0 available on output
//read from reg 2 makes holding reg 15:8 avaiable
//read from reg 3 makes holding reg 23:16 available
//so to read a counter, first strobe initial ADDR 0 or 1.
//Then raise RD and then read the DATA, and lower RD.
//Then Strobe ADDR 2, and then Raise Read

//reg rdyreg;
reg [23:0] holdingreg;
wire [7:0] interDATA;

///define output muliplexer	  
//synthesis attribute KEEP of interDATA is TRUE;
assign interDATA = (RDslct1) ? holdingreg[7:0] :
			 	 (RDslct2) ? holdingreg[7:0] :
			 	 (RDslct3) ? holdingreg[15:8] :
			 	 (RDslct4) ? holdingreg[23:16] :
			 	  8'bz;

assign outDATA = interDATA;

always @ (negedge Sclk)	 //this should run on the neg edge since the counter runs on the positive
	begin
		if (Reset)				// reset all the registers
			begin
				holdingreg <= 24'b0;
				//rdyreg <= 1'b0;
			end				
		else
			begin
				//rdyreg <= (RDslct1 | RDslct2); 	//rdy reg is used to let the processor know that it has
				//latched the data and is ready for reading.
				//This is not really needed any more.
				if (RDslct1) holdingreg <= ch0in; 		//clock in the data from the requested
				else if (RDslct2) holdingreg <= ch1in;	//register for reading
				else holdingreg <= holdingreg;
			end	
	end
endmodule