//--------------------------------------------------------------------------------------------------
//
// Title       : EncReader
// Design      : U4
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\compile\encreader.v
// Generated   : Tue May  4 09:52:46 2004
// From        : c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src\encreader.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps

module EncReader (DRV0HIGHr,DRV0LOWr,DRV1HIGHr,DRV1LOWr,DRV2HIGHr,DRV2LOWr,DRV3HIGHr,DRV3LOWr,DRVCTLw,DRVSTATr,
Mclk,Reset,Rflg0,Rflg1,Rflg2,Rflg3,data0,data1,data2,data3,
inDATA,ENCint,Renable0,Renable1,Renable2,Renable3,SSclk0,SSclk1,SSclk2,SSclk3,
outDATA) ;

// ------------ Port declarations --------- //
input DRV0HIGHr;
wire DRV0HIGHr;
input DRV0LOWr;
wire DRV0LOWr;
input DRV1HIGHr;
wire DRV1HIGHr;
input DRV1LOWr;
wire DRV1LOWr;
input DRV2HIGHr;
wire DRV2HIGHr;
input DRV2LOWr;
wire DRV2LOWr;
input DRV3HIGHr;
wire DRV3HIGHr;
input DRV3LOWr;
wire DRV3LOWr;
input DRVCTLw;
wire DRVCTLw;
input DRVSTATr;
wire DRVSTATr;
input Mclk;
wire Mclk;
input Reset;
wire Reset;
input Rflg0;
wire Rflg0;
input Rflg1;
wire Rflg1;
input Rflg2;
wire Rflg2;
input Rflg3;
wire Rflg3;
input data0;
wire data0;
input data1;
wire data1;
input data2;
wire data2;
input data3;
wire data3;
input [7:0] inDATA;
wire [7:0] inDATA;
output ENCint;
wire ENCint;
output Renable0;
wire Renable0;
output Renable1;
wire Renable1;
output Renable2;
wire Renable2;
output Renable3;
wire Renable3;
output SSclk0;
wire SSclk0;
output SSclk1;
wire SSclk1;
output SSclk2;
wire SSclk2;
output SSclk3;
wire SSclk3;
output [7:0] outDATA;
wire [7:0] outDATA;

// ----------- Signal declarations -------- //
wire NET266;
wire NET282;

// -------- Component instantiations -------//

EncoderControl U1
(
	.DAV(outDATA[0]),
	.DRVCTLw(DRVCTLw),
	.DRVSTATr(DRVSTATr),
	.Eclk(NET266),
	.Mclk(Mclk),
	.Reset(Reset),
	.Shift(NET282),
	.Start(inDATA[0])
);



EncShift U2
(
	.Data(data0),
	.Eclkin(NET266),
	.Eclkout(SSclk0),
	.LSByte(DRV0LOWr),
	.MSByte(DRV0HIGHr),
	.Mclk(Mclk),
	.PWRenc(Renable0),
	.PWRflag(Rflg0),
	.PWRflg(outDATA[4]),
	.PWRflgr(DRVSTATr),
	.Reset(Reset),
	.Shift(NET282),
	.State(inDATA[4]),
	.outDATA(outDATA),
	.setPWR(DRVCTLw)
);



EncShift U3
(
	.Data(data1),
	.Eclkin(NET266),
	.Eclkout(SSclk1),
	.LSByte(DRV1LOWr),
	.MSByte(DRV1HIGHr),
	.Mclk(Mclk),
	.PWRenc(Renable1),
	.PWRflag(Rflg1),
	.PWRflg(outDATA[5]),
	.PWRflgr(DRVSTATr),
	.Reset(Reset),
	.Shift(NET282),
	.State(inDATA[5]),
	.outDATA(outDATA),
	.setPWR(DRVCTLw)
);



EncShift U4
(
	.Data(data2),
	.Eclkin(NET266),
	.Eclkout(SSclk2),
	.LSByte(DRV2LOWr),
	.MSByte(DRV2HIGHr),
	.Mclk(Mclk),
	.PWRenc(Renable2),
	.PWRflag(Rflg2),
	.PWRflg(outDATA[6]),
	.PWRflgr(DRVSTATr),
	.Reset(Reset),
	.Shift(NET282),
	.State(inDATA[6]),
	.outDATA(outDATA),
	.setPWR(DRVCTLw)
);



EncShift U5
(
	.Data(data3),
	.Eclkin(NET266),
	.Eclkout(SSclk3),
	.LSByte(DRV3LOWr),
	.MSByte(DRV3HIGHr),
	.Mclk(Mclk),
	.PWRenc(Renable3),
	.PWRflag(Rflg3),
	.PWRflg(outDATA[7]),
	.PWRflgr(DRVSTATr),
	.Reset(Reset),
	.Shift(NET282),
	.State(inDATA[7]),
	.outDATA(outDATA),
	.setPWR(DRVCTLw)
);



ENCinterrupt U6
(
	.DRVCTLw(DRVCTLw),
	.DRVSTATr(DRVSTATr),
	.ENCint(ENCint),
	.Mclk(Mclk),
	.PWRflg0(outDATA[4]),
	.PWRflg1(outDATA[5]),
	.PWRflg2(outDATA[6]),
	.PWRflg3(outDATA[7]),
	.PWRflgIEw(inDATA[1]),
	.Reset(Reset),
	.outDATA(outDATA[3:1])
);



endmodule 
