//--------------------------------------------------------------------------------------------------
//
// Title       : ValveTranslator
// Design      : U4
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src\ValveTranslator.v
// Generated   : Tue May  4 07:54:38 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {ValveTranslator}}
module ValveTranslator ( Reset ,DRVVALV0w ,VAH0 ,VBH0 ,VAH1 ,inDATA ,VBH1 ,VAH2 ,VAH3 ,VBH2 ,VAH4 ,VBH3 ,VAL0 ,VAH5 ,VBH4 ,VBL0 ,VAL1 ,VAH6 ,VBH5 ,VBL1 ,VAL2 ,VAH7 ,VBH6 ,VAL3 ,VBL2 ,VBH7 ,VAL4 ,VBL3 ,VAL5 ,VBL4 ,VAL6 ,VBL5 ,VAL7 ,VBL6 ,VBL7 ,Mclk ,DRVVALV1w );

input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input DRVVALV0w ;
wire DRVVALV0w ;
input DRVVALV1w ;
wire DRVVALV1w ;
input Mclk ;
wire Mclk ;

output VAH0 ;
wire VAH0 ;
output VBH0 ;
wire VBH0 ;
output VAH1 ;
wire VAH1 ;
output VBH1 ;
wire VBH1 ;
output VAH2 ;
wire VAH2 ;
output VBH2 ;
wire VBH2 ;
output VAH3 ;
wire VAH3 ;
output VAH4 ;
wire VAH4 ;
output VAL0 ;
wire VAL0 ;
output VBH3 ;
wire VBH3 ;
output VAH5 ;
wire VAH5 ;
output VBH4 ;
wire VBH4 ;
output VBL0 ;
wire VBL0 ;
output VAL1 ;
wire VAL1 ;
output VAH6 ;
wire VAH6 ;
output VBH5 ;
wire VBH5 ;
output VBL1 ;
wire VBL1 ;
output VAL2 ;
wire VAL2 ;
output VAH7 ;
wire VAH7 ;
output VBH6 ;
wire VBH6 ;
output VBL2 ;
wire VBL2 ;
output VAL3 ;
wire VAL3 ;
output VBH7 ;
wire VBH7 ;
output VAL4 ;
wire VAL4 ;
output VBL3 ;
wire VBL3 ;
output VAL5 ;
wire VAL5 ;
output VBL4 ;
wire VBL4 ;
output VAL6 ;
wire VAL6 ;
output VBL5 ;
wire VBL5 ;
output VAL7 ;
wire VAL7 ;
output VBL6 ;
wire VBL6 ;
output VBL7 ;
wire VBL7 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

function xlator;
input Vset;
input Vother;
input Dset;
input Dother;
xlator = (Vset & !Vother & !Dother) | (!Vset & Vother & Dset & !Dother);
endfunction

reg [1:0] V7,V6,V5,V4,V3,V2,V1,V0;

assign VAH0 = V0[0];
assign VBL0 = V0[0];
assign VBH0 = V0[1];
assign VAL0 = V0[1];

assign VAH1 = V1[0];
assign VBL1 = V1[0];
assign VBH1 = V1[1];
assign VAL1 = V1[1];

assign VAH2 = V2[0];
assign VBL2 = V2[0];
assign VBH2 = V2[1];
assign VAL2 = V2[1];

assign VAH3 = V3[0];
assign VBL3 = V3[0];
assign VBH3 = V3[1];
assign VAL3 = V3[1];

assign VAH4 = V4[0];
assign VBL4 = V4[0];
assign VBH4 = V4[1];
assign VAL4 = V4[1];

assign VAH5 = V5[0];
assign VBL5 = V5[0];
assign VBH5 = V5[1];
assign VAL5 = V5[1];

assign VAH6 = V6[0];
assign VBL6 = V6[0];
assign VBH6 = V6[1];
assign VAL6 = V6[1];

assign VAH7 = V7[0];
assign VBL7 = V7[0];
assign VBH7 = V7[1];
assign VAL7 = V7[1];

always @ (negedge Mclk)
	begin
		if (Reset) {V7,V6,V5,V4,V3,V2,V1,V0} <= 16'b0;	
		else if (DRVVALV0w)
			begin 
				V0[0] <= xlator(inDATA[0],inDATA[1],V0[0],V0[1]);
				V0[1] <= xlator(inDATA[1],inDATA[0],V0[1],V0[0]);
				V1[0] <= xlator(inDATA[2],inDATA[3],V1[0],V1[1]);
				V1[1] <= xlator(inDATA[3],inDATA[2],V1[1],V1[0]);
				V2[0] <= xlator(inDATA[4],inDATA[5],V2[0],V2[1]);
				V2[1] <= xlator(inDATA[5],inDATA[4],V2[1],V2[0]);
				V3[0] <= xlator(inDATA[6],inDATA[7],V3[0],V3[1]);
				V3[1] <= xlator(inDATA[7],inDATA[6],V3[1],V3[0]);
			end
		else if (DRVVALV1w)
			begin 
				V4[0] <= xlator(inDATA[0],inDATA[1],V4[0],V4[1]);
				V4[1] <= xlator(inDATA[1],inDATA[0],V4[1],V4[0]);
				V5[0] <= xlator(inDATA[2],inDATA[3],V5[0],V5[1]);
				V5[1] <= xlator(inDATA[3],inDATA[2],V5[1],V5[0]);
				V6[0] <= xlator(inDATA[4],inDATA[5],V6[0],V6[1]);
				V6[1] <= xlator(inDATA[5],inDATA[4],V6[1],V6[0]);
				V7[0] <= xlator(inDATA[6],inDATA[7],V7[0],V7[1]);
				V7[1] <= xlator(inDATA[7],inDATA[6],V7[1],V7[0]);
			end
		else {V7,V6,V5,V4,V3,V2,V1,V0} <= {V7,V6,V5,V4,V3,V2,V1,V0};
	end
endmodule
