//--------------------------------------------------------------------------------------------------
//
// Title       : EncShift
// Design      : U4
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\genosensor\2g\cplds\rvavle\rvalve\u4\src\EncShift.v
// Generated   : Fri Apr 30 14:47:13 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {EncShift}}
module EncShift ( State ,PWRflg ,outDATA ,PWRflag ,LSByte ,Reset ,PWRflgr ,MSByte ,setPWR ,Eclkin ,Eclkout ,Mclk ,Data ,Shift ,PWRenc );

input State ;
wire State ;
input PWRflag ;
wire PWRflag ;
input LSByte ;
wire LSByte ;
input Reset ;
wire Reset ;
input PWRflgr ;
wire PWRflgr ;
input MSByte ;
wire MSByte ;
input setPWR ;
wire setPWR ;
input Eclkin ;
wire Eclkin ;
input Mclk ;
wire Mclk ;
input Data ;
wire Data ;
input Shift ;
wire Shift ;

output PWRflg ;
wire PWRflg ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output PWRenc ;
wire PWRenc ;
output Eclkout ;
wire Eclkout ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [8:0] EncReg; 
reg EncPWR;

assign outDATA = (MSByte) ? {7'b0, EncReg[8]} :
				(LSByte) ? (EncReg[7:0]) : 8'bz;

assign PWRenc = !EncPWR;   //send control signal to enable encoder

assign PWRflg = (PWRflgr) ? PWRflag : 1'bz;  // the read back of the error flag

assign Eclkout = (EncPWR) ? Eclkin : 1'bz;	 //do not generate the Eclk if not on

always @ (negedge Mclk)
	begin
		if (Reset) EncPWR <= 1'b0;
		else if (setPWR) EncPWR <= State;
		else EncPWR <= EncPWR;
	end	
	
always @ (posedge Mclk)
	begin
		if (Reset) EncReg <= 9'b0;
		else if (EncPWR & Shift) EncReg[8:0] <= {EncReg[7:0],Data};
	end																		
endmodule
