//--------------------------------------------------------------------------------------------------
//
// Title       : ENCinterrupt
// Design      : U4
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\u4\src\ENCinterrupt.v
// Generated   : Mon May  3 07:39:14 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {ENCinterrupt}}
module ENCinterrupt ( ENCint ,outDATA ,PWRflg0 ,PWRflg1 ,Reset ,PWRflg2 ,PWRflg3 ,DRVCTLw ,Mclk ,PWRflgIEw ,DRVSTATr );

input PWRflg0 ;
wire PWRflg0 ;
input PWRflg1 ;
wire PWRflg1 ;
input Reset ;
wire Reset ;
input PWRflg2 ;
wire PWRflg2 ;
input PWRflg3 ;
wire PWRflg3 ;
input DRVCTLw ;
wire DRVCTLw ;
input Mclk ;
wire Mclk ;
input PWRflgIEw ;
wire PWRflgIEw ;
input DRVSTATr ;
wire DRVSTATr ;

output ENCint ;
wire ENCint ;
output [3:1] outDATA ;
wire [3:1] outDATA ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg PWRflgier;
wire intENCint;

assign outDATA[1] = (DRVSTATr) ? PWRflgier : 1'bz;
assign outDATA[2] = (DRVSTATr) ? 1'b0 : 1'bz;
assign outDATA[3] = (DRVSTATr) ? 1'b0 : 1'bz;

assign intENCint = (PWRflgier) & (!PWRflg0 | !PWRflg1 | !PWRflg3 | !PWRflg2);
assign ENCint = (intENCint) ? 1'b0 : 1'bz;

always @ (negedge Mclk)
	begin
		if (Reset) PWRflgier <= 1'b0;
		else if (DRVCTLw) PWRflgier <= PWRflgIEw;
		else PWRflgier <= PWRflgier;
	end
endmodule
