//--------------------------------------------------------------------------------------------------
//
// Title       : U4
// Design      : U4
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\compile\U4.v
// Generated   : Wed May 19 06:46:00 2004
// From        : c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src\U4.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ns / 1ns
//synthesis attribute KEEP of DRVSTATr is TRUE;
//synthesis attribute KEEP of DRVCTLw is TRUE;
//synthesis attribute KEEP of DRV0LOWr is TRUE;
//synthesis attribute KEEP of DRV0HIGHr is TRUE;
//synthesis attribute KEEP of DRV1LOWr is TRUE;
//synthesis attribute KEEP of DRV1HIGHr is TRUE;
//synthesis attribute KEEP of DRV2LOWr is TRUE;
//synthesis attribute KEEP of DRV2HIGHr is TRUE;
//synthesis attribute KEEP of DRV3LOWr is TRUE;
//synthesis attribute KEEP of DRV3HIGHr is TRUE;
//synthesis attribute KEEP of DRVMTRCTLw is TRUE;
//synthesis attribute KEEP of DRVVALV0w is TRUE;
//synthesis attribute KEEP of DRVVALV1w is TRUE;
//synthesis attribute KEEP of DRVCURSELw is TRUE;

module U4 (AS,BUSReset,GPIO8,GPIO9,Mclk,R0data,R0flg,R1data,R1flg,R2data,
R2flg,R3data,R3flg,RD,WR,AS0,AS1,AS2,BusINT,Current_enable,
Heater_Control,Motor1_Phase_A_HIN,Motor1_Phase_A_LIN,Motor1_Phase_B_HIN,Motor1_Phase_B_LIN,Motor2_Phase_A_HIN,Motor2_Phase_A_LIN,Motor2_Phase_B_HIN,Motor2_Phase_B_LIN,Motor3_Phase_A_HIN,
Motor3_Phase_A_LIN,Motor3_Phase_B_HIN,Motor3_Phase_B_LIN,Motor4_Phase_A_HIN,Motor4_Phase_A_LIN,Motor4_Phase_B_HIN,Motor4_Phase_B_LIN,Motor_Power,Motor_Power_n,PhaseA_High_1,
PhaseA_High_2,PhaseA_High_3,PhaseA_High_4,PhaseA_High_5,PhaseA_High_6,PhaseA_High_7,PhaseA_High_8,PhaseA_Low_1,PhaseA_Low_2,PhaseA_Low_3,
PhaseA_Low_4,PhaseA_Low_5,PhaseA_Low_6,PhaseA_Low_7,PhaseA_Low_8,PhaseB_High_1,PhaseB_High_2,PhaseB_High_3,PhaseB_High_4,PhaseB_High_5,
PhaseB_High_6,PhaseB_High_7,PhaseB_High_8,PhaseB_Low_1,PhaseB_Low_2,PhaseB_Low_3,PhaseB_Low_4,PhaseB_Low_5,PhaseB_Low_6,PhaseB_Low_7,
PhaseB_Low_8,R0clk,R0enable,R1clk,R1enable,R2clk,R2enable,R3clk,R3enable,AD) ;

// ------------ Port declarations --------- //
input AS;
wire AS;
input BUSReset;
wire BUSReset;
input GPIO8;
wire GPIO8;
input GPIO9;
wire GPIO9;
input Mclk;
wire Mclk;
input R0data;
wire R0data;
input R0flg;
wire R0flg;
input R1data;
wire R1data;
input R1flg;
wire R1flg;
input R2data;
wire R2data;
input R2flg;
wire R2flg;
input R3data;
wire R3data;
input R3flg;
wire R3flg;
input RD;
wire RD;
input WR;
wire WR;
output AS0;
wire AS0;
output AS1;
wire AS1;
output AS2;
wire AS2;
output BusINT;
wire BusINT;
output Current_enable;
wire Current_enable;
output Heater_Control;
wire Heater_Control;
output Motor1_Phase_A_HIN;
wire Motor1_Phase_A_HIN;
output Motor1_Phase_A_LIN;
wire Motor1_Phase_A_LIN;
output Motor1_Phase_B_HIN;
wire Motor1_Phase_B_HIN;
output Motor1_Phase_B_LIN;
wire Motor1_Phase_B_LIN;
output Motor2_Phase_A_HIN;
wire Motor2_Phase_A_HIN;
output Motor2_Phase_A_LIN;
wire Motor2_Phase_A_LIN;
output Motor2_Phase_B_HIN;
wire Motor2_Phase_B_HIN;
output Motor2_Phase_B_LIN;
wire Motor2_Phase_B_LIN;
output Motor3_Phase_A_HIN;
wire Motor3_Phase_A_HIN;
output Motor3_Phase_A_LIN;
wire Motor3_Phase_A_LIN;
output Motor3_Phase_B_HIN;
wire Motor3_Phase_B_HIN;
output Motor3_Phase_B_LIN;
wire Motor3_Phase_B_LIN;
output Motor4_Phase_A_HIN;
wire Motor4_Phase_A_HIN;
output Motor4_Phase_A_LIN;
wire Motor4_Phase_A_LIN;
output Motor4_Phase_B_HIN;
wire Motor4_Phase_B_HIN;
output Motor4_Phase_B_LIN;
wire Motor4_Phase_B_LIN;
output Motor_Power;
wire Motor_Power;
output Motor_Power_n;
wire Motor_Power_n;
output PhaseA_High_1;
wire PhaseA_High_1;
output PhaseA_High_2;
wire PhaseA_High_2;
output PhaseA_High_3;
wire PhaseA_High_3;
output PhaseA_High_4;
wire PhaseA_High_4;
output PhaseA_High_5;
wire PhaseA_High_5;
output PhaseA_High_6;
wire PhaseA_High_6;
output PhaseA_High_7;
wire PhaseA_High_7;
output PhaseA_High_8;
wire PhaseA_High_8;
output PhaseA_Low_1;
wire PhaseA_Low_1;
output PhaseA_Low_2;
wire PhaseA_Low_2;
output PhaseA_Low_3;
wire PhaseA_Low_3;
output PhaseA_Low_4;
wire PhaseA_Low_4;
output PhaseA_Low_5;
wire PhaseA_Low_5;
output PhaseA_Low_6;
wire PhaseA_Low_6;
output PhaseA_Low_7;
wire PhaseA_Low_7;
output PhaseA_Low_8;
wire PhaseA_Low_8;
output PhaseB_High_1;
wire PhaseB_High_1;
output PhaseB_High_2;
wire PhaseB_High_2;
output PhaseB_High_3;
wire PhaseB_High_3;
output PhaseB_High_4;
wire PhaseB_High_4;
output PhaseB_High_5;
wire PhaseB_High_5;
output PhaseB_High_6;
wire PhaseB_High_6;
output PhaseB_High_7;
wire PhaseB_High_7;
output PhaseB_High_8;
wire PhaseB_High_8;
output PhaseB_Low_1;
wire PhaseB_Low_1;
output PhaseB_Low_2;
wire PhaseB_Low_2;
output PhaseB_Low_3;
wire PhaseB_Low_3;
output PhaseB_Low_4;
wire PhaseB_Low_4;
output PhaseB_Low_5;
wire PhaseB_Low_5;
output PhaseB_Low_6;
wire PhaseB_Low_6;
output PhaseB_Low_7;
wire PhaseB_Low_7;
output PhaseB_Low_8;
wire PhaseB_Low_8;
output R0clk;
wire R0clk;
output R0enable;
wire R0enable;
output R1clk;
wire R1clk;
output R1enable;
wire R1enable;
output R2clk;
wire R2clk;
output R2enable;
wire R2enable;
output R3clk;
wire R3clk;
output R3enable;
wire R3enable;
inout [7:0] AD;
wire [7:0] AD;

// ----------- Signal declarations -------- //
wire DRV0HIGHr;
wire DRV0LOWr;
wire DRV1HIGHr;
wire DRV1LOWr;
wire DRV2HIGHr;
wire DRV2LOWr;
wire DRV3HIGHr;
wire DRV3LOWr;
wire DRVCTLw;
wire DRVCURSELw;
wire DRVMTRCTLw;
wire DRVSTATr;
wire DRVVALV0w;
wire DRVVALV1w;
wire NET3281;
wire Reset;
wire [7:0] ADDR;
wire [7:0] inDATA;
wire [7:0] outDATA;

// -------- Component instantiations -------//

Interface U1
(
	.AD(AD),
	.ADDR(ADDR),
	.AS(AS),
	.Mclk(Mclk),
	.RD(RD),
	.Reset(Reset),
	.WR(WR),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



AddressDecode U2
(
	.ADDR(ADDR),
	.DRV0HIGHr(DRV0HIGHr),
	.DRV0LOWr(DRV0LOWr),
	.DRV1HIGHr(DRV1HIGHr),
	.DRV1LOWr(DRV1LOWr),
	.DRV2HIGHr(DRV2HIGHr),
	.DRV2LOWr(DRV2LOWr),
	.DRV3HIGHr(DRV3HIGHr),
	.DRV3LOWr(DRV3LOWr),
	.DRVCTLw(DRVCTLw),
	.DRVCURSELw(DRVCURSELw),
	.DRVMTRCTLw(DRVMTRCTLw),
	.DRVSTATr(DRVSTATr),
	.DRVVALV0w(DRVVALV0w),
	.DRVVALV1w(DRVVALV1w),
	.RD(RD),
	.WR(WR)
);



EncReader U3
(
	.DRV0HIGHr(DRV0HIGHr),
	.DRV0LOWr(DRV0LOWr),
	.DRV1HIGHr(DRV1HIGHr),
	.DRV1LOWr(DRV1LOWr),
	.DRV2HIGHr(DRV2HIGHr),
	.DRV2LOWr(DRV2LOWr),
	.DRV3HIGHr(DRV3HIGHr),
	.DRV3LOWr(DRV3LOWr),
	.DRVCTLw(DRVCTLw),
	.DRVSTATr(DRVSTATr),
	.ENCint(BusINT),
	.Mclk(Mclk),
	.Renable0(R0enable),
	.Renable1(R1enable),
	.Renable2(R2enable),
	.Renable3(R3enable),
	.Reset(Reset),
	.Rflg0(R0flg),
	.Rflg1(R1flg),
	.Rflg2(R2flg),
	.Rflg3(R3flg),
	.SSclk0(R0clk),
	.SSclk1(R1clk),
	.SSclk2(R2clk),
	.SSclk3(R3clk),
	.data0(R0data),
	.data1(R1data),
	.data2(R2data),
	.data3(R3data),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



PWMTranslator U4
(
	.DRVCTLw(DRVCTLw),
	.DRVMTRCTLw(DRVMTRCTLw),
	.MTRPWR(Motor_Power),
	.MTRPWR_n(Motor_Power_n),
	.Mclk(Mclk),
	.Motor0_Phase_A_HIN(Motor1_Phase_A_HIN),
	.Motor0_Phase_A_LIN(Motor1_Phase_A_LIN),
	.Motor0_Phase_B_HIN(Motor1_Phase_B_HIN),
	.Motor0_Phase_B_LIN(Motor1_Phase_B_LIN),
	.Motor1_Phase_A_HIN(Motor2_Phase_A_HIN),
	.Motor1_Phase_A_LIN(Motor2_Phase_A_LIN),
	.Motor1_Phase_B_HIN(Motor2_Phase_B_HIN),
	.Motor1_Phase_B_LIN(Motor2_Phase_B_LIN),
	.Motor2_Phase_A_HIN(Motor3_Phase_A_HIN),
	.Motor2_Phase_A_LIN(Motor3_Phase_A_LIN),
	.Motor2_Phase_B_HIN(Motor3_Phase_B_HIN),
	.Motor2_Phase_B_LIN(Motor3_Phase_B_LIN),
	.Motor3_Phase_A_HIN(Motor4_Phase_A_HIN),
	.Motor3_Phase_A_LIN(Motor4_Phase_A_LIN),
	.Motor3_Phase_B_HIN(Motor4_Phase_B_HIN),
	.Motor3_Phase_B_LIN(Motor4_Phase_B_LIN),
	.PWMsource(GPIO8),
	.Reset(Reset),
	.inDATA(inDATA)
);



ValveTranslator U5
(
	.DRVVALV0w(DRVVALV0w),
	.DRVVALV1w(DRVVALV1w),
	.Mclk(Mclk),
	.Reset(Reset),
	.VAH0(PhaseA_High_1),
	.VAH1(PhaseA_High_2),
	.VAH2(PhaseA_High_3),
	.VAH3(PhaseA_High_4),
	.VAH4(PhaseA_High_5),
	.VAH5(PhaseA_High_6),
	.VAH6(PhaseA_High_7),
	.VAH7(PhaseA_High_8),
	.VAL0(PhaseA_Low_1),
	.VAL1(PhaseA_Low_2),
	.VAL2(PhaseA_Low_3),
	.VAL3(PhaseA_Low_4),
	.VAL4(PhaseA_Low_5),
	.VAL5(PhaseA_Low_6),
	.VAL6(PhaseA_Low_7),
	.VAL7(PhaseA_Low_8),
	.VBH0(PhaseB_High_1),
	.VBH1(PhaseB_High_2),
	.VBH2(PhaseB_High_3),
	.VBH3(PhaseB_High_4),
	.VBH4(PhaseB_High_5),
	.VBH5(PhaseB_High_6),
	.VBH6(PhaseB_High_7),
	.VBH7(PhaseB_High_8),
	.VBL0(PhaseB_Low_1),
	.VBL1(PhaseB_Low_2),
	.VBL2(PhaseB_Low_3),
	.VBL3(PhaseB_Low_4),
	.VBL4(PhaseB_Low_5),
	.VBL5(PhaseB_Low_6),
	.VBL6(PhaseB_Low_7),
	.VBL7(PhaseB_Low_8),
	.inDATA(inDATA)
);



AnalogSel U6
(
	.ACE(Current_enable),
	.AS0(AS0),
	.AS1(AS1),
	.AS2(AS2),
	.DRVCURSELw(DRVCURSELw),
	.Mclk(Mclk),
	.Reset(Reset),
	.inDATA(inDATA)
);



assign Reset = ~(BUSReset);


// ----------- Terminals assignment --------//
//	       ---- Input terminals ---         //
assign NET3281 = GPIO9;

//		   ---- Output terminals ---        //
assign Heater_Control = NET3281;

endmodule 
