//--------------------------------------------------------------------------------------------------
//
// Title       : AddressDecode
// Design      : U4
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src\AddressDecode.v
// Generated   : Wed Apr 28 09:52:32 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {AddressDecode}}
module AddressDecode ( DRV0LOWr ,DRV1LOWr ,DRV2LOWr ,DRV3LOWr ,DRVCTLw ,WR ,DRVVALV0w ,DRVVALV1w ,DRV0HIGHr ,DRV1HIGHr ,DRV2HIGHr ,DRVCURSELw ,DRV3HIGHr ,RD ,DRVMTRCTLw ,DRVSTATr ,ADDR );

input WR ;
wire WR ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input RD ;
wire RD ;

output DRV2HIGHr ;
wire DRV2HIGHr ;
output DRV0LOWr ;
wire DRV0LOWr ;
output DRVCURSELw ;
wire DRVCURSELw ;
output DRV3HIGHr ;
wire DRV3HIGHr ;
output DRV1LOWr ;
wire DRV1LOWr ;
output DRV2LOWr ;
wire DRV2LOWr ;
output DRV3LOWr ;
wire DRV3LOWr ;
output DRVCTLw ;
wire DRVCTLw ;
output DRVMTRCTLw ;
wire DRVMTRCTLw ;
output DRVSTATr ;
wire DRVSTATr ;
output DRVVALV0w ;
wire DRVVALV0w ;
output DRVVALV1w ;
wire DRVVALV1w ;
output DRV0HIGHr ;
wire DRV0HIGHr ;
output DRV1HIGHr ;
wire DRV1HIGHr ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

`include "Rvalveaddressmap.v"
//how does this thing work...
//we will no longer consider the AS in the qualification of the select assign its state is used 
//by the interface unit to autoincrement

`define READ 1
`define WRITE 0

function Select;
input [7:0] Address;
input [7:0] Location;
input RD, WR;
input RorW;
 Select =  (RorW == `WRITE) ? (RD & !WR & (ADDR == Location)) :  (!RD & WR & (ADDR ==  Location)) ;
endfunction								   

//s-ynthesis attribute KEEP of DCORr is TRUE;
//assign  DCORr = Select(ADDR, `DCOR1, RD, WR, `READ);

//synthesis attribute KEEP of DRVSTATr is TRUE;
assign  DRVSTATr = Select(ADDR, `DRVSTAT, RD, WR, `READ);

//synthesis attribute KEEP of DRVCTLw is TRUE;
assign  DRVCTLw = Select(ADDR, `DRVCTL, RD, WR, `WRITE);

//synthesis attribute KEEP of DRV0HIGHr is TRUE;
assign  DRV0HIGHr = Select(ADDR, `DRV0HIGH, RD, WR, `READ);

//synthesis attribute KEEP of DRV0LOWr is TRUE;
assign  DRV0LOWr = Select(ADDR, `DRV0LOW, RD, WR, `READ);

//synthesis attribute KEEP of DRV1HIGHr is TRUE;
assign  DRV1HIGHr = Select(ADDR, `DRV1HIGH, RD, WR, `READ);

//synthesis attribute KEEP of DRV1LOWr is TRUE;
assign  DRV1LOWr = Select(ADDR, `DRV1LOW, RD, WR, `READ);

//synthesis attribute KEEP of DRV2HIGHr is TRUE;
assign  DRV2HIGHr = Select(ADDR, `DRV2HIGH, RD, WR, `READ);

//synthesis attribute KEEP of DRV2LOWr is TRUE;
assign  DRV2LOWr = Select(ADDR, `DRV2LOW, RD, WR, `READ);

//synthesis attribute KEEP of DRV3HIGHr is TRUE;
assign  DRV3HIGHr = Select(ADDR, `DRV3HIGH, RD, WR, `READ);

//synthesis attribute KEEP of DRV3LOWr is TRUE;
assign  DRV3LOWr = Select(ADDR, `DRV3LOW, RD, WR, `READ);

//synthesis attribute KEEP of DRVMTRCTLw is TRUE;
assign  DRVMTRCTLw = Select(ADDR, `DRVMTRCTL, RD, WR, `WRITE);

//synthesis attribute KEEP of DRVVALV0w is TRUE;
assign  DRVVALV0w = Select(ADDR, `DRVVALV0, RD, WR, `WRITE);

//synthesis attribute KEEP of DRVVALV1w is TRUE;
assign  DRVVALV1w = Select(ADDR, `DRVVALV1, RD, WR, `WRITE);

//synthesis attribute KEEP of DRVCURSELw is TRUE;
assign  DRVCURSELw = Select(ADDR, `DRVCURSEL, RD, WR, `WRITE);

endmodule
