## Synthesis Log

Created on 06:46:29 05/19/04

Running XST Synthesis...
Please wait...
Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
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TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : U4.prj
Input Format : mixed
Verilog Include Directory : "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src"
Ignore Synthesis Constraint File : yes
---- Target Parameters
Output File Name : U4
Output Format : NGC
Target Device : xpla3
---- Source Options
Top Module Name : U4
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Mux Extraction : yes
Resource Sharing : yes
---- Target Options
Add IO Buffers : yes
Equivalent register Removal : yes
MACRO Preserve : yes
XOR Preserve : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
RTL Output : yes
Keep Hierarchy : yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
verilog2001 : yes
Clock Enable : yes
wysiwyg : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\compile\U4.v"
Module <U4> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\interface.v"
Module <Interface> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\AddressDecode.v"
Compiling include file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/Rvalveaddressmap.v"
Module <AddressDecode> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\compile\encreader.v"
Module <EncReader> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\EncoderControl.v"
Module <EncoderControl> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\EncShift.v"
Module <EncShift> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\ENCinterrupt.v"
Module <ENCinterrupt> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\PWMTranslator.v"
Module <PWMTranslator> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\ValveTranslator.v"
Module <ValveTranslator> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\AnalogSel.v"
Module <AnalogSel> compiled
No errors in compilation
Analysis of file <U4.prj> succeeded.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <U4>.
Module <U4> is correct for synthesis.
Analyzing module <Interface>.
Module <Interface> is correct for synthesis.
Set user-defined property "KEEP = true" for signal <Enable_AD>.
Analyzing module <AddressDecode>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Module <AddressDecode> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <DRVSTATr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRVCTLw> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV0HIGHr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV0LOWr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV1HIGHr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV1LOWr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV2HIGHr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV2LOWr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV3HIGHr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRV3LOWr> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRVMTRCTLw> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRVVALV0w> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRVVALV1w> in unit <AddressDecode>.
Set user-defined property "KEEP = TRUE" for signal <DRVCURSELw> in unit <AddressDecode>.
Analyzing module <EncReader>.
Module <EncReader> is correct for synthesis.
Analyzing module <EncoderControl>.
WARNING:Xst:863 - c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\EncoderControl.v line 37: Name conflict (<start> and <Start>, renaming start as start_rnm0).
Module <EncoderControl> is correct for synthesis.
Analyzing module <EncShift>.
Module <EncShift> is correct for synthesis.
Analyzing module <ENCinterrupt>.
Module <ENCinterrupt> is correct for synthesis.
Analyzing module <PWMTranslator>.
Calling function <B_LIN>.
Calling function <A_LIN>.
Calling function <B_HIN>.
Calling function <A_HIN>.
Calling function <B_LIN>.
Calling function <A_LIN>.
Calling function <B_HIN>.
Calling function <A_HIN>.
Calling function <B_LIN>.
Calling function <A_LIN>.
Calling function <B_HIN>.
Calling function <A_HIN>.
Calling function <B_LIN>.
Calling function <A_LIN>.
Calling function <B_HIN>.
Calling function <A_HIN>.
Module <PWMTranslator> is correct for synthesis.
Analyzing module <ValveTranslator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Calling function <xlator>.
Module <ValveTranslator> is correct for synthesis.
Analyzing module <AnalogSel>.
Module <AnalogSel> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <DRVSTATr>.
Set user-defined property "KEEP = TRUE" for signal <DRVCTLw>.
Set user-defined property "KEEP = TRUE" for signal <DRV0LOWr>.
Set user-defined property "KEEP = TRUE" for signal <DRV0HIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DRV1LOWr>.
Set user-defined property "KEEP = TRUE" for signal <DRV1HIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DRV2LOWr>.
Set user-defined property "KEEP = TRUE" for signal <DRV2HIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DRV3LOWr>.
Set user-defined property "KEEP = TRUE" for signal <DRV3HIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DRVMTRCTLw>.
Set user-defined property "KEEP = TRUE" for signal <DRVVALV0w>.
Set user-defined property "KEEP = TRUE" for signal <DRVVALV1w>.
Set user-defined property "KEEP = TRUE" for signal <DRVCURSELw>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <ENCinterrupt>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\ENCinterrupt.v.
Found 3-bit tristate buffer for signal <outDATA>.
Found 1-bit tristate buffer for signal <ENCint>.
Found 1-bit register for signal <PWRflgier>.
Summary:
inferred 4 Tristate(s).
Unit <ENCinterrupt> synthesized.
Synthesizing Unit <EncShift>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\EncShift.v.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit tristate buffer for signal <Eclkout>.
Found 1-bit tristate buffer for signal <PWRflg>.
Found 1-bit register for signal <EncPWR>.
Found 9-bit register for signal <EncReg>.
Found 8 1-bit 2-to-1 multiplexers.
Summary:
inferred 10 Tristate(s).
Unit <EncShift> synthesized.
Synthesizing Unit <EncoderControl>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\EncoderControl.v.
Found 1-bit tristate buffer for signal <DAV>.
Found 4-bit comparator greatequal for signal <$n0007> created at line 99.
Found 4-bit comparator less for signal <$n0010> created at line 79.
Found 4-bit adder for signal <$n0011> created at line 100.
Found 4-bit up counter for signal <BitCounter>.
Found 1-bit register for signal <CEr>.
Found 1-bit register for signal <DAVr>.
Found 4-bit register for signal <divider>.
Found 1-bit register for signal <Eclkr>.
Found 1-bit register for signal <Shiftr>.
Found 1-bit register for signal <SS>.
Summary:
inferred 1 Counter(s).
inferred 1 Adder/Subtracter(s).
inferred 2 Comparator(s).
inferred 1 Tristate(s).
Unit <EncoderControl> synthesized.
Synthesizing Unit <AnalogSel>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\AnalogSel.v.
WARNING:Xst:1305 - Output <ACE> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <inDATA<7:4>> is never used.
WARNING:Xst:1305 - Output <AS0> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <AS1> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <AS2> is never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <analogr> is assigned but never used.
Unit <AnalogSel> synthesized.
Synthesizing Unit <ValveTranslator>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\ValveTranslator.v.
Found 2-bit register for signal <V0>.
Found 2-bit register for signal <V1>.
Found 2-bit register for signal <V2>.
Found 2-bit register for signal <V3>.
Found 2-bit register for signal <V4>.
Found 2-bit register for signal <V5>.
Found 2-bit register for signal <V6>.
Found 2-bit register for signal <V7>.
Found 16 1-bit 2-to-1 multiplexers.
Unit <ValveTranslator> synthesized.
Synthesizing Unit <PWMTranslator>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\PWMTranslator.v.
Found 1-bit register for signal <M00>.
Found 1-bit register for signal <M01>.
Found 1-bit register for signal <M10>.
Found 1-bit register for signal <M11>.
Found 1-bit register for signal <M20>.
Found 1-bit register for signal <M21>.
Found 1-bit register for signal <M30>.
Found 1-bit register for signal <M31>.
Found 1-bit register for signal <MTRPWRr>.
Found 8 1-bit 2-to-1 multiplexers.
Unit <PWMTranslator> synthesized.
Synthesizing Unit <EncReader>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\compile\encreader.v.
WARNING:Xst:647 - Input <inDATA<3:2>> is never used.
Unit <EncReader> synthesized.
Synthesizing Unit <AddressDecode>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\AddressDecode.v.
Unit <AddressDecode> synthesized.
Synthesizing Unit <Interface>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\src\interface.v.
Found 8-bit tristate buffer for signal <AD>.
Found 8-bit comparator lessequal for signal <$n0007> created at line 84.
Found 8-bit comparator greatequal for signal <$n0008> created at line 84.
Found 8-bit comparator lessequal for signal <$n0009> created at line 102.
Found 8-bit adder for signal <$n0013> created at line 102.
Found 8-bit comparator less for signal <$n0015> created at line 102.
Found 8-bit register for signal <ADDR_reg>.
Found 1-bit register for signal <ASedge>.
Found 1-bit register for signal <AutoInc>.
Found 1-bit register for signal <WRRDedge>.
Summary:
inferred 3 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 4 Comparator(s).
inferred 8 Tristate(s).
Unit <Interface> synthesized.
Synthesizing Unit <U4>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src/.\..\compile\U4.v.
Unit <U4> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 44
1-bit register : 38
8-bit register : 1
9-bit register : 4
4-bit register : 1
# Counters : 1
4-bit up counter : 1
# Multiplexers : 28
2-to-1 multiplexer : 28
# Tristates : 18
1-bit tristate buffer : 13
8-bit tristate buffer : 5
# Adders/Subtractors : 2
4-bit adder : 1
8-bit adder : 1
# Comparators : 6
4-bit comparator greatequal : 1
4-bit comparator less : 1
8-bit comparator lessequal : 2
8-bit comparator greatequal : 1
8-bit comparator less : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1348 - Unit Interface is merged (output interface has tristates)
WARNING:Xst:1348 - Unit EncShift is merged (output interface has tristates)
WARNING:Xst:1348 - Unit EncReader is merged (output interface has tristates)
WARNING:Xst:1348 - Unit ENCinterrupt is merged (output interface has tristates)
Optimizing unit <U4> ...
implementation constraint: KEEP : DRV3HIGHr
implementation constraint: KEEP : DRVVALV0w
implementation constraint: KEEP : DRVMTRCTLw
implementation constraint: KEEP : DRVVALV1w
implementation constraint: KEEP : DRV2LOWr
implementation constraint: KEEP : DRVCURSELw
implementation constraint: KEEP : DRVCTLw
implementation constraint: KEEP : DRV0HIGHr
implementation constraint: KEEP : DRVSTATr
implementation constraint: KEEP : DRV1LOWr
implementation constraint: KEEP : DRV3LOWr
implementation constraint: KEEP : DRV1HIGHr
implementation constraint: KEEP : DRV2HIGHr
implementation constraint: KEEP : DRV0LOWr
implementation constraint: KEEP : U1_Enable_AD
Optimizing unit <AddressDecode> ...
Optimizing unit <AnalogSel> ...
Optimizing unit <PWMTranslator> ...
Optimizing unit <ValveTranslator> ...
Optimizing unit <EncoderControl> ...
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : U4.ngr
Top Level Output File Name : U4
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : yes
Target Technology : xpla3
Macro Preserve : yes
XOR Preserve : yes
Clock Enable : yes
wysiwyg : no
Design Statistics
# IOs : 87
Macro Statistics :
# Registers : 3
# 1-bit register : 3
# Tristates : 18
# 1-bit tristate buffer : 13
# 8-bit tristate buffer : 5
# Comparators : 6
# 4-bit comparator greatequal : 1
# 4-bit comparator less : 1
# 8-bit comparator greatequal : 1
# 8-bit comparator less : 1
# 8-bit comparator lessequal : 2
# Xors : 21
# 1-bit xor2 : 21
Cell Usage :
# BELS : 808
# AND2 : 365
# AND3 : 29
# AND4 : 6
# GND : 5
# INV : 315
# OR2 : 75
# XOR2 : 13
# FlipFlops/Latches : 90
# FD : 12
# FDCE : 78
# Tri-States : 40
# BUFE : 40
# IO Buffers : 87
# IBUF : 15
# IOBUFE : 8
# OBUF : 59
# OBUFE : 5
=========================================================================
CPU : 2.20 / 4.53 s | Elapsed : 2.00 / 4.00 s
-->
Total memory usage is 53800 kilobytes
Processing design ...
Writing file U4.v completed.
Synthesis finished with warnings.