## Implement Log

Created on 13:37:09 05/12/04

InputFile = c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/implement/xie0.ini
Executing C:\Xilinx\bin\nt\ngdbuild.exe -p R3384XLTQ144-10 -sd "c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\synthesis" -sd "c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\compile" -sd "c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src" -sd "C:\Program Files\Aldec\Active-HDL 6.2\vlib\XC9500\compile" -uc "U4.ucf" "U4.ngc" "U4.ngd"
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - ngdbuild G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p R3384XLTQ144-10 -sd
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\synthesis -sd
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\compile -sd
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src -sd "C:\Program
Files\Aldec\Active-HDL 6.2\vlib\XC9500\compile" -uc U4.ucf U4.ngc U4.ngd
Reading NGO file
"c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/implement/ver0/rev1/U4.ngc"
...
Reading component libraries for design expansion...
Annotating constraints to design from file "U4.ucf" ...
Checking timing specifications ...
Checking expanded design ...
NgdBuild:454 - logical net 'DRVCURSELw' has no load
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Total memory usage is 37556 kilobytes
Writing NGD file "U4.ngd" ...
Writing NGDBUILD log file "U4.bld"...
NGDBUILD done.
Executing C:\Xilinx\bin\nt\cpldfit.exe -p XCR3384XL-10-TQ144 -loc on -slew slow -init low -unused pullup -terminate float -optimize speed -nofbnand -inputs 32 -pterms 28 -inreg on -blkfanin 38 "U4.ngd"
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - CPLD Optimizer/Partitioner G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA2' is detected.
The logic is being translated to a mux implementation.
Considering device XCR3384XL-10-TQ144.
Re-checking device resources ...
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Synthesizing and Optimizing...
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Fitting...
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Design U4 has been optimized and fit into device XCR3384XL-10-TQ144.
Executing C:\Xilinx\bin\nt\tsim.exe "U4.vm6" "U4.nga"
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - CPLD Timing Simulation Interface G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Creating NGA for simulation.
Speed File: Version 6.0
Executing C:\Xilinx\bin\nt\netgen.exe -sim -ofmt verilog -sdf_path c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement "U4.nga" "c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1\time_sim.v"
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - netgen G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Reading design U4.nga ...
Flattening design ...
Flattening design completed.
Specializing design ...
Specializing design completed.
Preping physical only global signals ...
Preping design's networks ...
Preping design's macros ...
Writing Verilog SDF file
c:\projects\genosensor\2g\cplds\rvavle\rvalve\u4\implement\time_sim.sdf ...
Writing Verilog netlist file
c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/implement/ver0/rev1/time_sim.v
...
INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
simulator compile and invocation commands in order to allow proper
initialization of the design. If simulation is performed within Project
Navigator, this will be taken care of automatically. For more information on
compiling and performing Xilinx simulation, consult the online Synthesis and
Simulation Design Guide:
http://support.xilinx.com/support/software_manuals.htm
Total memory usage is 34724 kilobytes
Created netgen log file
'c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1\time_sim.n
lf'.
Executing C:\Xilinx\bin\nt\hprep6.exe -i "U4" -r jed -a -l "U4.log" -n "U4"
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\implement\ver0\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - Programming File Generator G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Implementation ver0->rev1: 0 error(s), 41 warning(s)
Implementation ended with warning(s).