I 000050 55 4827          1083102109426 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1083102109362 2004.04.27 14:41:49)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083102109362)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 58 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 58 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 70 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 74 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#79_0 (_architecture 0 0 79 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(8)(5)(15))
			)))
			(#ASSIGN#83_2 (_architecture 2 0 83 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#84_3 (_architecture 3 0 84 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(7))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#91_4 (_architecture 4 0 91 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#92_5 (_architecture 5 0 92 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#94_6 (_architecture 6 0 94 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
I 000048 55 2956          1083344036550 Shifter
(_unit VERILOG 6.349C.6.256 (Shifter 0 25 (Shifter 0 25 ))
	(_version v32)
	(_time 1083344036268 2004.04.30 09:53:56)
	(_source (\./src/shifter.v\ VERILOG (\./src/shifter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1083344036268)
		(_use )
	)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal data ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[8:0]reg~ 0 47 (_array ~reg ((_downto (i 8) (i 0))))))
		(_signal (_internal Pdatar ~[8:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#50_0 (_architecture 0 0 50 (_process (_simple)
				(_target(0))
				(_sensitivity(1)(7(8))(4)(7(d_7_0)))
			)))
			(#ALWAYS#52_1 (_architecture 1 0 52 (_process 
				(_target(7))
				(_read(6)(3)(5)(7(d_7_0))(2)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Shifter 3 -1)

)
I 000047 55 2043          1083344095753 DAVctl
(_unit VERILOG 6.349C.6.256 (DAVctl 0 25 (DAVctl 0 25 ))
	(_version v32)
	(_time 1083344095690 2004.04.30 09:54:55)
	(_source (\./src/davctl.v\ VERILOG (\./src/davctl.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1083344095690)
		(_use )
	)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAVin ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#39_0 (_architecture 0 0 39 (_process (_simple)
				(_target(0))
				(_sensitivity(2)(1))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . DAVctl 2 -1)

)
I 000054 55 3722          1083344127206 EncoderEngine
(_unit VERILOG 6.349C.6.256 (EncoderEngine 0 23 (EncoderEngine 0 23 ))
	(_version v32)
	(_time 1083344127128 2004.04.30 09:55:27)
	(_source (\./compile/encoderengine.v\ VERILOG (\./compile/encoderengine.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1083344127128)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DAV ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Reset ~wire 0 23 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 23 (_array ~reg ((_downto (i 5) (i 0))))))
		(_port (_internal SSclkb ~[5:0]reg~ 0 23 (_architecture (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal data ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal start ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_DAV ~reg 0 32 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_shift ~reg 0 37 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CurrState_Sreg0 ~[5:0]reg~ 0 83 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NextState_Sreg0 ~[5:0]reg~ 0 85 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#97_0 (_architecture 0 0 97 (_process 
				(_target(10)(7)(8))
				(_read)
				(_sensitivity(0)(6)(4)(5)(9))
			)))
			(#ALWAYS#354_1 (_architecture 1 0 354 (_process 
				(_target(9))
				(_read(1)(2)(10))
			)))
			(#ALWAYS#365_2 (_architecture 2 0 365 (_process 
				(_target(0)(5))
				(_read(1)(2)(7)(8))
			)))
			(#ALWAYS#380_3 (_architecture 3 0 380 (_process 
				(_target(3))
				(_read)
				(_sensitivity(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Sreg0_NextState begin 0 98
		)
		(_unit Sreg0_CurrentState begin 0 355
		)
		(_unit Sreg0_RegOutput begin 0 366
		)
	)
	(_model . EncoderEngine 5 -1)

)
I 000048 55 2956          1083344134926 Shifter
(_unit VERILOG 6.349C.6.256 (Shifter 0 25 (Shifter 0 25 ))
	(_version v32)
	(_time 1083344134878 2004.04.30 09:55:34)
	(_source (\./src/shifter.v\ VERILOG (\./src/shifter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1083344134878)
		(_use )
	)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal data ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[8:0]reg~ 0 47 (_array ~reg ((_downto (i 8) (i 0))))))
		(_signal (_internal Pdatar ~[8:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#50_0 (_architecture 0 0 50 (_process (_simple)
				(_target(0))
				(_sensitivity(1)(7(8))(4)(7(d_7_0)))
			)))
			(#ALWAYS#52_1 (_architecture 1 0 52 (_process 
				(_target(7))
				(_read(6)(3)(5)(7(d_7_0))(2)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Shifter 3 -1)

)
I 000047 55 4266          1083344305596 reader
(_unit VERILOG 6.349C.6.256 (reader 0 32 (reader 0 32 ))
	(_version v32)
	(_time 1083344305534 2004.04.30 09:58:25)
	(_source (\./compile/reader.v\ VERILOG (\./compile/reader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1083344305534)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk ~wire 0 32 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1330 ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET843 ~wire 0 56 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 57 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal SSclkb ~[5:0]wire~ 0 57 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#98_0 (_architecture 0 0 98 (_process (_alias ((SSclk)(SSclkb(1))))(_simple)
				(_target(7))
				(_sensitivity(11(1)))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U3 0 61 (_entity .  EncoderEngine)
		(_port
			((DAV) (NET1330))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((SSclkb) (SSclkb))
			((data) (data))
			((shift) (NET843))
			((start) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 74 (_entity .  Shifter)
		(_port
			((Mclk) (Mclk))
			((Pdata) (outDATA))
			((RVALVEHIGHr) (DRVHIGHr))
			((RVALVELOWr) (DRVLOWr))
			((Reset) (Reset))
			((data) (data))
			((shift) (NET843))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 87 (_entity .  DAVctl)
		(_port
			((DAVin) (NET1330))
			((Pdata) (outDATA))
			((RVALVESTATr) (DRVSTATr))
		)
		(_strength strong0 strong1)
	)
	(_model . reader 2 -1)

)
I 000055 55 4954          1083361214347 EncoderControl
(_unit VERILOG 6.349C.6.256 (EncoderControl 0 25 (EncoderControl 0 25 ))
	(_version v32)
	(_time 1083361214284 2004.04.30 14:40:14)
	(_source (\./src/encodercontrol.v\ VERILOG (\./src/encodercontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083361214284)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~vector~0 0 47 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal divisor ~vector~0 0 47 \4'd3\ (_entity -1 (_constant \4'd3\))))
		(_type (_internal ~vector~1 0 48 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal bits ~vector~1 0 48 \4'd10\ (_entity -1 (_constant \4'd10\))))
		(_port (_internal CE ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAV ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Shift ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Start ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal SS ~reg 0 50 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 51 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal divider ~[3:0]reg~ 0 51 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CEr ~reg 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BitCounter ~[3:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Eclkr ~reg 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Stop ~wire 0 55 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DAVr ~reg 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Shiftr ~reg 0 57 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#59_0 (_architecture 0 0 59 (_process (_simple)
				(_target(12))
				(_sensitivity(5)(10))
			)))
			(#ASSIGN#60_1 (_architecture 1 0 60 (_process (_alias ((CE)(CEr)))(_simple)
				(_target(0))
				(_sensitivity(9))
			)))
			(#ASSIGN#61_2 (_architecture 2 0 61 (_process (_alias ((Eclk)(Eclkr)))(_simple)
				(_target(5))
				(_sensitivity(11))
			)))
			(#ASSIGN#62_3 (_architecture 3 0 62 (_process (_alias ((Shift)(Shiftr)))(_simple)
				(_target(3))
				(_sensitivity(14))
			)))
			(#ASSIGN#63_4 (_architecture 4 0 63 (_process (_alias ((DAV)(DAVr)))(_simple)
				(_target(1))
				(_sensitivity(13))
			)))
			(#ALWAYS#65_5 (_architecture 5 0 65 (_process 
				(_target(7)(9)(14)(13))
				(_read(6)(2)(12)(4)(7)(8)(11)(10)(5)(13))
			)))
			(#ALWAYS#92_6 (_architecture 6 0 92 (_process 
				(_target(8)(11)(10))
				(_read(6)(2)(7)(8)(9)(11)(0)(10))
			)))
			(#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . EncoderControl 8 -1)

)
I 000049 55 4736          1083592828300 EncShift
(_unit VERILOG 6.349C.6.256 (EncShift 0 25 (EncShift 0 25 ))
	(_version v32)
	(_time 1083592828050 2004.05.03 07:00:28)
	(_source (\./src/encshift.v\ VERILOG (\./src/encshift.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1083592828050)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal State ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflg ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflag ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSByte ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflgr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MSByte ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal setPWR ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclkin ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclkout ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Data ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Shift ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRenc ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[8:0]reg~ 0 63 (_array ~reg ((_downto (i 8) (i 0))))))
		(_signal (_internal EncReg ~[8:0]reg~ 0 63 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal EncPWR ~reg 0 64 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#67_0 (_architecture 0 0 67 (_process (_simple)
				(_target(2))
				(_sensitivity(7)(15(8))(4)(15(d_7_0)))
			)))
			(#ASSIGN#69_1 (_architecture 1 0 69 (_process (_alias ((PWRenc)(EncPWR)))(_simple)
				(_target(14))
				(_sensitivity(16))
			)))
			(#ASSIGN#71_2 (_architecture 2 0 71 (_process (_simple)
				(_target(1))
				(_sensitivity(6)(3))
			)))
			(#ASSIGN#73_3 (_architecture 3 0 73 (_process (_simple)
				(_target(10))
				(_sensitivity(0)(9))
			)))
			(#ALWAYS#75_4 (_architecture 4 0 75 (_process 
				(_target(16))
				(_read(11)(5)(8)(0)(16))
			)))
			(#ALWAYS#82_5 (_architecture 5 0 82 (_process 
				(_target(15))
				(_read(11)(5)(16)(13)(15(d_7_0))(12))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . EncShift 7 -1)

)
I 000055 55 5507          1083594608832 EncoderControl
(_unit VERILOG 6.349C.6.256 (EncoderControl 0 25 (EncoderControl 0 25 ))
	(_version v32)
	(_time 1083594608769 2004.05.03 07:30:08)
	(_source (\./src/encodercontrol.v\ VERILOG (\./src/encodercontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 9))
	(_entity
		(_time 1083594608769)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~vector~0 0 27 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal divisor ~vector~0 0 27 \4'd3\ (_entity -1 (_constant \4'd3\))))
		(_type (_internal ~vector~1 0 28 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal bits ~vector~1 0 28 \4'd10\ (_entity -1 (_constant \4'd10\))))
		(_port (_internal CE ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAV ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Shift ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Start ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal SS ~reg 0 54 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 55 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal divider ~[3:0]reg~ 0 55 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CEr ~reg 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BitCounter ~[3:0]reg~ 0 57 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Eclkr ~reg 0 58 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Stop ~wire 0 59 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal start ~wire 0 60 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DAVr ~reg 0 61 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Shiftr ~reg 0 62 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#64_0 (_architecture 0 0 64 (_process (_simple)
				(_target(14))
				(_sensitivity(7)(12))
			)))
			(#ASSIGN#65_1 (_architecture 1 0 65 (_process (_alias ((CE)(CEr)))(_simple)
				(_target(0))
				(_sensitivity(11))
			)))
			(#ASSIGN#66_2 (_architecture 2 0 66 (_process (_alias ((Eclk)(Eclkr)))(_simple)
				(_target(7))
				(_sensitivity(13))
			)))
			(#ASSIGN#67_3 (_architecture 3 0 67 (_process (_alias ((Shift)(Shiftr)))(_simple)
				(_target(4))
				(_sensitivity(17))
			)))
			(#ASSIGN#68_4 (_architecture 4 0 68 (_process (_simple)
				(_target(2))
				(_sensitivity(1)(16))
			)))
			(#ASSIGN#69_5 (_architecture 5 0 69 (_process (_alias ((start)(Start)(DRVCTLw)))(_simple)
				(_target(15))
				(_sensitivity(6)(5))
			)))
			(#ALWAYS#71_6 (_architecture 6 0 71 (_process 
				(_target(9)(11)(17)(16))
				(_read(8)(3)(14)(15)(9)(10)(13)(12)(7)(16))
			)))
			(#ALWAYS#98_7 (_architecture 7 0 98 (_process 
				(_target(10)(13)(12))
				(_read(8)(3)(9)(10)(11)(13)(0)(12))
			)))
			(#INTERNAL#0_8 (_internal 8 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . EncoderControl 9 -1)

)
V 000053 55 4135          1083596164175 ENCinterrupt
(_unit VERILOG 6.349C.6.256 (ENCinterrupt 0 25 (ENCinterrupt 0 25 ))
	(_version v32)
	(_time 1083596164097 2004.05.03 07:56:04)
	(_source (\./src/encinterrupt.v\ VERILOG (\./src/encinterrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1083596164097)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal ENCint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[3:1]wire~ 0 25 (_array ~wire ((_downto (i 3) (i 1))))))
		(_port (_internal outDATA ~[3:1]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflg0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflg1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflg2 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflg3 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal PWRflgIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal PWRflgier ~reg 0 55 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal intENCint ~wire 0 56 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#58_0 (_architecture 0 0 58 (_process (_simple)
				(_target(1(1)))
				(_sensitivity(10)(11))
			)))
			(#ASSIGN#59_1 (_architecture 1 0 59 (_process (_simple)
				(_target(1(2)))
				(_sensitivity(10))
			)))
			(#ASSIGN#60_2 (_architecture 2 0 60 (_process (_simple)
				(_target(1(3)))
				(_sensitivity(10))
			)))
			(#ASSIGN#62_3 (_architecture 3 0 62 (_process (_alias ((intENCint)(PWRflgier)(PWRflg0)(PWRflg1)(PWRflg3)(PWRflg2)))(_simple)
				(_target(12))
				(_sensitivity(11)(2)(3)(6)(5))
			)))
			(#ASSIGN#63_4 (_architecture 4 0 63 (_process (_simple)
				(_target(0))
				(_sensitivity(12))
			)))
			(#ALWAYS#65_5 (_architecture 5 0 65 (_process 
				(_target(11))
				(_read(8)(4)(7)(9)(11))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . ENCinterrupt 7 -1)

)
V 000050 55 9119          1083596430614 EncReader
(_unit VERILOG 6.349C.6.256 (EncReader 0 32 (EncReader 0 32 ))
	(_version v32)
	(_time 1083596430566 2004.05.03 08:00:30)
	(_source (\./compile/encreader.v\ VERILOG (\./compile/encreader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083596430566)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal ENCint ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET266 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET282 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 107 (_entity .  EncoderControl)
		(_port
			((DAV) (outDATA(0)))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Eclk) (NET266))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((Shift) (NET282))
			((Start) (inDATA(0)))
			((CE) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 121 (_entity .  EncShift)
		(_port
			((Data) (data0))
			((Eclkin) (NET266))
			((Eclkout) (SSclk0))
			((LSByte) (DRV0LOWr))
			((MSByte) (DRV0HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable0))
			((PWRflag) (Rflg0))
			((PWRflg) (outDATA(4)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(4)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 142 (_entity .  EncShift)
		(_port
			((Data) (data1))
			((Eclkin) (NET266))
			((Eclkout) (SSclk1))
			((LSByte) (DRV1LOWr))
			((MSByte) (DRV1HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable1))
			((PWRflag) (Rflg1))
			((PWRflg) (outDATA(5)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(5)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 163 (_entity .  EncShift)
		(_port
			((Data) (data2))
			((Eclkin) (NET266))
			((Eclkout) (SSclk2))
			((LSByte) (DRV2LOWr))
			((MSByte) (DRV2HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable2))
			((PWRflag) (Rflg2))
			((PWRflg) (outDATA(6)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(6)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 184 (_entity .  EncShift)
		(_port
			((Data) (data3))
			((Eclkin) (NET266))
			((Eclkout) (SSclk3))
			((LSByte) (DRV3LOWr))
			((MSByte) (DRV3HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable3))
			((PWRflag) (Rflg3))
			((PWRflg) (outDATA(7)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(7)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 205 (_entity .  ENCinterrupt)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (ENCint))
			((Mclk) (Mclk))
			((PWRflg0) (outDATA(4)))
			((PWRflg1) (outDATA(5)))
			((PWRflg2) (outDATA(6)))
			((PWRflg3) (outDATA(7)))
			((PWRflgIEw) (inDATA(1)))
			((Reset) (Reset))
			((outDATA) (outDATA(d_3_1)))
		)
		(_strength strong0 strong1)
	)
	(_model . EncReader 1 -1)

)
I 000055 55 5243          1083596547691 EncoderControl
(_unit VERILOG 6.349C.6.256 (EncoderControl 0 25 (EncoderControl 0 25 ))
	(_version v32)
	(_time 1083596547613 2004.05.03 08:02:27)
	(_source (\./src/encodercontrol.v\ VERILOG (\./src/encodercontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083596547613)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~vector~0 0 27 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal divisor ~vector~0 0 27 \4'd3\ (_entity -1 (_constant \4'd3\))))
		(_type (_internal ~vector~1 0 28 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal bits ~vector~1 0 28 \4'd10\ (_entity -1 (_constant \4'd10\))))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAV ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Shift ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Start ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal SS ~reg 0 52 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 53 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal divider ~[3:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CEr ~reg 0 54 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BitCounter ~[3:0]reg~ 0 55 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Eclkr ~reg 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Stop ~wire 0 57 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal start ~wire 0 58 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DAVr ~reg 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Shiftr ~reg 0 60 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#62_0 (_architecture 0 0 62 (_process (_simple)
				(_target(13))
				(_sensitivity(6)(11))
			)))
			(#ASSIGN#63_1 (_architecture 1 0 63 (_process (_alias ((Eclk)(Eclkr)))(_simple)
				(_target(6))
				(_sensitivity(12))
			)))
			(#ASSIGN#64_2 (_architecture 2 0 64 (_process (_alias ((Shift)(Shiftr)))(_simple)
				(_target(3))
				(_sensitivity(16))
			)))
			(#ASSIGN#65_3 (_architecture 3 0 65 (_process (_simple)
				(_target(1))
				(_sensitivity(0)(15))
			)))
			(#ASSIGN#66_4 (_architecture 4 0 66 (_process (_alias ((start)(Start)(DRVCTLw)))(_simple)
				(_target(14))
				(_sensitivity(5)(4))
			)))
			(#ALWAYS#68_5 (_architecture 5 0 68 (_process 
				(_target(8)(10)(16)(15))
				(_read(7)(2)(13)(14)(8)(9)(12)(11)(6)(15))
			)))
			(#ALWAYS#95_6 (_architecture 6 0 95 (_process 
				(_target(9)(12)(11))
				(_read(7)(2)(8)(9)(10)(12)(16)(11))
			)))
			(#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . EncoderControl 8 -1)

)
I 000054 55 6046          1083600106442 AddressDecode
(_unit VERILOG 6.349C.6.256 (AddressDecode 0 25 (AddressDecode 0 25 ))
	(_version v32)
	(_time 1083600106363 2004.05.03 09:01:46)
	(_source (\./src/addressdecode.v\ VERILOG (\./src/addressdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 12))
	(_entity
		(_time 1083600106363)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV2HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 68 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 68 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 69 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 70 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 70 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 71 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 10 0 67 (_architecture (_function)(_target(18))
				(_read(17)(15)(16)(10)(14))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#79_0 (_architecture 0 0 79 (_process (_simple)
				(_target(9))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_simple)
				(_target(6))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#85_2 (_architecture 2 0 85 (_process (_simple)
				(_target(11))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#88_3 (_architecture 3 0 88 (_process (_simple)
				(_target(1))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#91_4 (_architecture 4 0 91 (_process (_simple)
				(_target(12))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#94_5 (_architecture 5 0 94 (_process (_simple)
				(_target(3))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#97_6 (_architecture 6 0 97 (_process (_simple)
				(_target(0))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#100_7 (_architecture 7 0 100 (_process (_simple)
				(_target(4))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#103_8 (_architecture 8 0 103 (_process (_simple)
				(_target(2))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#106_9 (_architecture 9 0 106 (_process (_simple)
				(_target(5))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#INTERNAL#0_11 (_internal 11 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 67
		)
	)
	(_model . AddressDecode 12 -1)

)
I 000043 55 8426          1083600912332 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083600912285 2004.05.03 09:15:12)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083600912285)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 34 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET409 ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET417 ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET425 ~wire 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET433 ~wire 0 86 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET451 ~wire 0 87 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET459 ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET467 ~wire 0 89 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET475 ~wire 0 90 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET483 ~wire 0 91 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET491 ~wire 0 92 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 93 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 94 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 95 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 99 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 114 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 133 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
I 000054 55 1461          1083612082081 PWMTranslator
(_unit VERILOG 6.349C.6.256 (PWMTranslator 0 25 (PWMTranslator 0 25 ))
	(_version v32)
	(_time 1083612082035 2004.05.03 12:21:22)
	(_source (\./src/pwmtranslator.v\ VERILOG (\./src/pwmtranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083612082035)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_model . PWMTranslator 1 -1)

)
I 000044 55 5442          1083613086050 MSP
(_unit VERILOG 6.349C.6.256 (MSP 0 25 (MSP 0 25 ))
	(_version v32)
	(_time 1083613085972 2004.05.03 12:38:05)
	(_source (\./src/msp.v\ VERILOG (\./src/msp.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083613085972)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 27 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal Half_period ~vector~0 0 27 \500000\ (_entity -1 (_constant \500000\))))
		(_type (_internal ~vector~1 0 28 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal BITS ~vector~1 0 28 \12\ (_entity -1 (_constant \12\))))
		(_type (_internal ~vector~2 0 29 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal WORDS ~vector~2 0 29 \159\ (_entity -1 (_constant \159\))))
		(_port (_internal WR ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASr ~reg 0 49 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRr ~reg 0 50 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDr ~reg 0 51 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Mclkr ~reg 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 53 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADr ~[7:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal busDrive ~reg 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Resetr ~reg 0 55 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~integer 0 57 (_array ~reg ((_downto (i 31) (i 0))))(_attribute signed)))
		(_signal (_internal J ~integer 0 57 (_architecture (_uni ))) (_reg integer) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[1:BITS]reg~[1:WORDS]~ 0 59 (_array ~reg ((_range  8)(_range  9)))))
		(_signal (_internal Vmem ~[1:BITS]reg~[1:WORDS]~ 0 59 (_architecture (_uni ))) (_reg memory) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_function \$readmemb\)

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#62_0 (_architecture 0 0 62 (_process (_alias ((AS)(ASr)))(_simple)
				(_target(2))
				(_sensitivity(6))
			)))
			(#ASSIGN#63_1 (_architecture 1 0 63 (_process (_alias ((RD)(RDr)))(_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#ASSIGN#64_2 (_architecture 2 0 64 (_process (_alias ((WR)(WRr)))(_simple)
				(_target(0))
				(_sensitivity(7))
			)))
			(#ASSIGN#65_3 (_architecture 3 0 65 (_process (_simple)
				(_target(3))
				(_sensitivity(11)(10))
			)))
			(#ASSIGN#66_4 (_architecture 4 0 66 (_process (_alias ((Mclk)(Mclkr)))(_simple)
				(_target(5))
				(_sensitivity(9))
			)))
			(#ASSIGN#67_5 (_architecture 5 0 67 (_process (_alias ((Reset)(Resetr)))(_simple)
				(_target(1))
				(_sensitivity(12))
			)))
			(#INITIAL#69_6 (_architecture 6 0 69 (_process 
				(_target(13)(9)(12)(6)(8)(7)(11)(10))
				(_read(14)(13))
			)))
			(#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . MSP 10 -1)

)
I 000043 55 8512          1083613277113 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083613277035 2004.05.03 12:41:17)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083613277035)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 34 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET409 ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET417 ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET425 ~wire 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET433 ~wire 0 86 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET451 ~wire 0 87 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET459 ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET467 ~wire 0 89 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET475 ~wire 0 90 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET483 ~wire 0 91 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET491 ~wire 0 92 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 93 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 94 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 95 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 99 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 114 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 133 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 169 (_entity .  PWMTranslator)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
V 000050 55 9101          1083613433770 EncReader
(_unit VERILOG 6.349C.6.256 (EncReader 0 32 (EncReader 0 32 ))
	(_version v32)
	(_time 1083613433706 2004.05.03 12:43:53)
	(_source (\./compile/encreader.v\ VERILOG (\./compile/encreader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083613433706)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal ENCint ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET266 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET282 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 107 (_entity .  EncoderControl)
		(_port
			((DAV) (outDATA(0)))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Eclk) (NET266))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((Shift) (NET282))
			((Start) (inDATA(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 121 (_entity .  EncShift)
		(_port
			((Data) (data0))
			((Eclkin) (NET266))
			((Eclkout) (SSclk0))
			((LSByte) (DRV0LOWr))
			((MSByte) (DRV0HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable0))
			((PWRflag) (Rflg0))
			((PWRflg) (outDATA(4)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(4)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 142 (_entity .  EncShift)
		(_port
			((Data) (data1))
			((Eclkin) (NET266))
			((Eclkout) (SSclk1))
			((LSByte) (DRV1LOWr))
			((MSByte) (DRV1HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable1))
			((PWRflag) (Rflg1))
			((PWRflg) (outDATA(5)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(5)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 163 (_entity .  EncShift)
		(_port
			((Data) (data2))
			((Eclkin) (NET266))
			((Eclkout) (SSclk2))
			((LSByte) (DRV2LOWr))
			((MSByte) (DRV2HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable2))
			((PWRflag) (Rflg2))
			((PWRflg) (outDATA(6)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(6)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 184 (_entity .  EncShift)
		(_port
			((Data) (data3))
			((Eclkin) (NET266))
			((Eclkout) (SSclk3))
			((LSByte) (DRV3LOWr))
			((MSByte) (DRV3HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable3))
			((PWRflag) (Rflg3))
			((PWRflg) (outDATA(7)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(7)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 205 (_entity .  ENCinterrupt)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (ENCint))
			((Mclk) (Mclk))
			((PWRflg0) (outDATA(4)))
			((PWRflg1) (outDATA(5)))
			((PWRflg2) (outDATA(6)))
			((PWRflg3) (outDATA(7)))
			((PWRflgIEw) (inDATA(1)))
			((Reset) (Reset))
			((outDATA) (outDATA(d_3_1)))
		)
		(_strength strong0 strong1)
	)
	(_model . EncReader 1 -1)

)
V 000049 55 4747          1083613462535 EncShift
(_unit VERILOG 6.349C.6.256 (EncShift 0 25 (EncShift 0 25 ))
	(_version v32)
	(_time 1083613462456 2004.05.03 12:44:22)
	(_source (\./src/encshift.v\ VERILOG (\./src/encshift.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1083613462456)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal State ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflg ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflag ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSByte ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRflgr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MSByte ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal setPWR ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclkin ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclkout ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Data ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Shift ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRenc ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[8:0]reg~ 0 63 (_array ~reg ((_downto (i 8) (i 0))))))
		(_signal (_internal EncReg ~[8:0]reg~ 0 63 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal EncPWR ~reg 0 64 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#67_0 (_architecture 0 0 67 (_process (_simple)
				(_target(2))
				(_sensitivity(7)(15(8))(4)(15(d_7_0)))
			)))
			(#ASSIGN#69_1 (_architecture 1 0 69 (_process (_alias ((PWRenc)(EncPWR)))(_simple)
				(_target(14))
				(_sensitivity(16))
			)))
			(#ASSIGN#71_2 (_architecture 2 0 71 (_process (_simple)
				(_target(1))
				(_sensitivity(6)(3))
			)))
			(#ASSIGN#73_3 (_architecture 3 0 73 (_process (_simple)
				(_target(10))
				(_sensitivity(16)(9))
			)))
			(#ALWAYS#75_4 (_architecture 4 0 75 (_process 
				(_target(16))
				(_read(11)(5)(8)(0)(16))
			)))
			(#ALWAYS#82_5 (_architecture 5 0 82 (_process 
				(_target(15))
				(_read(11)(5)(16)(13)(15(d_7_0))(12))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . EncShift 7 -1)

)
V 000050 55 3846          1083613478410 RValve_TB
(_unit VERILOG 6.349C.6.256 (RValve_TB 0 32 (RValve_TB 0 32 ))
	(_version v32)
	(_time 1083613478363 2004.05.03 12:44:38)
	(_source (\./compile/rvalve_tb.v\ VERILOG (\./compile/rvalve_tb.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1083613478363)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 35 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 35 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_signal (_internal NET58 ~wire 0 38 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET62 ~wire 0 39 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET66 ~wire 0 40 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET70 ~wire 0 41 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET74 ~wire 0 42 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 43 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal BUS78 ~[7:0]wire~ 0 43 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 46 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#46_0 (_architecture 0 0 46 (_process (_simple)
				(_target(6))
			)))
			(#INTERNAL#0_1 (_internal 1 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 50 (_entity .  U4)
		(_port
			((AD) (BUS78))
			((AS) (NET58))
			((Mclk) (NET70))
			((R0data) (Dangling_Input_Signal))
			((R0flg) (Dangling_Input_Signal))
			((R1data) (Dangling_Input_Signal))
			((R1flg) (Dangling_Input_Signal))
			((R2data) (Dangling_Input_Signal))
			((R2flg) (Dangling_Input_Signal))
			((R3data) (Dangling_Input_Signal))
			((R3flg) (Dangling_Input_Signal))
			((RD) (NET66))
			((Reset) (NET74))
			((WR) (NET62))
			((R0clk) (_open))
			((R0enable) (_open))
			((R1clk) (_open))
			((R1enable) (_open))
			((R2clk) (_open))
			((R2enable) (_open))
			((R3clk) (_open))
			((R3enable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 70 (_entity .  MSP)
		(_port
			((AD) (BUS78))
			((AS) (NET58))
			((Mclk) (NET70))
			((RD) (NET66))
			((Reset) (NET74))
			((WR) (NET62))
		)
		(_strength strong0 strong1)
	)
	(_model . RValve_TB 2 -1)

)
V 000044 55 5442          1083613488238 MSP
(_unit VERILOG 6.349C.6.256 (MSP 0 25 (MSP 0 25 ))
	(_version v32)
	(_time 1083613488160 2004.05.03 12:44:48)
	(_source (\./src/msp.v\ VERILOG (\./src/msp.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083613488160)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 27 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal Half_period ~vector~0 0 27 \500000\ (_entity -1 (_constant \500000\))))
		(_type (_internal ~vector~1 0 28 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal BITS ~vector~1 0 28 \12\ (_entity -1 (_constant \12\))))
		(_type (_internal ~vector~2 0 29 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal WORDS ~vector~2 0 29 \159\ (_entity -1 (_constant \159\))))
		(_port (_internal WR ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASr ~reg 0 49 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRr ~reg 0 50 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDr ~reg 0 51 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Mclkr ~reg 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 53 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADr ~[7:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal busDrive ~reg 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Resetr ~reg 0 55 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~integer 0 57 (_array ~reg ((_downto (i 31) (i 0))))(_attribute signed)))
		(_signal (_internal J ~integer 0 57 (_architecture (_uni ))) (_reg integer) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[1:BITS]reg~[1:WORDS]~ 0 59 (_array ~reg ((_range  8)(_range  9)))))
		(_signal (_internal Vmem ~[1:BITS]reg~[1:WORDS]~ 0 59 (_architecture (_uni ))) (_reg memory) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_function \$readmemb\)

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#62_0 (_architecture 0 0 62 (_process (_alias ((AS)(ASr)))(_simple)
				(_target(2))
				(_sensitivity(6))
			)))
			(#ASSIGN#63_1 (_architecture 1 0 63 (_process (_alias ((RD)(RDr)))(_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#ASSIGN#64_2 (_architecture 2 0 64 (_process (_alias ((WR)(WRr)))(_simple)
				(_target(0))
				(_sensitivity(7))
			)))
			(#ASSIGN#65_3 (_architecture 3 0 65 (_process (_simple)
				(_target(3))
				(_sensitivity(11)(10))
			)))
			(#ASSIGN#66_4 (_architecture 4 0 66 (_process (_alias ((Mclk)(Mclkr)))(_simple)
				(_target(5))
				(_sensitivity(9))
			)))
			(#ASSIGN#67_5 (_architecture 5 0 67 (_process (_alias ((Reset)(Resetr)))(_simple)
				(_target(1))
				(_sensitivity(12))
			)))
			(#INITIAL#69_6 (_architecture 6 0 69 (_process 
				(_target(13)(9)(12)(6)(8)(7)(11)(10))
				(_read(14)(13))
			)))
			(#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . MSP 10 -1)

)
V 000043 55 8512          1083613497394 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083613497347 2004.05.03 12:44:57)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083613497347)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 34 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET409 ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET417 ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET425 ~wire 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET433 ~wire 0 86 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET451 ~wire 0 87 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET459 ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET467 ~wire 0 89 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET475 ~wire 0 90 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET483 ~wire 0 91 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET491 ~wire 0 92 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 93 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 94 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 95 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 99 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 114 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 133 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 169 (_entity .  PWMTranslator)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
I 000055 55 5241          1083614709628 EncoderControl
(_unit VERILOG 6.349C.6.256 (EncoderControl 0 25 (EncoderControl 0 25 ))
	(_version v32)
	(_time 1083614709566 2004.05.03 13:05:09)
	(_source (\./src/encodercontrol.v\ VERILOG (\./src/encodercontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083614709566)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~vector~0 0 27 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal bits ~vector~0 0 27 \4'd9\ (_entity -1 (_constant \4'd9\))))
		(_type (_internal ~vector~1 0 28 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal divisor ~vector~1 0 28 \4'd3\ (_entity -1 (_constant \4'd3\))))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAV ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Shift ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Start ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal SS ~reg 0 52 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 53 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal divider ~[3:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CEr ~reg 0 54 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BitCounter ~[3:0]reg~ 0 55 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Eclkr ~reg 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Stop ~wire 0 57 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal start ~wire 0 58 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DAVr ~reg 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Shiftr ~reg 0 60 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#62_0 (_architecture 0 0 62 (_process (_simple)
				(_target(13))
				(_sensitivity(6)(11))
			)))
			(#ASSIGN#63_1 (_architecture 1 0 63 (_process (_alias ((Eclk)(Eclkr)))(_simple)
				(_target(6))
				(_sensitivity(12))
			)))
			(#ASSIGN#64_2 (_architecture 2 0 64 (_process (_alias ((Shift)(Shiftr)))(_simple)
				(_target(3))
				(_sensitivity(16))
			)))
			(#ASSIGN#65_3 (_architecture 3 0 65 (_process (_simple)
				(_target(1))
				(_sensitivity(0)(15))
			)))
			(#ASSIGN#66_4 (_architecture 4 0 66 (_process (_alias ((start)(Start)(DRVCTLw)))(_simple)
				(_target(14))
				(_sensitivity(5)(4))
			)))
			(#ALWAYS#68_5 (_architecture 5 0 68 (_process 
				(_target(8)(10)(16)(15))
				(_read(7)(2)(13)(14)(8)(9)(12)(11)(6)(15))
			)))
			(#ALWAYS#95_6 (_architecture 6 0 95 (_process 
				(_target(9)(12)(11))
				(_read(7)(2)(8)(9)(10)(12)(16)(11))
			)))
			(#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . EncoderControl 8 -1)

)
V 000050 55 9101          1083614725676 EncReader
(_unit VERILOG 6.349C.6.256 (EncReader 0 32 (EncReader 0 32 ))
	(_version v32)
	(_time 1083614725628 2004.05.03 13:05:25)
	(_source (\./compile/encreader.v\ VERILOG (\./compile/encreader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083614725628)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal ENCint ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET266 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET282 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 107 (_entity .  EncoderControl)
		(_port
			((DAV) (outDATA(0)))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Eclk) (NET266))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((Shift) (NET282))
			((Start) (inDATA(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 121 (_entity .  EncShift)
		(_port
			((Data) (data0))
			((Eclkin) (NET266))
			((Eclkout) (SSclk0))
			((LSByte) (DRV0LOWr))
			((MSByte) (DRV0HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable0))
			((PWRflag) (Rflg0))
			((PWRflg) (outDATA(4)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(4)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 142 (_entity .  EncShift)
		(_port
			((Data) (data1))
			((Eclkin) (NET266))
			((Eclkout) (SSclk1))
			((LSByte) (DRV1LOWr))
			((MSByte) (DRV1HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable1))
			((PWRflag) (Rflg1))
			((PWRflg) (outDATA(5)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(5)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 163 (_entity .  EncShift)
		(_port
			((Data) (data2))
			((Eclkin) (NET266))
			((Eclkout) (SSclk2))
			((LSByte) (DRV2LOWr))
			((MSByte) (DRV2HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable2))
			((PWRflag) (Rflg2))
			((PWRflg) (outDATA(6)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(6)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 184 (_entity .  EncShift)
		(_port
			((Data) (data3))
			((Eclkin) (NET266))
			((Eclkout) (SSclk3))
			((LSByte) (DRV3LOWr))
			((MSByte) (DRV3HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable3))
			((PWRflag) (Rflg3))
			((PWRflg) (outDATA(7)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(7)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 205 (_entity .  ENCinterrupt)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (ENCint))
			((Mclk) (Mclk))
			((PWRflg0) (outDATA(4)))
			((PWRflg1) (outDATA(5)))
			((PWRflg2) (outDATA(6)))
			((PWRflg3) (outDATA(7)))
			((PWRflgIEw) (inDATA(1)))
			((Reset) (Reset))
			((outDATA) (outDATA(d_3_1)))
		)
		(_strength strong0 strong1)
	)
	(_model . EncReader 1 -1)

)
I 000050 55 4827          1083616574067 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1083616573956 2004.05.03 13:36:13)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083616573956)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 67 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 69 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 71 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#80_0 (_architecture 0 0 80 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#83_1 (_architecture 1 0 83 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(8)(5)(15))
			)))
			(#ASSIGN#84_2 (_architecture 2 0 84 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#85_3 (_architecture 3 0 85 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(7))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#92_4 (_architecture 4 0 92 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#93_5 (_architecture 5 0 93 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#95_6 (_architecture 6 0 95 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
V 000043 55 8494          1083618629925 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083618629863 2004.05.03 14:10:29)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083618629863)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 34 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET409 ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET417 ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET425 ~wire 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET433 ~wire 0 86 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET451 ~wire 0 87 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET459 ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET467 ~wire 0 89 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET475 ~wire 0 90 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET483 ~wire 0 91 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET491 ~wire 0 92 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 93 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 94 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 95 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 99 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 114 (_entity .  Fub3)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 133 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 169 (_entity .  Fub6)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
I 000050 55 4827          1083618641347 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1083618641269 2004.05.03 14:10:41)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083618641269)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 67 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 69 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 71 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#80_0 (_architecture 0 0 80 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#83_1 (_architecture 1 0 83 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(8)(5)(15))
			)))
			(#ASSIGN#84_2 (_architecture 2 0 84 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#85_3 (_architecture 3 0 85 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(7))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#92_4 (_architecture 4 0 92 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#93_5 (_architecture 5 0 93 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#95_6 (_architecture 6 0 95 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
I 000054 55 6046          1083618691692 AddressDecode
(_unit VERILOG 6.349C.6.256 (AddressDecode 0 25 (AddressDecode 0 25 ))
	(_version v32)
	(_time 1083618691628 2004.05.03 14:11:31)
	(_source (\./src/addressdecode.v\ VERILOG (\./src/addressdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 12))
	(_entity
		(_time 1083618691628)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV2HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 68 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 68 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 69 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 70 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 70 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 71 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 10 0 67 (_architecture (_function)(_target(18))
				(_read(17)(15)(16)(10)(14))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#79_0 (_architecture 0 0 79 (_process (_simple)
				(_target(9))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_simple)
				(_target(6))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#85_2 (_architecture 2 0 85 (_process (_simple)
				(_target(11))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#88_3 (_architecture 3 0 88 (_process (_simple)
				(_target(1))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#91_4 (_architecture 4 0 91 (_process (_simple)
				(_target(12))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#94_5 (_architecture 5 0 94 (_process (_simple)
				(_target(3))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#97_6 (_architecture 6 0 97 (_process (_simple)
				(_target(0))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#100_7 (_architecture 7 0 100 (_process (_simple)
				(_target(4))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#103_8 (_architecture 8 0 103 (_process (_simple)
				(_target(2))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#ASSIGN#106_9 (_architecture 9 0 106 (_process (_simple)
				(_target(5))
				(_sensitivity(10)(7)(8))
				(_call(0))
			)))
			(#INTERNAL#0_11 (_internal 11 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 67
		)
	)
	(_model . AddressDecode 12 -1)

)
V 000043 55 8503          1083618701895 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083618701847 2004.05.03 14:11:41)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083618701847)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 34 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET409 ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET417 ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET425 ~wire 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET433 ~wire 0 86 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET451 ~wire 0 87 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET459 ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET467 ~wire 0 89 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET475 ~wire 0 90 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET483 ~wire 0 91 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET491 ~wire 0 92 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 93 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 94 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 95 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 99 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 114 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 133 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 169 (_entity .  Fub6)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
I 000054 55 1461          1083618748941 PWMTranslator
(_unit VERILOG 6.349C.6.256 (PWMTranslator 0 25 (PWMTranslator 0 25 ))
	(_version v32)
	(_time 1083618748894 2004.05.03 14:12:28)
	(_source (\./src/pwmtranslator.v\ VERILOG (\./src/pwmtranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083618748894)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_model . PWMTranslator 1 -1)

)
V 000043 55 8512          1083618755817 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083618755769 2004.05.03 14:12:35)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083618755769)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 34 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET409 ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET417 ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET425 ~wire 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET433 ~wire 0 86 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET451 ~wire 0 87 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET459 ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET467 ~wire 0 89 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET475 ~wire 0 90 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET483 ~wire 0 91 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET491 ~wire 0 92 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 93 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 94 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 95 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 99 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 114 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 133 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (NET425))
			((DRV0LOWr) (NET433))
			((DRV1HIGHr) (NET491))
			((DRV1LOWr) (NET451))
			((DRV2HIGHr) (NET459))
			((DRV2LOWr) (NET467))
			((DRV3HIGHr) (NET475))
			((DRV3LOWr) (NET483))
			((DRVCTLw) (NET417))
			((DRVSTATr) (NET409))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 169 (_entity .  PWMTranslator)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
V 000055 55 5243          1083619187222 EncoderControl
(_unit VERILOG 6.349C.6.256 (EncoderControl 0 25 (EncoderControl 0 25 ))
	(_version v32)
	(_time 1083619187144 2004.05.03 14:19:47)
	(_source (\./src/encodercontrol.v\ VERILOG (\./src/encodercontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083619187144)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~vector~0 0 27 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal bits ~vector~0 0 27 \4'd10\ (_entity -1 (_constant \4'd10\))))
		(_type (_internal ~vector~1 0 28 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal divisor ~vector~1 0 28 \4'd3\ (_entity -1 (_constant \4'd3\))))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAV ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Shift ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Start ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Eclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal SS ~reg 0 52 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 53 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal divider ~[3:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CEr ~reg 0 54 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BitCounter ~[3:0]reg~ 0 55 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Eclkr ~reg 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Stop ~wire 0 57 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal start ~wire 0 58 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DAVr ~reg 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Shiftr ~reg 0 60 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#62_0 (_architecture 0 0 62 (_process (_simple)
				(_target(13))
				(_sensitivity(6)(11))
			)))
			(#ASSIGN#63_1 (_architecture 1 0 63 (_process (_alias ((Eclk)(Eclkr)))(_simple)
				(_target(6))
				(_sensitivity(12))
			)))
			(#ASSIGN#64_2 (_architecture 2 0 64 (_process (_alias ((Shift)(Shiftr)))(_simple)
				(_target(3))
				(_sensitivity(16))
			)))
			(#ASSIGN#65_3 (_architecture 3 0 65 (_process (_simple)
				(_target(1))
				(_sensitivity(0)(15))
			)))
			(#ASSIGN#66_4 (_architecture 4 0 66 (_process (_alias ((start)(Start)(DRVCTLw)))(_simple)
				(_target(14))
				(_sensitivity(5)(4))
			)))
			(#ALWAYS#68_5 (_architecture 5 0 68 (_process 
				(_target(8)(10)(16)(15))
				(_read(7)(2)(13)(14)(8)(9)(12)(11)(6)(15))
			)))
			(#ALWAYS#95_6 (_architecture 6 0 95 (_process 
				(_target(9)(12)(11))
				(_read(7)(2)(8)(9)(10)(12)(16)(11))
			)))
			(#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . EncoderControl 8 -1)

)
V 000050 55 9101          1083619197988 EncReader
(_unit VERILOG 6.349C.6.256 (EncReader 0 32 (EncReader 0 32 ))
	(_version v32)
	(_time 1083619197925 2004.05.03 14:19:57)
	(_source (\./compile/encreader.v\ VERILOG (\./compile/encreader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083619197925)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal ENCint ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET266 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET282 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 107 (_entity .  EncoderControl)
		(_port
			((DAV) (outDATA(0)))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Eclk) (NET266))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((Shift) (NET282))
			((Start) (inDATA(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 121 (_entity .  EncShift)
		(_port
			((Data) (data0))
			((Eclkin) (NET266))
			((Eclkout) (SSclk0))
			((LSByte) (DRV0LOWr))
			((MSByte) (DRV0HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable0))
			((PWRflag) (Rflg0))
			((PWRflg) (outDATA(4)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(4)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 142 (_entity .  EncShift)
		(_port
			((Data) (data1))
			((Eclkin) (NET266))
			((Eclkout) (SSclk1))
			((LSByte) (DRV1LOWr))
			((MSByte) (DRV1HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable1))
			((PWRflag) (Rflg1))
			((PWRflg) (outDATA(5)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(5)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 163 (_entity .  EncShift)
		(_port
			((Data) (data2))
			((Eclkin) (NET266))
			((Eclkout) (SSclk2))
			((LSByte) (DRV2LOWr))
			((MSByte) (DRV2HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable2))
			((PWRflag) (Rflg2))
			((PWRflg) (outDATA(6)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(6)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 184 (_entity .  EncShift)
		(_port
			((Data) (data3))
			((Eclkin) (NET266))
			((Eclkout) (SSclk3))
			((LSByte) (DRV3LOWr))
			((MSByte) (DRV3HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable3))
			((PWRflag) (Rflg3))
			((PWRflg) (outDATA(7)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(7)))
			((outDATA) (inDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 205 (_entity .  ENCinterrupt)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (ENCint))
			((Mclk) (Mclk))
			((PWRflg0) (outDATA(4)))
			((PWRflg1) (outDATA(5)))
			((PWRflg2) (outDATA(6)))
			((PWRflg3) (outDATA(7)))
			((PWRflgIEw) (inDATA(1)))
			((Reset) (Reset))
			((outDATA) (outDATA(d_3_1)))
		)
		(_strength strong0 strong1)
	)
	(_model . EncReader 1 -1)

)
I 000054 55 11318         1083677562380 PWMTranslator
(_unit VERILOG 6.349C.6.256 (PWMTranslator 0 25 (PWMTranslator 0 25 ))
	(_version v32)
	(_time 1083677561833 2004.05.04 06:32:41)
	(_source (\./src/pwmtranslator.v\ VERILOG (\./src/pwmtranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 22))
	(_entity
		(_time 1083677561833)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWMsource ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Motor0_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor0_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor0_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor0_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVMTRCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M31 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M30 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M21 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M20 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M11 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M10 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M01 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M00 ~reg 0 80 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.PWM ~reg 0 83 (_subprogram A_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.M1 ~reg 0 84 (_subprogram A_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.M0 ~reg 0 85 (_subprogram A_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.A_HIN ~reg 0 0 (_subprogram A_HIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.PWM ~reg 0 90 (_subprogram B_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.M1 ~reg 0 91 (_subprogram B_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.M0 ~reg 0 92 (_subprogram B_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.B_HIN ~reg 0 0 (_subprogram B_HIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.PWM ~reg 0 97 (_subprogram A_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.M1 ~reg 0 98 (_subprogram A_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.M0 ~reg 0 99 (_subprogram A_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.A_LIN ~reg 0 0 (_subprogram A_LIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.PWM ~reg 0 104 (_subprogram B_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.M1 ~reg 0 105 (_subprogram B_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.M0 ~reg 0 106 (_subprogram B_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.B_LIN ~reg 0 0 (_subprogram B_LIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal A_HIN 17 0 82 (_architecture (_function)(_target(32))
				(_read(29)(30)(31))
			))
			(_internal B_HIN 18 0 89 (_architecture (_function)(_target(36))
				(_read(33)(34)(35))
			))
			(_internal A_LIN 19 0 96 (_architecture (_function)(_target(40))
				(_read(38)(39)(37))
			))
			(_internal B_LIN 20 0 103 (_architecture (_function)(_target(44))
				(_read(42)(43)(41))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#110_0 (_architecture 0 0 110 (_process (_simple)
				(_target(3))
				(_sensitivity(1)(27)(28))
				(_call(0))
			)))
			(#ASSIGN#111_1 (_architecture 1 0 111 (_process (_simple)
				(_target(4))
				(_sensitivity(1)(27)(28))
				(_call(1))
			)))
			(#ASSIGN#112_2 (_architecture 2 0 112 (_process (_simple)
				(_target(11))
				(_sensitivity(1)(27)(28))
				(_call(2))
			)))
			(#ASSIGN#113_3 (_architecture 3 0 113 (_process (_simple)
				(_target(13))
				(_sensitivity(1)(27)(28))
				(_call(3))
			)))
			(#ASSIGN#115_4 (_architecture 4 0 115 (_process (_simple)
				(_target(5))
				(_sensitivity(1)(25)(26))
				(_call(0))
			)))
			(#ASSIGN#116_5 (_architecture 5 0 116 (_process (_simple)
				(_target(7))
				(_sensitivity(1)(25)(26))
				(_call(1))
			)))
			(#ASSIGN#117_6 (_architecture 6 0 117 (_process (_simple)
				(_target(14))
				(_sensitivity(1)(25)(26))
				(_call(2))
			)))
			(#ASSIGN#118_7 (_architecture 7 0 118 (_process (_simple)
				(_target(15))
				(_sensitivity(1)(25)(26))
				(_call(3))
			)))
			(#ASSIGN#120_8 (_architecture 8 0 120 (_process (_simple)
				(_target(8))
				(_sensitivity(1)(23)(24))
				(_call(0))
			)))
			(#ASSIGN#121_9 (_architecture 9 0 121 (_process (_simple)
				(_target(9))
				(_sensitivity(1)(23)(24))
				(_call(1))
			)))
			(#ASSIGN#122_10 (_architecture 10 0 122 (_process (_simple)
				(_target(16))
				(_sensitivity(1)(23)(24))
				(_call(2))
			)))
			(#ASSIGN#123_11 (_architecture 11 0 123 (_process (_simple)
				(_target(17))
				(_sensitivity(1)(23)(24))
				(_call(3))
			)))
			(#ASSIGN#125_12 (_architecture 12 0 125 (_process (_simple)
				(_target(10))
				(_sensitivity(1)(21)(22))
				(_call(0))
			)))
			(#ASSIGN#126_13 (_architecture 13 0 126 (_process (_simple)
				(_target(12))
				(_sensitivity(1)(21)(22))
				(_call(1))
			)))
			(#ASSIGN#127_14 (_architecture 14 0 127 (_process (_simple)
				(_target(18))
				(_sensitivity(1)(21)(22))
				(_call(2))
			)))
			(#ASSIGN#128_15 (_architecture 15 0 128 (_process (_simple)
				(_target(19))
				(_sensitivity(1)(21)(22))
				(_call(3))
			)))
			(#ALWAYS#130_16 (_architecture 16 0 130 (_process 
				(_target(21)(22)(23)(24)(25)(26)(27)(28))
				(_read(2)(0)(20)(6)(21)(22)(23)(24)(25)(26)(27)(28))
			)))
			(#INTERNAL#0_21 (_internal 21 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit A_HIN function 0 82
		)
		(_unit B_HIN function 0 89
		)
		(_unit A_LIN function 0 96
		)
		(_unit B_LIN function 0 103
		)
	)
	(_model . PWMTranslator 22 -1)

)
I 000054 55 6332          1083680390473 AddressDecode
(_unit VERILOG 6.349C.6.256 (AddressDecode 0 25 (AddressDecode 0 25 ))
	(_version v32)
	(_time 1083680390255 2004.05.04 07:19:50)
	(_source (\./src/addressdecode.v\ VERILOG (\./src/addressdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 13))
	(_entity
		(_time 1083680390255)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV2HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVMTRCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 70 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 70 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 71 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 72 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 72 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 73 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 11 0 69 (_architecture (_function)(_target(19))
				(_read(18)(16)(17)(11)(15))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#81_0 (_architecture 0 0 81 (_process (_simple)
				(_target(10))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#84_1 (_architecture 1 0 84 (_process (_simple)
				(_target(6))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#87_2 (_architecture 2 0 87 (_process (_simple)
				(_target(12))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#90_3 (_architecture 3 0 90 (_process (_simple)
				(_target(1))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#93_4 (_architecture 4 0 93 (_process (_simple)
				(_target(13))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#96_5 (_architecture 5 0 96 (_process (_simple)
				(_target(3))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#99_6 (_architecture 6 0 99 (_process (_simple)
				(_target(0))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#102_7 (_architecture 7 0 102 (_process (_simple)
				(_target(4))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#105_8 (_architecture 8 0 105 (_process (_simple)
				(_target(2))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#108_9 (_architecture 9 0 108 (_process (_simple)
				(_target(5))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#ASSIGN#111_10 (_architecture 10 0 111 (_process (_simple)
				(_target(8))
				(_sensitivity(11)(7)(9))
				(_call(0))
			)))
			(#INTERNAL#0_12 (_internal 12 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 69
		)
	)
	(_model . AddressDecode 13 -1)

)
V 000054 55 12215         1083680932348 PWMTranslator
(_unit VERILOG 6.349C.6.256 (PWMTranslator 0 25 (PWMTranslator 0 25 ))
	(_version v32)
	(_time 1083680932255 2004.05.04 07:28:52)
	(_source (\./src/pwmtranslator.v\ VERILOG (\./src/pwmtranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 24))
	(_entity
		(_time 1083680932255)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWMsource ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal MTRPWR ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor0_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor0_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor0_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor0_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRPWR_n ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVMTRCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal MTRPWRr ~reg 0 81 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M31 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M30 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M21 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M20 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M11 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M10 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M01 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal M00 ~reg 0 88 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.PWM ~reg 0 91 (_subprogram A_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.M1 ~reg 0 92 (_subprogram A_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.M0 ~reg 0 93 (_subprogram A_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_HIN.A_HIN ~reg 0 0 (_subprogram A_HIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.PWM ~reg 0 98 (_subprogram B_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.M1 ~reg 0 99 (_subprogram B_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.M0 ~reg 0 100 (_subprogram B_HIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_HIN.B_HIN ~reg 0 0 (_subprogram B_HIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.PWM ~reg 0 105 (_subprogram A_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.M1 ~reg 0 106 (_subprogram A_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.M0 ~reg 0 107 (_subprogram A_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal A_LIN.A_LIN ~reg 0 0 (_subprogram A_LIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.PWM ~reg 0 112 (_subprogram B_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.M1 ~reg 0 113 (_subprogram B_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.M0 ~reg 0 114 (_subprogram B_LIN (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal B_LIN.B_LIN ~reg 0 0 (_subprogram B_LIN (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal A_HIN 19 0 90 (_architecture (_function)(_target(36))
				(_read(33)(34)(35))
			))
			(_internal B_HIN 20 0 97 (_architecture (_function)(_target(40))
				(_read(37)(38)(39))
			))
			(_internal A_LIN 21 0 104 (_architecture (_function)(_target(44))
				(_read(42)(43)(41))
			))
			(_internal B_LIN 22 0 111 (_architecture (_function)(_target(48))
				(_read(46)(47)(45))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#118_0 (_architecture 0 0 118 (_process (_simple)
				(_target(5))
				(_sensitivity(1)(31)(32))
				(_call(0))
			)))
			(#ASSIGN#119_1 (_architecture 1 0 119 (_process (_simple)
				(_target(6))
				(_sensitivity(1)(31)(32))
				(_call(1))
			)))
			(#ASSIGN#120_2 (_architecture 2 0 120 (_process (_simple)
				(_target(13))
				(_sensitivity(1)(31)(32))
				(_call(2))
			)))
			(#ASSIGN#121_3 (_architecture 3 0 121 (_process (_simple)
				(_target(15))
				(_sensitivity(1)(31)(32))
				(_call(3))
			)))
			(#ASSIGN#123_4 (_architecture 4 0 123 (_process (_simple)
				(_target(7))
				(_sensitivity(1)(29)(30))
				(_call(0))
			)))
			(#ASSIGN#124_5 (_architecture 5 0 124 (_process (_simple)
				(_target(9))
				(_sensitivity(1)(29)(30))
				(_call(1))
			)))
			(#ASSIGN#125_6 (_architecture 6 0 125 (_process (_simple)
				(_target(16))
				(_sensitivity(1)(29)(30))
				(_call(2))
			)))
			(#ASSIGN#126_7 (_architecture 7 0 126 (_process (_simple)
				(_target(17))
				(_sensitivity(1)(29)(30))
				(_call(3))
			)))
			(#ASSIGN#128_8 (_architecture 8 0 128 (_process (_simple)
				(_target(10))
				(_sensitivity(1)(27)(28))
				(_call(0))
			)))
			(#ASSIGN#129_9 (_architecture 9 0 129 (_process (_simple)
				(_target(11))
				(_sensitivity(1)(27)(28))
				(_call(1))
			)))
			(#ASSIGN#130_10 (_architecture 10 0 130 (_process (_simple)
				(_target(18))
				(_sensitivity(1)(27)(28))
				(_call(2))
			)))
			(#ASSIGN#131_11 (_architecture 11 0 131 (_process (_simple)
				(_target(19))
				(_sensitivity(1)(27)(28))
				(_call(3))
			)))
			(#ASSIGN#133_12 (_architecture 12 0 133 (_process (_simple)
				(_target(12))
				(_sensitivity(1)(25)(26))
				(_call(0))
			)))
			(#ASSIGN#134_13 (_architecture 13 0 134 (_process (_simple)
				(_target(14))
				(_sensitivity(1)(25)(26))
				(_call(1))
			)))
			(#ASSIGN#135_14 (_architecture 14 0 135 (_process (_simple)
				(_target(20))
				(_sensitivity(1)(25)(26))
				(_call(2))
			)))
			(#ASSIGN#136_15 (_architecture 15 0 136 (_process (_simple)
				(_target(21))
				(_sensitivity(1)(25)(26))
				(_call(3))
			)))
			(#ASSIGN#138_16 (_architecture 16 0 138 (_process (_alias ((MTRPWR)(MTRPWRr)))(_simple)
				(_target(4))
				(_sensitivity(24))
			)))
			(#ASSIGN#139_17 (_architecture 17 0 139 (_process (_alias ((MTRPWR_n)(MTRPWRr)))(_simple)
				(_target(22))
				(_sensitivity(24))
			)))
			(#ALWAYS#141_18 (_architecture 18 0 141 (_process 
				(_target(25)(26)(27)(28)(29)(30)(31)(32)(24))
				(_read(3)(0)(23)(8)(25)(26)(27)(28)(29)(30)(31)(32)(2)(8(2))(24))
			)))
			(#INTERNAL#0_23 (_internal 23 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit A_HIN function 0 90
		)
		(_unit B_HIN function 0 97
		)
		(_unit A_LIN function 0 104
		)
		(_unit B_LIN function 0 111
		)
	)
	(_model . PWMTranslator 24 -1)

)
V 000043 55 12884         1083680991801 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083680991739 2004.05.04 07:29:51)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083680991739)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 36 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 123 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 124 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 125 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 126 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 127 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 128 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 129 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 130 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 131 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 132 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 133 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 134 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 135 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 136 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 140 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 155 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 175 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 211 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
I 000054 55 6630          1083682460083 AddressDecode
(_unit VERILOG 6.349C.6.256 (AddressDecode 0 25 (AddressDecode 0 25 ))
	(_version v32)
	(_time 1083682460005 2004.05.04 07:54:20)
	(_source (\./src/addressdecode.v\ VERILOG (\./src/addressdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 14))
	(_entity
		(_time 1083682460005)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV2HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALVEw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVMTRCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 72 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 72 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 73 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 74 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 74 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 75 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 12 0 71 (_architecture (_function)(_target(20))
				(_read(19)(17)(18)(12)(16))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#83_0 (_architecture 0 0 83 (_process (_simple)
				(_target(11))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#86_1 (_architecture 1 0 86 (_process (_simple)
				(_target(7))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#89_2 (_architecture 2 0 89 (_process (_simple)
				(_target(13))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#92_3 (_architecture 3 0 92 (_process (_simple)
				(_target(1))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#95_4 (_architecture 4 0 95 (_process (_simple)
				(_target(14))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#98_5 (_architecture 5 0 98 (_process (_simple)
				(_target(4))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#101_6 (_architecture 6 0 101 (_process (_simple)
				(_target(0))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#104_7 (_architecture 7 0 104 (_process (_simple)
				(_target(5))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#107_8 (_architecture 8 0 107 (_process (_simple)
				(_target(3))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#110_9 (_architecture 9 0 110 (_process (_simple)
				(_target(6))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#113_10 (_architecture 10 0 113 (_process (_simple)
				(_target(9))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#ASSIGN#116_11 (_architecture 11 0 116 (_process (_simple)
				(_target(2))
				(_sensitivity(12)(8)(10))
				(_call(0))
			)))
			(#INTERNAL#0_13 (_internal 13 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 71
		)
	)
	(_model . AddressDecode 14 -1)

)
I 000056 55 8768          1083682727365 ValveTranslator
(_unit VERILOG 6.349C.6.256 (ValveTranslator 0 25 (ValveTranslator 0 25 ))
	(_version v32)
	(_time 1083682727317 2004.05.04 07:58:47)
	(_source (\./src/valvetranslator.v\ VERILOG (\./src/valvetranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1083682727317)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DRVVALVEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAH1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAH2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAH3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAH4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAH5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAH6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAH7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBH7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VAL7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal VBL7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[1:0]reg~ 0 105 (_array ~reg ((_downto (i 1) (i 0))))))
		(_signal (_internal V7 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V6 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V5 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V4 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V3 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V2 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V1 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V0 ~[1:0]reg~ 0 105 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#107_0 (_architecture 0 0 107 (_process 
				(_target(36)(37)(38)(39)(40)(41)(42)(43))
				(_read(35)(1))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . ValveTranslator 2 -1)

)
I 000054 55 6918          1083682883318 AddressDecode
(_unit VERILOG 6.349C.6.256 (AddressDecode 0 25 (AddressDecode 0 25 ))
	(_version v32)
	(_time 1083682883239 2004.05.04 08:01:23)
	(_source (\./src/addressdecode.v\ VERILOG (\./src/addressdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1083682883239)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV0w ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV1w ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVMTRCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 74 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 74 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 75 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 76 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 76 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 77 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 13 0 73 (_architecture (_function)(_target(21))
				(_read(20)(18)(19)(15)(17))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#85_0 (_architecture 0 0 85 (_process (_simple)
				(_target(14))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#88_1 (_architecture 1 0 88 (_process (_simple)
				(_target(4))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#91_2 (_architecture 2 0 91 (_process (_simple)
				(_target(8))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#94_3 (_architecture 3 0 94 (_process (_simple)
				(_target(0))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#97_4 (_architecture 4 0 97 (_process (_simple)
				(_target(9))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#100_5 (_architecture 5 0 100 (_process (_simple)
				(_target(1))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#103_6 (_architecture 6 0 103 (_process (_simple)
				(_target(10))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#106_7 (_architecture 7 0 106 (_process (_simple)
				(_target(2))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#109_8 (_architecture 8 0 109 (_process (_simple)
				(_target(11))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#112_9 (_architecture 9 0 112 (_process (_simple)
				(_target(3))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#115_10 (_architecture 10 0 115 (_process (_simple)
				(_target(13))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#118_11 (_architecture 11 0 118 (_process (_simple)
				(_target(6))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#121_12 (_architecture 12 0 121 (_process (_simple)
				(_target(7))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 73
		)
	)
	(_model . AddressDecode 15 -1)

)
I 000056 55 13247         1083683574881 ValveTranslator
(_unit VERILOG 6.349C.6.256 (ValveTranslator 0 25 (ValveTranslator 0 25 ))
	(_version v32)
	(_time 1083683574786 2004.05.04 08:12:54)
	(_source (\./src/valvetranslator.v\ VERILOG (\./src/valvetranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 34))
	(_entity
		(_time 1083683574786)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV0w ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal DRVVALV1w ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[1:0]reg~ 0 107 (_array ~reg ((_downto (i 1) (i 0))))))
		(_signal (_internal V7 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V6 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V5 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V4 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V3 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V2 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V1 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V0 ~[1:0]reg~ 0 107 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#109_0 (_architecture 0 0 109 (_process (_alias ((VAH0)(V0(0))(V0(1))))(_simple)
				(_target(2))
				(_sensitivity(44(0))(44(1)))
			)))
			(#ASSIGN#110_1 (_architecture 1 0 110 (_process (_alias ((VBL0)(V0(0))(V0(1))))(_simple)
				(_target(15))
				(_sensitivity(44(0))(44(1)))
			)))
			(#ASSIGN#111_2 (_architecture 2 0 111 (_process (_alias ((VBH0)(V0(0))(V0(1))))(_simple)
				(_target(3))
				(_sensitivity(44(0))(44(1)))
			)))
			(#ASSIGN#112_3 (_architecture 3 0 112 (_process (_alias ((VAL0)(V0(0))(V0(1))))(_simple)
				(_target(12))
				(_sensitivity(44(0))(44(1)))
			)))
			(#ASSIGN#114_4 (_architecture 4 0 114 (_process (_alias ((VAH1)(V1(0))(V1(1))))(_simple)
				(_target(4))
				(_sensitivity(43(0))(43(1)))
			)))
			(#ASSIGN#115_5 (_architecture 5 0 115 (_process (_alias ((VBL1)(V1(0))(V1(1))))(_simple)
				(_target(19))
				(_sensitivity(43(0))(43(1)))
			)))
			(#ASSIGN#116_6 (_architecture 6 0 116 (_process (_alias ((VBH1)(V1(0))(V1(1))))(_simple)
				(_target(6))
				(_sensitivity(43(0))(43(1)))
			)))
			(#ASSIGN#117_7 (_architecture 7 0 117 (_process (_alias ((VAL1)(V1(0))(V1(1))))(_simple)
				(_target(16))
				(_sensitivity(43(0))(43(1)))
			)))
			(#ASSIGN#119_8 (_architecture 8 0 119 (_process (_alias ((VAH2)(V2(0))(V2(1))))(_simple)
				(_target(7))
				(_sensitivity(42(0))(42(1)))
			)))
			(#ASSIGN#120_9 (_architecture 9 0 120 (_process (_alias ((VBL2)(V2(0))(V2(1))))(_simple)
				(_target(24))
				(_sensitivity(42(0))(42(1)))
			)))
			(#ASSIGN#121_10 (_architecture 10 0 121 (_process (_alias ((VBH2)(V2(0))(V2(1))))(_simple)
				(_target(9))
				(_sensitivity(42(0))(42(1)))
			)))
			(#ASSIGN#122_11 (_architecture 11 0 122 (_process (_alias ((VAL2)(V2(0))(V2(1))))(_simple)
				(_target(20))
				(_sensitivity(42(0))(42(1)))
			)))
			(#ASSIGN#124_12 (_architecture 12 0 124 (_process (_alias ((VAH3)(V3(0))(V3(1))))(_simple)
				(_target(8))
				(_sensitivity(41(0))(41(1)))
			)))
			(#ASSIGN#125_13 (_architecture 13 0 125 (_process (_alias ((VBL3)(V3(0))(V3(1))))(_simple)
				(_target(27))
				(_sensitivity(41(0))(41(1)))
			)))
			(#ASSIGN#126_14 (_architecture 14 0 126 (_process (_alias ((VBH3)(V3(0))(V3(1))))(_simple)
				(_target(11))
				(_sensitivity(41(0))(41(1)))
			)))
			(#ASSIGN#127_15 (_architecture 15 0 127 (_process (_alias ((VAL3)(V3(0))(V3(1))))(_simple)
				(_target(23))
				(_sensitivity(41(0))(41(1)))
			)))
			(#ASSIGN#129_16 (_architecture 16 0 129 (_process (_alias ((VAH4)(V4(0))(V4(1))))(_simple)
				(_target(10))
				(_sensitivity(40(0))(40(1)))
			)))
			(#ASSIGN#130_17 (_architecture 17 0 130 (_process (_alias ((VBL4)(V4(0))(V4(1))))(_simple)
				(_target(29))
				(_sensitivity(40(0))(40(1)))
			)))
			(#ASSIGN#131_18 (_architecture 18 0 131 (_process (_alias ((VBH4)(V4(0))(V4(1))))(_simple)
				(_target(14))
				(_sensitivity(40(0))(40(1)))
			)))
			(#ASSIGN#132_19 (_architecture 19 0 132 (_process (_alias ((VAL4)(V4(0))(V4(1))))(_simple)
				(_target(26))
				(_sensitivity(40(0))(40(1)))
			)))
			(#ASSIGN#134_20 (_architecture 20 0 134 (_process (_alias ((VAH5)(V5(0))(V5(1))))(_simple)
				(_target(13))
				(_sensitivity(39(0))(39(1)))
			)))
			(#ASSIGN#135_21 (_architecture 21 0 135 (_process (_alias ((VBL5)(V5(0))(V5(1))))(_simple)
				(_target(31))
				(_sensitivity(39(0))(39(1)))
			)))
			(#ASSIGN#136_22 (_architecture 22 0 136 (_process (_alias ((VBH5)(V5(0))(V5(1))))(_simple)
				(_target(18))
				(_sensitivity(39(0))(39(1)))
			)))
			(#ASSIGN#137_23 (_architecture 23 0 137 (_process (_alias ((VAL5)(V5(0))(V5(1))))(_simple)
				(_target(28))
				(_sensitivity(39(0))(39(1)))
			)))
			(#ASSIGN#139_24 (_architecture 24 0 139 (_process (_alias ((VAH6)(V6(0))(V6(1))))(_simple)
				(_target(17))
				(_sensitivity(38(0))(38(1)))
			)))
			(#ASSIGN#140_25 (_architecture 25 0 140 (_process (_alias ((VBL6)(V6(0))(V6(1))))(_simple)
				(_target(33))
				(_sensitivity(38(0))(38(1)))
			)))
			(#ASSIGN#141_26 (_architecture 26 0 141 (_process (_alias ((VBH6)(V6(0))(V6(1))))(_simple)
				(_target(22))
				(_sensitivity(38(0))(38(1)))
			)))
			(#ASSIGN#142_27 (_architecture 27 0 142 (_process (_alias ((VAL6)(V6(0))(V6(1))))(_simple)
				(_target(30))
				(_sensitivity(38(0))(38(1)))
			)))
			(#ASSIGN#144_28 (_architecture 28 0 144 (_process (_alias ((VAH7)(V7(0))(V7(1))))(_simple)
				(_target(21))
				(_sensitivity(37(0))(37(1)))
			)))
			(#ASSIGN#145_29 (_architecture 29 0 145 (_process (_alias ((VBL7)(V7(0))(V7(1))))(_simple)
				(_target(34))
				(_sensitivity(37(0))(37(1)))
			)))
			(#ASSIGN#146_30 (_architecture 30 0 146 (_process (_alias ((VBH7)(V7(0))(V7(1))))(_simple)
				(_target(25))
				(_sensitivity(37(0))(37(1)))
			)))
			(#ASSIGN#147_31 (_architecture 31 0 147 (_process (_alias ((VAL7)(V7(0))(V7(1))))(_simple)
				(_target(32))
				(_sensitivity(37(0))(37(1)))
			)))
			(#ALWAYS#149_32 (_architecture 32 0 149 (_process 
				(_target(37)(38)(39)(40)(41)(42)(43)(44))
				(_read(35)(0)(1)(5)(36)(37)(38)(39)(40)(41)(42)(43)(44))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . ValveTranslator 34 -1)

)
V 000043 55 19500         1083683826380 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083683826317 2004.05.04 08:17:06)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083683826317)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 209 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 224 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 246 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ENCint) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 282 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 312 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
I 000050 55 4827          1083684574052 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1083684573989 2004.05.04 08:29:33)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083684573989)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 67 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 69 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 71 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#80_0 (_architecture 0 0 80 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#83_1 (_architecture 1 0 83 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(8)(5)(15))
			)))
			(#ASSIGN#84_2 (_architecture 2 0 84 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#85_3 (_architecture 3 0 85 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(7))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#92_4 (_architecture 4 0 92 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#93_5 (_architecture 5 0 93 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#95_6 (_architecture 6 0 95 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
V 000043 55 19655         1083684877973 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083684877911 2004.05.04 08:34:37)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083684877911)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 211 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 226 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 248 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 285 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 315 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
V 000050 55 4829          1083684990756 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1083684990692 2004.05.04 08:36:30)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1083684990692)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASleading ~wire 0 56 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 67 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 69 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 71 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#80_0 (_architecture 0 0 80 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(8))
				(_sensitivity(10))
			)))
			(#ASSIGN#83_1 (_architecture 1 0 83 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(7)(5)(15))
			)))
			(#ASSIGN#84_2 (_architecture 2 0 84 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#85_3 (_architecture 3 0 85 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(9))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#92_4 (_architecture 4 0 92 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#93_5 (_architecture 5 0 93 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#95_6 (_architecture 6 0 95 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(7)(5)(2)(9)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
V 000043 55 19630         1083685000912 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083685000848 2004.05.04 08:36:40)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083685000848)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 211 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 226 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 248 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 285 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 315 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
I 000054 55 6918          1083685581412 AddressDecode
(_unit VERILOG 6.349C.6.256 (AddressDecode 0 25 (AddressDecode 0 25 ))
	(_version v32)
	(_time 1083685581333 2004.05.04 08:46:21)
	(_source (\./src/addressdecode.v\ VERILOG (\./src/addressdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1083685581333)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV0w ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV1w ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVMTRCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 74 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 74 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 75 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 76 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 76 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 77 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 13 0 73 (_architecture (_function)(_target(21))
				(_read(20)(18)(19)(15)(17))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#85_0 (_architecture 0 0 85 (_process (_simple)
				(_target(14))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#88_1 (_architecture 1 0 88 (_process (_simple)
				(_target(4))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#91_2 (_architecture 2 0 91 (_process (_simple)
				(_target(8))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#94_3 (_architecture 3 0 94 (_process (_simple)
				(_target(0))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#97_4 (_architecture 4 0 97 (_process (_simple)
				(_target(9))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#100_5 (_architecture 5 0 100 (_process (_simple)
				(_target(1))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#103_6 (_architecture 6 0 103 (_process (_simple)
				(_target(10))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#106_7 (_architecture 7 0 106 (_process (_simple)
				(_target(2))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#109_8 (_architecture 8 0 109 (_process (_simple)
				(_target(11))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#112_9 (_architecture 9 0 112 (_process (_simple)
				(_target(3))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#115_10 (_architecture 10 0 115 (_process (_simple)
				(_target(13))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#118_11 (_architecture 11 0 118 (_process (_simple)
				(_target(6))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#ASSIGN#121_12 (_architecture 12 0 121 (_process (_simple)
				(_target(7))
				(_sensitivity(15)(12)(5))
				(_call(0))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 73
		)
	)
	(_model . AddressDecode 15 -1)

)
V 000043 55 19630         1083688868724 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083688868676 2004.05.04 09:41:08)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083688868676)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 211 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 226 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 248 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 285 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 315 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
V 000050 55 9133          1083689317161 EncReader
(_unit VERILOG 6.349C.6.256 (EncReader 0 32 (EncReader 0 32 ))
	(_version v32)
	(_time 1083689317098 2004.05.04 09:48:37)
	(_source (\./compile/encreader.v\ VERILOG (\./compile/encreader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083689317098)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal ENCint ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET266 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET282 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 107 (_entity .  EncoderControl)
		(_port
			((DAV) (outDATA(0)))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Eclk) (NET266))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((Shift) (NET282))
			((Start) (inDATA(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 121 (_entity .  EncShift)
		(_port
			((Data) (data0))
			((Eclkin) (NET266))
			((Eclkout) (SSclk0))
			((LSByte) (DRV0LOWr))
			((MSByte) (DRV0HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable0))
			((PWRflag) (Rflg0))
			((PWRflg) (outDATA(4)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(4)))
			((outDATA) (outDATA(d_3_1)))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 142 (_entity .  EncShift)
		(_port
			((Data) (data1))
			((Eclkin) (NET266))
			((Eclkout) (SSclk1))
			((LSByte) (DRV1LOWr))
			((MSByte) (DRV1HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable1))
			((PWRflag) (Rflg1))
			((PWRflg) (outDATA(5)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(5)))
			((outDATA) (outDATA(d_3_1)))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 163 (_entity .  EncShift)
		(_port
			((Data) (data2))
			((Eclkin) (NET266))
			((Eclkout) (SSclk2))
			((LSByte) (DRV2LOWr))
			((MSByte) (DRV2HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable2))
			((PWRflag) (Rflg2))
			((PWRflg) (outDATA(6)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(6)))
			((outDATA) (outDATA(d_3_1)))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 184 (_entity .  EncShift)
		(_port
			((Data) (data3))
			((Eclkin) (NET266))
			((Eclkout) (SSclk3))
			((LSByte) (DRV3LOWr))
			((MSByte) (DRV3HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable3))
			((PWRflag) (Rflg3))
			((PWRflg) (outDATA(7)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(7)))
			((outDATA) (outDATA(d_3_1)))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 205 (_entity .  ENCinterrupt)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (ENCint))
			((Mclk) (Mclk))
			((PWRflg0) (outDATA(4)))
			((PWRflg1) (outDATA(5)))
			((PWRflg2) (outDATA(6)))
			((PWRflg3) (outDATA(7)))
			((PWRflgIEw) (inDATA(1)))
			((Reset) (Reset))
			((outDATA) (outDATA(d_3_1)))
		)
		(_strength strong0 strong1)
	)
	(_model . EncReader 1 -1)

)
V 000050 55 9112          1083689436912 EncReader
(_unit VERILOG 6.349C.6.256 (EncReader 0 32 (EncReader 0 32 ))
	(_version v32)
	(_time 1083689436864 2004.05.04 09:50:36)
	(_source (\./compile/encreader.v\ VERILOG (\./compile/encreader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083689436864)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal ENCint ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET266 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET282 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 107 (_entity .  EncoderControl)
		(_port
			((DAV) (outDATA(0)))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Eclk) (NET266))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((Shift) (NET282))
			((Start) (inDATA(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 121 (_entity .  EncShift)
		(_port
			((Data) (data0))
			((Eclkin) (NET266))
			((Eclkout) (SSclk0))
			((LSByte) (DRV0LOWr))
			((MSByte) (DRV0HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable0))
			((PWRflag) (Rflg0))
			((PWRflg) (outDATA(4)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(4)))
			((outDATA) (outDATA(d_3_1)))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 142 (_entity .  EncShift)
		(_port
			((Data) (data1))
			((Eclkin) (NET266))
			((Eclkout) (SSclk1))
			((LSByte) (DRV1LOWr))
			((MSByte) (DRV1HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable1))
			((PWRflag) (Rflg1))
			((PWRflg) (outDATA(5)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(5)))
			((outDATA) (outDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 163 (_entity .  EncShift)
		(_port
			((Data) (data2))
			((Eclkin) (NET266))
			((Eclkout) (SSclk2))
			((LSByte) (DRV2LOWr))
			((MSByte) (DRV2HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable2))
			((PWRflag) (Rflg2))
			((PWRflg) (outDATA(6)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(6)))
			((outDATA) (outDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 184 (_entity .  EncShift)
		(_port
			((Data) (data3))
			((Eclkin) (NET266))
			((Eclkout) (SSclk3))
			((LSByte) (DRV3LOWr))
			((MSByte) (DRV3HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable3))
			((PWRflag) (Rflg3))
			((PWRflg) (outDATA(7)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(7)))
			((outDATA) (outDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 205 (_entity .  ENCinterrupt)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (ENCint))
			((Mclk) (Mclk))
			((PWRflg0) (outDATA(4)))
			((PWRflg1) (outDATA(5)))
			((PWRflg2) (outDATA(6)))
			((PWRflg3) (outDATA(7)))
			((PWRflgIEw) (inDATA(1)))
			((Reset) (Reset))
			((outDATA) (outDATA(d_3_1)))
		)
		(_strength strong0 strong1)
	)
	(_model . EncReader 1 -1)

)
V 000050 55 9105          1083689568161 EncReader
(_unit VERILOG 6.349C.6.256 (EncReader 0 32 (EncReader 0 32 ))
	(_version v32)
	(_time 1083689568098 2004.05.04 09:52:48)
	(_source (\./compile/encreader.v\ VERILOG (\./compile/encreader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083689568098)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV0LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Rflg3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data3 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal ENCint ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Renable3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk2 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk3 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET266 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET282 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 107 (_entity .  EncoderControl)
		(_port
			((DAV) (outDATA(0)))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((Eclk) (NET266))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((Shift) (NET282))
			((Start) (inDATA(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 121 (_entity .  EncShift)
		(_port
			((Data) (data0))
			((Eclkin) (NET266))
			((Eclkout) (SSclk0))
			((LSByte) (DRV0LOWr))
			((MSByte) (DRV0HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable0))
			((PWRflag) (Rflg0))
			((PWRflg) (outDATA(4)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(4)))
			((outDATA) (outDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 142 (_entity .  EncShift)
		(_port
			((Data) (data1))
			((Eclkin) (NET266))
			((Eclkout) (SSclk1))
			((LSByte) (DRV1LOWr))
			((MSByte) (DRV1HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable1))
			((PWRflag) (Rflg1))
			((PWRflg) (outDATA(5)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(5)))
			((outDATA) (outDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 163 (_entity .  EncShift)
		(_port
			((Data) (data2))
			((Eclkin) (NET266))
			((Eclkout) (SSclk2))
			((LSByte) (DRV2LOWr))
			((MSByte) (DRV2HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable2))
			((PWRflag) (Rflg2))
			((PWRflg) (outDATA(6)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(6)))
			((outDATA) (outDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 184 (_entity .  EncShift)
		(_port
			((Data) (data3))
			((Eclkin) (NET266))
			((Eclkout) (SSclk3))
			((LSByte) (DRV3LOWr))
			((MSByte) (DRV3HIGHr))
			((Mclk) (Mclk))
			((PWRenc) (Renable3))
			((PWRflag) (Rflg3))
			((PWRflg) (outDATA(7)))
			((PWRflgr) (DRVSTATr))
			((Reset) (Reset))
			((Shift) (NET282))
			((State) (inDATA(7)))
			((outDATA) (outDATA))
			((setPWR) (DRVCTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 205 (_entity .  ENCinterrupt)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (ENCint))
			((Mclk) (Mclk))
			((PWRflg0) (outDATA(4)))
			((PWRflg1) (outDATA(5)))
			((PWRflg2) (outDATA(6)))
			((PWRflg3) (outDATA(7)))
			((PWRflgIEw) (inDATA(1)))
			((Reset) (Reset))
			((outDATA) (outDATA(d_3_1)))
		)
		(_strength strong0 strong1)
	)
	(_model . EncReader 1 -1)

)
V 000054 55 7205          1083693488209 AddressDecode
(_unit VERILOG 6.349C.6.256 (AddressDecode 0 25 (AddressDecode 0 25 ))
	(_version v32)
	(_time 1083693488145 2004.05.04 10:58:08)
	(_source (\./src/addressdecode.v\ VERILOG (\./src/addressdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 16))
	(_entity
		(_time 1083693488145)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DRV0LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3LOWr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV0w ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV1w ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV0HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV1HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV2HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCURSELw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRV3HIGHr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVMTRCTLw ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVSTATr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 76 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 76 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 77 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 78 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 78 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 79 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 14 0 75 (_architecture (_function)(_target(22))
				(_read(21)(19)(20)(16)(18))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#87_0 (_architecture 0 0 87 (_process (_simple)
				(_target(15))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#90_1 (_architecture 1 0 90 (_process (_simple)
				(_target(4))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#93_2 (_architecture 2 0 93 (_process (_simple)
				(_target(8))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#96_3 (_architecture 3 0 96 (_process (_simple)
				(_target(0))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#99_4 (_architecture 4 0 99 (_process (_simple)
				(_target(9))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#102_5 (_architecture 5 0 102 (_process (_simple)
				(_target(1))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#105_6 (_architecture 6 0 105 (_process (_simple)
				(_target(10))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#108_7 (_architecture 7 0 108 (_process (_simple)
				(_target(2))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#111_8 (_architecture 8 0 111 (_process (_simple)
				(_target(12))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#114_9 (_architecture 9 0 114 (_process (_simple)
				(_target(3))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#117_10 (_architecture 10 0 117 (_process (_simple)
				(_target(14))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#120_11 (_architecture 11 0 120 (_process (_simple)
				(_target(6))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#123_12 (_architecture 12 0 123 (_process (_simple)
				(_target(7))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#ASSIGN#126_13 (_architecture 13 0 126 (_process (_simple)
				(_target(11))
				(_sensitivity(16)(13)(5))
				(_call(0))
			)))
			(#INTERNAL#0_15 (_internal 15 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 75
		)
	)
	(_model . AddressDecode 16 -1)

)
I 000045 55 3062          1083693626474 Fub2
(_unit VERILOG 6.349C.6.256 (Fub2 0 25 (Fub2 0 25 ))
	(_version v32)
	(_time 1083693626426 2004.05.04 11:00:26)
	(_source (\./src/fub2.v\ VERILOG (\./src/fub2.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1083693626426)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal ACE ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCURSELw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 49 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal analogr ~[3:0]reg~ 0 49 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#51_0 (_architecture 0 0 51 (_process 
				(_target(8))
				(_read(7)(3)(2)(1(d_3_0))(8))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Fub2 2 -1)

)
V 000043 55 20700         1083693662521 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083693662458 2004.05.04 11:01:02)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083693662458)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS0 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Current_enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCURSELw ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 220 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 235 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVCURSELw) (DRVCURSELw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 258 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 295 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 325 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 368 (_entity .  Fub2)
		(_port
			((ACE) (Current_enable))
			((AS0) (AS0))
			((AS1) (AS1))
			((AS2) (AS2))
			((DRVCURSELw) (DRVCURSELw))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
V 000050 55 3087          1083694629645 AnalogSel
(_unit VERILOG 6.349C.6.256 (AnalogSel 0 25 (AnalogSel 0 25 ))
	(_version v32)
	(_time 1083694629583 2004.05.04 11:17:09)
	(_source (\./src/analogsel.v\ VERILOG (\./src/analogsel.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1083694629583)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal ACE ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVCURSELw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 49 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal analogr ~[3:0]reg~ 0 49 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#51_0 (_architecture 0 0 51 (_process 
				(_target(8))
				(_read(7)(3)(2)(1(d_3_0))(8))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . AnalogSel 2 -1)

)
V 000043 55 20705         1083694829818 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1083694829770 2004.05.04 11:20:29)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1083694829770)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS0 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Current_enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCURSELw ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 220 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 235 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVCURSELw) (DRVCURSELw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 258 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 295 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 325 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 368 (_entity .  AnalogSel)
		(_port
			((ACE) (Current_enable))
			((AS0) (AS0))
			((AS1) (AS1))
			((AS2) (AS2))
			((DRVCURSELw) (DRVCURSELw))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 1 -1)

)
V 000043 55 20988         1084313379289 U4
(_unit VERILOG 6.349C.6.256 (U4 0 32 (U4 0 32 ))
	(_version v32)
	(_time 1084313379226 2004.05.11 15:09:39)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1084313379226)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BUSReset ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS0 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Current_enable ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCURSELw ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Reset ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#383_0 (_architecture 0 0 383 (_process (_alias ((Reset)(BUSReset)))(_simple)
				(_target(92))
				(_sensitivity(1))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 221 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 236 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVCURSELw) (DRVCURSELw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 259 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 296 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 326 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 369 (_entity .  AnalogSel)
		(_port
			((ACE) (Current_enable))
			((AS0) (AS0))
			((AS1) (AS1))
			((AS2) (AS2))
			((DRVCURSELw) (DRVCURSELw))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 2 -1)

)
V 000056 55 14100         1084389763002 ValveTranslator
(_unit VERILOG 6.349C.6.256 (ValveTranslator 0 25 (ValveTranslator 0 25 ))
	(_version v32)
	(_time 1084389762892 2004.05.12 12:22:42)
	(_source (\./src/valvetranslator.v\ VERILOG (\./src/valvetranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 35))
	(_entity
		(_time 1084389762892)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DRVVALV0w ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAH7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBH7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VAL7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL6 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal VBL7 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal DRVVALV1w ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal xlator.Vset ~reg 0 108 (_subprogram xlator (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal xlator.Vother ~reg 0 109 (_subprogram xlator (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal xlator.Dset ~reg 0 110 (_subprogram xlator (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal xlator.Dother ~reg 0 111 (_subprogram xlator (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal xlator.xlator ~reg 0 0 (_subprogram xlator (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[1:0]reg~ 0 115 (_array ~reg ((_downto (i 1) (i 0))))))
		(_signal (_internal V7 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V6 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V5 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V4 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V3 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V2 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V1 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal V0 ~[1:0]reg~ 0 115 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal xlator 33 0 107 (_architecture (_function)(_target(41))
				(_read(37)(38)(40)(39))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#117_0 (_architecture 0 0 117 (_process (_alias ((VAH0)(V0(0))))(_simple)
				(_target(2))
				(_sensitivity(49(0)))
			)))
			(#ASSIGN#118_1 (_architecture 1 0 118 (_process (_alias ((VBL0)(V0(0))))(_simple)
				(_target(15))
				(_sensitivity(49(0)))
			)))
			(#ASSIGN#119_2 (_architecture 2 0 119 (_process (_alias ((VBH0)(V0(1))))(_simple)
				(_target(3))
				(_sensitivity(49(1)))
			)))
			(#ASSIGN#120_3 (_architecture 3 0 120 (_process (_alias ((VAL0)(V0(1))))(_simple)
				(_target(12))
				(_sensitivity(49(1)))
			)))
			(#ASSIGN#122_4 (_architecture 4 0 122 (_process (_alias ((VAH1)(V1(0))))(_simple)
				(_target(4))
				(_sensitivity(48(0)))
			)))
			(#ASSIGN#123_5 (_architecture 5 0 123 (_process (_alias ((VBL1)(V1(0))))(_simple)
				(_target(19))
				(_sensitivity(48(0)))
			)))
			(#ASSIGN#124_6 (_architecture 6 0 124 (_process (_alias ((VBH1)(V1(1))))(_simple)
				(_target(6))
				(_sensitivity(48(1)))
			)))
			(#ASSIGN#125_7 (_architecture 7 0 125 (_process (_alias ((VAL1)(V1(1))))(_simple)
				(_target(16))
				(_sensitivity(48(1)))
			)))
			(#ASSIGN#127_8 (_architecture 8 0 127 (_process (_alias ((VAH2)(V2(0))))(_simple)
				(_target(7))
				(_sensitivity(47(0)))
			)))
			(#ASSIGN#128_9 (_architecture 9 0 128 (_process (_alias ((VBL2)(V2(0))))(_simple)
				(_target(24))
				(_sensitivity(47(0)))
			)))
			(#ASSIGN#129_10 (_architecture 10 0 129 (_process (_alias ((VBH2)(V2(1))))(_simple)
				(_target(9))
				(_sensitivity(47(1)))
			)))
			(#ASSIGN#130_11 (_architecture 11 0 130 (_process (_alias ((VAL2)(V2(1))))(_simple)
				(_target(20))
				(_sensitivity(47(1)))
			)))
			(#ASSIGN#132_12 (_architecture 12 0 132 (_process (_alias ((VAH3)(V3(0))))(_simple)
				(_target(8))
				(_sensitivity(46(0)))
			)))
			(#ASSIGN#133_13 (_architecture 13 0 133 (_process (_alias ((VBL3)(V3(0))))(_simple)
				(_target(27))
				(_sensitivity(46(0)))
			)))
			(#ASSIGN#134_14 (_architecture 14 0 134 (_process (_alias ((VBH3)(V3(1))))(_simple)
				(_target(11))
				(_sensitivity(46(1)))
			)))
			(#ASSIGN#135_15 (_architecture 15 0 135 (_process (_alias ((VAL3)(V3(1))))(_simple)
				(_target(23))
				(_sensitivity(46(1)))
			)))
			(#ASSIGN#137_16 (_architecture 16 0 137 (_process (_alias ((VAH4)(V4(0))))(_simple)
				(_target(10))
				(_sensitivity(45(0)))
			)))
			(#ASSIGN#138_17 (_architecture 17 0 138 (_process (_alias ((VBL4)(V4(0))))(_simple)
				(_target(29))
				(_sensitivity(45(0)))
			)))
			(#ASSIGN#139_18 (_architecture 18 0 139 (_process (_alias ((VBH4)(V4(1))))(_simple)
				(_target(14))
				(_sensitivity(45(1)))
			)))
			(#ASSIGN#140_19 (_architecture 19 0 140 (_process (_alias ((VAL4)(V4(1))))(_simple)
				(_target(26))
				(_sensitivity(45(1)))
			)))
			(#ASSIGN#142_20 (_architecture 20 0 142 (_process (_alias ((VAH5)(V5(0))))(_simple)
				(_target(13))
				(_sensitivity(44(0)))
			)))
			(#ASSIGN#143_21 (_architecture 21 0 143 (_process (_alias ((VBL5)(V5(0))))(_simple)
				(_target(31))
				(_sensitivity(44(0)))
			)))
			(#ASSIGN#144_22 (_architecture 22 0 144 (_process (_alias ((VBH5)(V5(1))))(_simple)
				(_target(18))
				(_sensitivity(44(1)))
			)))
			(#ASSIGN#145_23 (_architecture 23 0 145 (_process (_alias ((VAL5)(V5(1))))(_simple)
				(_target(28))
				(_sensitivity(44(1)))
			)))
			(#ASSIGN#147_24 (_architecture 24 0 147 (_process (_alias ((VAH6)(V6(0))))(_simple)
				(_target(17))
				(_sensitivity(43(0)))
			)))
			(#ASSIGN#148_25 (_architecture 25 0 148 (_process (_alias ((VBL6)(V6(0))))(_simple)
				(_target(33))
				(_sensitivity(43(0)))
			)))
			(#ASSIGN#149_26 (_architecture 26 0 149 (_process (_alias ((VBH6)(V6(1))))(_simple)
				(_target(22))
				(_sensitivity(43(1)))
			)))
			(#ASSIGN#150_27 (_architecture 27 0 150 (_process (_alias ((VAL6)(V6(1))))(_simple)
				(_target(30))
				(_sensitivity(43(1)))
			)))
			(#ASSIGN#152_28 (_architecture 28 0 152 (_process (_alias ((VAH7)(V7(0))))(_simple)
				(_target(21))
				(_sensitivity(42(0)))
			)))
			(#ASSIGN#153_29 (_architecture 29 0 153 (_process (_alias ((VBL7)(V7(0))))(_simple)
				(_target(34))
				(_sensitivity(42(0)))
			)))
			(#ASSIGN#154_30 (_architecture 30 0 154 (_process (_alias ((VBH7)(V7(1))))(_simple)
				(_target(25))
				(_sensitivity(42(1)))
			)))
			(#ASSIGN#155_31 (_architecture 31 0 155 (_process (_alias ((VAL7)(V7(1))))(_simple)
				(_target(32))
				(_sensitivity(42(1)))
			)))
			(#ALWAYS#157_32 (_architecture 32 0 157 (_process 
				(_target(42)(43)(44)(45)(46)(47)(48)(49)(49(0))(49(1))(48(0))(48(1))(47(0))(47(1))(46(0))(46(1))(45(0))(45(1))(44(0))(44(1))(43(0))(43(1))(42(0))(42(1)))
				(_read(35)(0)(1)(5(0))(5(1))(49(0))(49(1))(5(2))(5(3))(48(0))(48(1))(5(4))(5(5))(47(0))(47(1))(5(6))(5(7))(46(0))(46(1))(36)(45(0))(45(1))(44(0))(44(1))(43(0))(43(1))(42(0))(42(1))(42)(43)(44)(45)(46)(47)(48)(49))
				(_call(0))
			)))
			(#INTERNAL#0_34 (_internal 34 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit xlator function 0 107
		)
	)
	(_model . ValveTranslator 35 -1)

)
V 000043 55 20988         1084394113798 U4
(_unit VERILOG 6.349C.6.256 (U4 0 46 (U4 0 46 ))
	(_version v32)
	(_time 1084394113736 2004.05.12 13:35:13)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1084394113736)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BUSReset ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS0 ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS1 ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS2 ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Current_enable ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 53 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 53 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCURSELw ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 227 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Reset ~wire 0 228 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 229 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 230 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 231 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#397_0 (_architecture 0 0 397 (_process (_alias ((Reset)(BUSReset)))(_simple)
				(_target(92))
				(_sensitivity(1))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 235 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 250 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVCURSELw) (DRVCURSELw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 273 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 310 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 340 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 383 (_entity .  AnalogSel)
		(_port
			((ACE) (Current_enable))
			((AS0) (AS0))
			((AS1) (AS1))
			((AS2) (AS2))
			((DRVCURSELw) (DRVCURSELw))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 2 -1)

)
V 000043 55 21708         1084974370669 U4
(_unit VERILOG 6.349C.6.256 (U4 0 46 (U4 0 46 ))
	(_version v32)
	(_time 1084974370341 2004.05.19 06:46:10)
	(_source (\./compile/u4.v\ VERILOG (\./compile/u4.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 4))
	(_entity
		(_time 1084974370341)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BUSReset ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GPIO8 ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GPIO9 ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0data ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0flg ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1data ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1flg ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2data ~wire 0 46 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2flg ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3data ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3flg ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal WR ~wire 0 47 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS0 ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS1 ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal AS2 ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal BusINT ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Current_enable ~wire 0 47 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Heater_Control ~wire 0 48 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Motor1_Phase_A_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_A_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor1_Phase_B_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_A_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor2_Phase_B_LIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_HIN ~wire 0 48 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_A_LIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_HIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor3_Phase_B_LIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_HIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_A_LIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_HIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor4_Phase_B_LIN ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motor_Power_n ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_1 ~wire 0 49 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_2 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_3 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_4 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_5 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_6 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_7 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_High_8 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_1 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_2 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_3 ~wire 0 50 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_4 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_5 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_6 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_7 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Low_8 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_1 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_2 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_3 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_4 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_5 ~wire 0 51 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_6 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_7 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_High_8 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_1 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_2 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_3 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_4 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_5 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_6 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_7 ~wire 0 52 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Low_8 ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0clk ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R0enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1clk ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R1enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2clk ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R2enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3clk ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal R3enable ~wire 0 53 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 53 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 53 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0HIGHr ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV0LOWr ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1HIGHr ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV1LOWr ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2HIGHr ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV2LOWr ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3HIGHr ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRV3LOWr ~wire 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCTLw ~wire 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVCURSELw ~wire 0 227 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVMTRCTLw ~wire 0 228 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVSTATr ~wire 0 229 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV0w ~wire 0 230 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal DRVVALV1w ~wire 0 231 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3281 ~wire 0 232 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Reset ~wire 0 233 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR ~[7:0]wire~ 0 234 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 235 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 236 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#402_0 (_architecture 0 0 402 (_process (_alias ((Reset)(BUSReset)))(_simple)
				(_target(95))
				(_sensitivity(1))
			)))
			(#ASSIGN#407_1 (_architecture 1 0 407 (_process (_alias ((NET3281)(GPIO9)))(_simple)
				(_target(94))
				(_sensitivity(3))
			)))
			(#ASSIGN#410_2 (_architecture 2 0 410 (_process (_alias ((Heater_Control)(NET3281)))(_simple)
				(_target(20))
				(_sensitivity(94))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 240 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (ADDR))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 255 (_entity .  AddressDecode)
		(_port
			((ADDR) (ADDR))
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVCURSELw) (DRVCURSELw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((DRVSTATr) (DRVSTATr))
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 278 (_entity .  EncReader)
		(_port
			((DRV0HIGHr) (DRV0HIGHr))
			((DRV0LOWr) (DRV0LOWr))
			((DRV1HIGHr) (DRV1HIGHr))
			((DRV1LOWr) (DRV1LOWr))
			((DRV2HIGHr) (DRV2HIGHr))
			((DRV2LOWr) (DRV2LOWr))
			((DRV3HIGHr) (DRV3HIGHr))
			((DRV3LOWr) (DRV3LOWr))
			((DRVCTLw) (DRVCTLw))
			((DRVSTATr) (DRVSTATr))
			((ENCint) (BusINT))
			((Mclk) (Mclk))
			((Renable0) (R0enable))
			((Renable1) (R1enable))
			((Renable2) (R2enable))
			((Renable3) (R3enable))
			((Reset) (Reset))
			((Rflg0) (R0flg))
			((Rflg1) (R1flg))
			((Rflg2) (R2flg))
			((Rflg3) (R3flg))
			((SSclk0) (R0clk))
			((SSclk1) (R1clk))
			((SSclk2) (R2clk))
			((SSclk3) (R3clk))
			((data0) (R0data))
			((data1) (R1data))
			((data2) (R2data))
			((data3) (R3data))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 315 (_entity .  PWMTranslator)
		(_port
			((DRVCTLw) (DRVCTLw))
			((DRVMTRCTLw) (DRVMTRCTLw))
			((MTRPWR) (Motor_Power))
			((MTRPWR_n) (Motor_Power_n))
			((Mclk) (Mclk))
			((Motor0_Phase_A_HIN) (Motor1_Phase_A_HIN))
			((Motor0_Phase_A_LIN) (Motor1_Phase_A_LIN))
			((Motor0_Phase_B_HIN) (Motor1_Phase_B_HIN))
			((Motor0_Phase_B_LIN) (Motor1_Phase_B_LIN))
			((Motor1_Phase_A_HIN) (Motor2_Phase_A_HIN))
			((Motor1_Phase_A_LIN) (Motor2_Phase_A_LIN))
			((Motor1_Phase_B_HIN) (Motor2_Phase_B_HIN))
			((Motor1_Phase_B_LIN) (Motor2_Phase_B_LIN))
			((Motor2_Phase_A_HIN) (Motor3_Phase_A_HIN))
			((Motor2_Phase_A_LIN) (Motor3_Phase_A_LIN))
			((Motor2_Phase_B_HIN) (Motor3_Phase_B_HIN))
			((Motor2_Phase_B_LIN) (Motor3_Phase_B_LIN))
			((Motor3_Phase_A_HIN) (Motor4_Phase_A_HIN))
			((Motor3_Phase_A_LIN) (Motor4_Phase_A_LIN))
			((Motor3_Phase_B_HIN) (Motor4_Phase_B_HIN))
			((Motor3_Phase_B_LIN) (Motor4_Phase_B_LIN))
			((PWMsource) (GPIO8))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 345 (_entity .  ValveTranslator)
		(_port
			((DRVVALV0w) (DRVVALV0w))
			((DRVVALV1w) (DRVVALV1w))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((VAH0) (PhaseA_High_1))
			((VAH1) (PhaseA_High_2))
			((VAH2) (PhaseA_High_3))
			((VAH3) (PhaseA_High_4))
			((VAH4) (PhaseA_High_5))
			((VAH5) (PhaseA_High_6))
			((VAH6) (PhaseA_High_7))
			((VAH7) (PhaseA_High_8))
			((VAL0) (PhaseA_Low_1))
			((VAL1) (PhaseA_Low_2))
			((VAL2) (PhaseA_Low_3))
			((VAL3) (PhaseA_Low_4))
			((VAL4) (PhaseA_Low_5))
			((VAL5) (PhaseA_Low_6))
			((VAL6) (PhaseA_Low_7))
			((VAL7) (PhaseA_Low_8))
			((VBH0) (PhaseB_High_1))
			((VBH1) (PhaseB_High_2))
			((VBH2) (PhaseB_High_3))
			((VBH3) (PhaseB_High_4))
			((VBH4) (PhaseB_High_5))
			((VBH5) (PhaseB_High_6))
			((VBH6) (PhaseB_High_7))
			((VBH7) (PhaseB_High_8))
			((VBL0) (PhaseB_Low_1))
			((VBL1) (PhaseB_Low_2))
			((VBL2) (PhaseB_Low_3))
			((VBL3) (PhaseB_Low_4))
			((VBL4) (PhaseB_Low_5))
			((VBL5) (PhaseB_Low_6))
			((VBL6) (PhaseB_Low_7))
			((VBL7) (PhaseB_Low_8))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 388 (_entity .  AnalogSel)
		(_port
			((ACE) (Current_enable))
			((AS0) (AS0))
			((AS1) (AS1))
			((AS2) (AS2))
			((DRVCURSELw) (DRVCURSELw))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U4 4 -1)

)