[Project]
Current Flow=Multivendor
VCS=0
version=3
Current Config=compile

[Configurations]
compile=U4

[Library]
U4=.\U4.LIB
U4_post_synthesis=.\U4_post_synthesis\U4_post_synthesis.lib
U4_timing=.\U4_timing\U4_timing.lib

[$LibMap$]
U4=.
Active_lib=XC9500
xilinxun=XC9500
UnlinkedDesignLibrary=XC9500
DESIGNS=XC9500

[Settings]
FLOW_TYPE=HDL
LANGUAGE=VERILOG
REFRESH_FLOW=1
SYNTH_TOOL=MV_XST6
IMPL_TOOL=MV_ISE61
FAMILY=Xilinx6x COOLRUNNER
FLOWTOOLS=IMPL_WITH_SYNTH
FUNC_LIB=U4
POST_LIB=U4_post_synthesis
TIM_LIB=U4_timing
SYNTH_STATUS=warnings
IMPL_STATUS=warnings
RUN_MODE_IMPL=0
RUN_MODE_SYNTH=0
AccessRead=0
AccessReadWrite=0
AccessACCB=0
AccessACCR=0
AccessReadWriteSLP=0
AccessReadTopLevel=0
DisableC=0

[IMPLEMENTATION]
UCF=C:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src\U4.ucf
FAMILY=Xilinx6x COOLRUNNER
DEVICE=r3384xlTQ144
SPEED=-10
NETLIST=c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\synthesis\U4.ngc
DEF_UCF=0
JOB_DESCRIPTION=ImplementationJob1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
LAST_RUN=1084974424
OUTPUT_NETLIST=IMPLEMENT\TIME_SIM.V
OUTPUT_SDF=

[HierarchyViewer]
SortInfo=u
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=

[SIM.FUNC]
FJD=FunctionalSimJob1
FST=-all
OPTION=0
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*:synthesis\*.*:implement\*.*
TOPLEVEL=RValve_TB
WAVEFORMS=
DEFWAVE=0

[SYNTHESIS]
OBSOLETE_ALIASES=1
TOPLEVEL=U4
FAMILY=Xilinx6x COOLRUNNER
DEVICE=COOLRUNNER
SPEED=
FSM_ENCODE=
PACK_IO_REGISTERS=
SIMOUTFORM=2
AUTO_CLOSE_GUI=0
USE_DEF_UCF_FILE=1
UCF_FILENAME=
LSO_FILENAME=
HDL_INI_FILENAME=
XST_INCLUDE_PATH=c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/src
CORES_SEARCH_DIR=
OTHER_COMMAND_LINE_OPT=
XST_WORK_DIR=c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/synthesis/xst
Show_OptimizationGoalCombo=Speed
Show_OptimizationEffortCombo=Normal
Show_FSM_Encoding_Algorithm=Auto
Show_MuxExtractionCombo=Yes
Show_Resource_Sharing=1
Show_Add_IO_Buffer=1
Show_Equivalent_Register_Removal=1
Show_Clock_Enable=1
Show_Macro_Preserve=1
Show_Xor_Preserve=1
Show_WysiwygCombo=None
Show_Case_Implementation_Style=None
Show_JobDescription=JobDesc1
Show_IncludeInputFiles=*.*
Show_ExcludeInputFiles=log*.*:implement*.*
Show_UseSynthesisConstraintsFile=0
Show_HierarchySeparator=_
Show_BusDelimiter=<>
Show_GenerateRtlSchematic=Yes
Show_CaseVhdl=Maintain
Show_Verilog2001=1
Show_SimulationOutputFormat=2
Show_KeepHierarchyCPLD=Yes
RAM_STYLE=Auto
ROM_STYLE=Auto
MUX_STYLE=Auto
MOVE_FIRST_FF_STAGE=1
MOVE_LAST_FF_STAGE=1
JOB_DESCRIPTION=JobDesc1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
LAST_RUN=1084974379
OUTPUT_NETLIST=c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\synthesis\U4.ngc
OUTPUT_SIMUL_NETLIST=synthesis\U4.v

[Groups]
post-synthesis=1
timing=1

[IMPLEMENTATION_XILINX6]
impl_opt(edif_str)=c:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\synthesis\U4.ngc
impl_opt(_family_sel)=Xilinx6x COOLRUNNER
impl_opt(_device_sel)=r3384xlTQ144
impl_opt(_speed_sel)=-10
impl_opt(netlist_format)=2
impl_opt(auto_close)=0
impl_opt(override_existing_project)=1
impl_opt(bat_file_name)=
impl_opt(is_bat_mode)=0
impl_opt(version_sel)=ver0
impl_opt(revision_sel)=rev2
impl_opt(xon)=0
impl_opt(Use_Location_Constraints)=Always
impl_opt(Output_Slew_Rate)=Slow
impl_opt(Default_PowerUp)=Low
impl_opt(fit_mode)=0
impl_opt(log_opt)=1
impl_opt(Use_Fast_Input_For_Registers)=1
impl_opt(Collapsing_Input_Limit_4_40)=32
impl_opt(Collapsing_Pterm_Limit_3_48)=28
impl_opt(ngdbuild_file_str)=
impl_opt(use_ngdbuild_file)=0
impl_opt(netgen_file_str)=
impl_opt(use_netgen_file)=0
impl_opt(cpldfit_file_str)=
impl_opt(use_cpldfit_file)=0
impl_opt(hprep6_file_str)=
impl_opt(use_hprep6_file)=0
impl_opt(Allow_Unmatched_LOC_Constraint)=0
impl_opt(Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=
impl_opt(Use_Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=0
impl_opt(Show_Generate_Testbench_File)=0
impl_opt(Function_Block_Input_Limit)=38
impl_opt(Input_Pin_Termination)=Float
impl_opt(Unused_Pin_Termination_Mode)=Pullup
impl_opt(Show_Use_Timing_Constraint)=1
impl_opt(Other_Ngdbuild_Options)=
impl_opt(Implementation_Template_1)=Optimize Balance
impl_opt(Logic_Optimization_1)=Speed
impl_opt(Preserve_Unused_Inputs)=0
impl_opt(Use_Function_Block_Clock)=1
impl_opt(Use_Foldback_Nands)=0
impl_opt(Reserve_Isp_Pins)=1
impl_opt(Other_Fitter_Commands)=
impl_opt(Retain_Hiearchy)=1
impl_opt(Reset_Configuration_Pulsee)=
impl_opt(Generate_Architecture_Only)=0
impl_opt(Include_Uselib_Directive)=0
impl_opt(Do_Not_Escape_Signal)=0
impl_opt(Other_Netgen_Command)=
impl_opt(Macro_Search_Path)=
impl_opt(Path_Used_In_Sdf)=c:/Projects/genosensor/2g/CPLDs/Rvavle/Rvalve/U4/implement

[sdf.vm.RValve_TB]
0=IMPLEMENT\TIME_SIM.SDF| /U1, Average, No
SdfNoWarn=0
IVG=0

[SIM.TIME]
SDF_PATH=
TOPLEVEL=U4 glbl

[Files]
/U4.bde=-1
/Design Notes.txt=-1
/U4.ucf=-1
/interface.v=-1
/AddressDecode.v=-1
/encreader.bde=-1
/EncoderControl.v=-1
/EncShift.v=-1
/ENCinterrupt.v=-1
/RVALVEaddressmap.v=-1
/PWMTranslator.v=-1
/RValve_TB.bde=-1
/msp.v=-1
/MSP_vectors.txt=-1
/functional.awf=-1
/ValveTranslator.v=-1
/AnalogSel.v=-1
post-synthesis/..\..\synthesis\U4.v=-1
timing/..\..\IMPLEMENT\TIME_SIM.V=-1
timing/..\..\IMPLEMENT\TIME_SIM.SDF=-1
timing/..\..\implement\glbl.v=-1

[Files.Data]
.\src\U4.bde=Block Diagram
.\src\Design Notes.txt=Text File
.\src\U4.ucf=External File
.\src\interface.v=Verilog Source Code
.\src\AddressDecode.v=Verilog Source Code
.\src\encreader.bde=Block Diagram
.\src\EncoderControl.v=Verilog Source Code
.\src\EncShift.v=Verilog Source Code
.\src\ENCinterrupt.v=Verilog Source Code
.\src\RVALVEaddressmap.v=Verilog Source Code
.\src\PWMTranslator.v=Verilog Source Code
.\src\RValve_TB.bde=Block Diagram
.\src\msp.v=Verilog Source Code
.\src\MSP_vectors.txt=Text File
.\src\functional.awf=Waveform File
.\src\ValveTranslator.v=Verilog Source Code
.\src\AnalogSel.v=Verilog Source Code
.\synthesis\U4.v=Verilog Source Code
.\IMPLEMENT\TIME_SIM.V=Verilog Source Code
.\IMPLEMENT\TIME_SIM.SDF=SDF File
.\implement\glbl.v=Verilog Source Code


[file_out:/encreader.bde]
/\compile\encreader.v=-1

[file_out:/RValve_TB.bde]
/\compile\RValve_TB.v=-1

[LocalVhdlSets]
CompileWithDebug=1
[LocalVerilogSets]
EnableDebug=1
EnableSLP=0
[file_out:/U4.bde]
/\compile\U4.v=-1
[SpecTracer]
WindowVisible=0