 
cpldfit:  version G.26                              Xilinx Inc.
                                  Fitter Report
Design Name: U4                                  Date:  5-12-2004,  1:37PM
Device Used: XCR3384XL-10-TQ144
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
160/384 ( 42%) 406 /1344 ( 30%) 107/384 ( 28%) 85 /114 ( 75%) 362/960 ( 38%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   13          13    |  I/O              :    84       26
Output        :   63          63    |  GCK/IO           :     1        3
Bidirectional :    8           8    |  
GCK           :    1           1    |  
                 ----        ----
        Total      85          85 

MACROCELL RESOURCES:

Total Macrocells Available                   384
Registered Macrocells                        107
Non-registered Macrocell driving I/O          32

GLOBAL RESOURCES:

Signal 'Mclk' mapped onto global clock net GCK2.
Universal Control Terms (Used/Total)                      : 2/4

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Total)     : 2/192
Total Foldback NANDs (Used/Total)                         : 0/192

End of Resource Summary
****************************  Errors and Warnings  *************************

WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg Init
Name                Pt    Used            Rate #    Type      Use     State
AD<0>               10      18    FB1_16  SLOW 91   I/O       I/O     
AD<1>               10      14    FB1_13  SLOW 92   I/O       I/O     
AD<2>               10      13    FB1_5   SLOW 93   I/O       I/O     
AD<3>               10      13    FB1_1   SLOW 94   I/O       I/O     
AD<4>               10      14    FB2_2   SLOW 96   I/O       I/O     
AD<5>               10      14    FB2_3   SLOW 97   I/O       I/O     
AD<6>               10      14    FB2_4   SLOW 98   I/O       I/O     
AD<7>               10      14    FB2_5   SLOW 99   I/O       I/O     
AS0                 0       0     FB14_2  SLOW 47   I/O       O       
AS1                 0       0     FB16_2  SLOW 48   I/O       O       
AS2                 0       0     FB16_4  SLOW 49   I/O       O       
BusINT              1       1     FB8_16  SLOW 74   I/O       O       
Current_enable      0       0     FB14_3  SLOW 46   I/O       O       
DRV0HIGHr           1       10    FB3_6             (b)       (b)     
DRV0LOWr            1       10    FB3_3             (b)       (b)     
DRV1HIGHr           1       10    FB3_2             (b)       (b)     
DRV1LOWr            1       10    FB3_1             (b)       (b)     
DRV2HIGHr           1       10    FB3_16       87   I/O       I       
DRV2LOWr            1       10    FB3_14       88   I/O       I       
DRV3HIGHr           1       10    FB3_5        89   I/O       I       
DRV3LOWr            1       10    FB8_13            (b)       (b)     
DRVCTLw             1       10    FB8_12            (b)       (b)     
DRVMTRCTLw          1       10    FB8_11            (b)       (b)     
DRVSTATr            1       10    FB8_10            (b)       (b)     
DRVVALV0w           1       10    FB8_9             (b)       (b)     
DRVVALV1w           1       10    FB8_8             (b)       (b)     
Motor1_Phase_A_HIN  1       3     FB19_15 SLOW 140  I/O       O       
Motor1_Phase_A_LIN  2       3     FB12_1  SLOW 139  I/O       O       
Motor1_Phase_B_HIN  1       3     FB12_3  SLOW 138  I/O       O       
Motor1_Phase_B_LIN  2       3     FB12_4  SLOW 137  I/O       O       
Motor2_Phase_A_HIN  1       3     FB12_13 SLOW 136  I/O       O       
Motor2_Phase_A_LIN  2       3     FB10_16 SLOW 134  I/O       O       
Motor2_Phase_B_HIN  1       3     FB10_15 SLOW 133  I/O       O       
Motor2_Phase_B_LIN  2       3     FB10_4  SLOW 132  I/O       O       
Motor3_Phase_A_HIN  1       3     FB9_5   SLOW 120  I/O       O       
Motor3_Phase_A_LIN  2       3     FB11_16 SLOW 119  I/O       O       
Motor3_Phase_B_HIN  1       3     FB11_15 SLOW 118  I/O       O       
Motor3_Phase_B_LIN  2       3     FB11_5  SLOW 117  I/O       O       
Motor4_Phase_A_HIN  1       3     FB4_16  SLOW 116  I/O       O       
Motor4_Phase_A_LIN  2       3     FB4_15  SLOW 114  I/O       O       
Motor4_Phase_B_HIN  1       3     FB4_14  SLOW 113  I/O       O       
Motor4_Phase_B_LIN  2       3     FB4_13  SLOW 112  I/O       O       
Motor_Power         2       4     FB21_13 SLOW 40   I/O       O       RESET
Motor_Power_n       3       4     FB4_5   SLOW 111  I/O       O       SET
N_PZ_1048           24      30    FB5_2        86   TCK/I/O   (b)     
N_PZ_577            2       3     FB1_8             (b)       (b)     
N_PZ_578            2       3     FB5_10            (b)       (b)     
N_PZ_579            2       3     FB2_9             (b)       (b)     
N_PZ_580            2       3     FB2_8             (b)       (b)     
N_PZ_581            1       2     FB8_1             (b)       (b)     
N_PZ_628            2       5     FB8_15            (b)       (b)     
PhaseA_High_1       4       8     FB21_16 SLOW 37   I/O       O       RESET
PhaseA_High_2       4       8     FB24_14 SLOW 32   I/O       O       RESET
PhaseA_High_3       4       8     FB24_3  SLOW 28   I/O       O       RESET
PhaseA_High_4       4       8     FB22_13 SLOW 23   I/O       O       RESET
PhaseA_High_5       4       8     FB20_16 SLOW 18   I/O       O       RESET
PhaseA_High_6       4       8     FB18_16 SLOW 12   I/O       O       RESET
PhaseA_High_7       4       8     FB18_2  SLOW 8    I/O       O       RESET
PhaseA_High_8       4       8     FB17_5  SLOW 4    I/O       O       RESET
PhaseA_Low_1        4       8     FB23_1  SLOW 36   I/O       O       RESET
PhaseA_Low_2        4       8     FB24_13 SLOW 31   I/O       O       RESET
PhaseA_Low_3        4       8     FB24_2  SLOW 27   I/O       O       RESET
PhaseA_Low_4        4       8     FB22_4  SLOW 21   I/O       O       RESET
PhaseA_Low_5        4       8     FB20_14 SLOW 16   I/O       O       RESET
PhaseA_Low_6        4       8     FB18_15 SLOW 11   I/O       O       RESET
PhaseA_Low_7        4       8     FB18_1  SLOW 7    I/O       O       RESET
PhaseA_Low_8        4       8     FB17_15 SLOW 2    I/O       O       RESET
PhaseB_High_1       3       6     FB23_14 SLOW 35   I/O       O       RESET
PhaseB_High_2       3       6     FB24_5  SLOW 30   I/O       O       RESET
PhaseB_High_3       3       6     FB24_1  SLOW 26   I/O       O       RESET
PhaseB_High_4       3       6     FB22_3  SLOW 20   I/O       O       RESET
PhaseB_High_5       4       7     FB20_4  SLOW 15   I/O       O       RESET
PhaseB_High_6       4       7     FB18_4  SLOW 10   I/O       O       RESET
PhaseB_High_7       4       7     FB17_3  SLOW 6    I/O       O       RESET
PhaseB_High_8       4       7     FB17_16 SLOW 1    I/O       O       RESET
PhaseB_Low_1        3       6     FB24_16 SLOW 34   I/O       O       RESET
PhaseB_Low_2        3       6     FB24_4  SLOW 29   I/O       O       RESET
PhaseB_Low_3        3       6     FB22_16 SLOW 25   I/O       O       RESET
PhaseB_Low_4        3       6     FB22_1  SLOW 19   I/O       O       RESET
PhaseB_Low_5        4       7     FB20_1  SLOW 14   I/O       O       RESET
PhaseB_Low_6        4       7     FB18_3  SLOW 9    I/O       O       RESET
PhaseB_Low_7        4       7     FB17_4  SLOW 5    I/O       O       RESET
PhaseB_Low_8        4       7     FB19_2  SLOW 143  I/O       O       RESET
R0clk               2       2     FB15_3  SLOW 60   I/O       O       
R0enable            3       4     FB8_2   SLOW 71   I/O       O       SET
R1clk               2       2     FB4_3   SLOW 107  I/O       O       
R1enable            3       4     FB8_3   SLOW 72   I/O       O       SET
R2clk               2       2     FB2_16  SLOW 103  I/O       O       
R2enable            3       4     FB14_16 SLOW 43   I/O       O       SET
R3clk               4       5     FB2_14  SLOW 101  I/O       O       RESET
R3enable            3       4     FB14_14 SLOW 44   I/O       O       SET
U1_ADDR_reg<0>      5       14    FB3_11            (b)       (b)     RESET
U1_ADDR_reg<1>      5       15    FB3_9             (b)       (b)     RESET
U1_ADDR_reg<2>      4       15    FB3_10            (b)       (b)     RESET
U1_ADDR_reg<3>      5       15    FB3_8             (b)       (b)     RESET
U1_ADDR_reg<4>      6       15    FB3_7             (b)       (b)     RESET
U1_ADDR_reg<5>      3       6     FB3_12            (b)       (b)     RESET
U1_ADDR_reg<6>      3       6     FB6_1        67   I/O       I       RESET
U1_ADDR_reg<7>      3       6     FB7_2        79   I/O       I       RESET
U1_ASedge           0       0     FB3_4        90   I/O       I       RESET
U1_AutoInc          2       3     FB3_13            (b)       (b)     RESET
U1_Enable_AD        2       8     FB8_14            (b)       (b)     
U1_WRRDedge         1       1     FB3_15            (b)       (b)     RESET
U3_NET282           3       6     FB6_11            (b)       (b)     RESET
U3_U1/BitCounter<0> 2       4     FB4_9             (b)       (b)     RESET
U3_U1/BitCounter<1> 2       5     FB4_10            (b)       (b)     RESET
U3_U1/BitCounter<2> 3       6     FB4_11            (b)       (b)     RESET
U3_U1/BitCounter<3> 3       7     FB4_12            (b)       (b)     RESET
U3_U1/CEr           3       5     FB6_12            (b)       (b)     RESET
U3_U1/DAVr          4       9     FB4_1             (b)       (b)     RESET
U3_U1/SS            4       9     FB4_4             (b)       (b)     RESET
U3_U1/divider<0>    2       5     FB6_14            (b)       (b)     RESET
U3_U1/divider<1>    3       6     FB6_13            (b)       (b)     RESET
U3_U1/divider<2>    1       3     FB6_15            (b)       (b)     RESET
U3_U1/divider<3>    1       3     FB6_10            (b)       (b)     RESET
U3_U2_EncReg<0>     2       6     FB1_11            (b)       (b)     RESET
U3_U2_EncReg<1>     2       6     FB1_15            (b)       (b)     RESET
U3_U2_EncReg<2>     2       6     FB1_14            (b)       (b)     RESET
U3_U2_EncReg<3>     2       6     FB1_12            (b)       (b)     RESET
U3_U2_EncReg<4>     2       6     FB1_10            (b)       (b)     RESET
U3_U2_EncReg<5>     2       6     FB1_9             (b)       (b)     RESET
U3_U2_EncReg<6>     2       6     FB5_5             (b)       (b)     RESET
U3_U2_EncReg<7>     2       6     FB5_14            (b)       (b)     RESET
U3_U2_EncReg<8>     2       6     FB5_15            (b)       (b)     RESET
U3_U3_EncReg<0>     2       6     FB4_8             (b)       (b)     RESET
U3_U3_EncReg<1>     2       6     FB4_7             (b)       (b)     RESET
U3_U3_EncReg<2>     2       6     FB4_6             (b)       (b)     RESET
U3_U3_EncReg<3>     2       6     FB4_2        106  I/O       I       RESET
U3_U3_EncReg<4>     2       6     FB5_11            (b)       (b)     RESET
U3_U3_EncReg<5>     2       6     FB5_16            (b)       (b)     RESET
U3_U3_EncReg<6>     2       6     FB5_13            (b)       (b)     RESET
U3_U3_EncReg<7>     2       6     FB5_12            (b)       (b)     RESET
U3_U3_EncReg<8>     2       6     FB7_1             (b)       (b)     RESET
U3_U4_EncReg<0>     2       6     FB7_3             (b)       (b)     RESET
U3_U4_EncReg<1>     2       6     FB7_4             (b)       (b)     RESET
U3_U4_EncReg<2>     2       6     FB7_15            (b)       (b)     RESET
U3_U4_EncReg<3>     2       6     FB7_16            (b)       (b)     RESET
U3_U4_EncReg<4>     2       6     FB2_10            (b)       (b)     RESET
U3_U4_EncReg<5>     2       6     FB2_13            (b)       (b)     RESET
U3_U4_EncReg<6>     2       6     FB2_12            (b)       (b)     RESET
U3_U4_EncReg<7>     2       6     FB2_11            (b)       (b)     RESET
U3_U4_EncReg<8>     2       6     FB7_14            (b)       (b)     RESET
U3_U5_EncReg<0>     2       6     FB7_13            (b)       (b)     RESET
U3_U5_EncReg<1>     2       6     FB7_12            (b)       (b)     RESET
U3_U5_EncReg<2>     2       6     FB7_11            (b)       (b)     RESET
U3_U5_EncReg<3>     2       6     FB7_10            (b)       (b)     RESET
U3_U5_EncReg<4>     2       6     FB7_9             (b)       (b)     RESET
U3_U5_EncReg<5>     2       6     FB7_8             (b)       (b)     RESET
U3_U5_EncReg<6>     2       6     FB7_7             (b)       (b)     RESET
U3_U5_EncReg<7>     2       6     FB7_6             (b)       (b)     RESET
U3_U5_EncReg<8>     2       6     FB7_5             (b)       (b)     RESET
U3_U6_PWRflgier     2       4     FB6_9             (b)       (b)     RESET
U4/M00              2       4     FB6_7             (b)       (b)     RESET
U4/M01              2       4     FB6_8             (b)       (b)     RESET
U4/M10              2       4     FB6_6             (b)       (b)     RESET
U4/M11              2       4     FB6_5             (b)       (b)     RESET
U4/M20              2       4     FB6_4             (b)       (b)     RESET
U4/M21              2       4     FB6_3             (b)       (b)     RESET
U4/M30              2       4     FB6_2             (b)       (b)     RESET
U4/M31              2       4     FB6_16       69   I/O       I       RESET

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
AS                                FB3_4        90   I/O       I                  
BUSReset                          FB3_16       87   I/O       I                  
GPIO8                             FB7_2        79   I/O       I                  
Mclk                                           126  GCK/I     GCK                
R0data                            FB13_1       61   I/O       I                  
R0flg                             FB13_3       62   I/O       I                  
R1data                            FB4_2        106  I/O       I                  
R1flg                             FB13_14      65   I/O       I                  
R2data                            FB2_15       102  I/O       I                  
R2flg                             FB13_16      66   I/O       I                  
R3data                            FB6_16       69   I/O       I                  
R3flg                             FB6_1        67   I/O       I                  
RD                                FB3_5        89   I/O       I                  
WR                                FB3_14       88   I/O       I                  

End of Resources

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          11          38          38           41         0/4        4   
FB2          12          38          38           41         2/4        7   
FB3          16          23          23           39         0/0        4   
FB4          16          23          23           37         6/0        7   
FB5           9          38          38           40         0/0        0   
FB6          16          30          30           34         0/0        2   
FB7          16          32          32           33         0/0        1   
FB8          12          20          20           16         3/0        3   
FB9           1           3           3            1         1/0        2   
FB10          3           3           3            5         3/0        3   
FB11          3           3           3            5         3/0        3   
FB12          4           5           5            6         4/0        4   
FB13          0           0           0            0         0/0        4   
FB14          4           6           6            4         4/0        4   
FB15          1           2           2            2         1/0        2   
FB16          2           0           0            0         2/0        2   
FB17          5          13          13           17         5/0        5   
FB18          6          15          15           18         6/0        6   
FB19          2          10          10            5         2/0        2   
FB20          4           9           9           10         4/0        4   
FB21          2          11          11            6         2/0        2   
FB22          5          13          13           15         5/0        5   
FB23          2           8           8            6         2/0        2   
FB24          8          19          19           25         8/0        8   
            ----                                -----       -----     ----- 
            160                                  406        63/8       86   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  38
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   41/7
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
AD<3>                              10    FB1_1      94   I/O   I/O
(unused)                            0    FB1_2           (b)      
(unused)                            0    FB1_3           (b)      
(unused)                            0    FB1_4           (b)      
AD<2>                              10    FB1_5      93   I/O   I/O
(unused)                            0    FB1_6           (b)      
(unused)                            0    FB1_7           (b)      
N_PZ_577                            2    FB1_8           (b)   (b)
U3_U2_EncReg<5>                     2    FB1_9           (b)   (b)
U3_U2_EncReg<4>                     2    FB1_10          (b)   (b)
U3_U2_EncReg<0>                     2    FB1_11          (b)   (b)
U3_U2_EncReg<3>                     2    FB1_12          (b)   (b)
AD<1>                              10    FB1_13     92   I/O   I/O
U3_U2_EncReg<2>                     2    FB1_14          (b)   (b)
U3_U2_EncReg<1>                     2    FB1_15          (b)   (b)
AD<0>                              10    FB1_16     91   I/O   I/O

Signals Used by Logic in Function Block
  1: BUSReset          14: U3_NET282         27: U3_U3_EncReg<8> 
  2: DRV0HIGHr         15: U3_U1/DAVr        28: U3_U4_EncReg<0> 
  3: DRV0LOWr          16: U3_U2_EncReg<0>   29: U3_U4_EncReg<1> 
  4: DRV1HIGHr         17: U3_U2_EncReg<1>   30: U3_U4_EncReg<2> 
  5: DRV1LOWr          18: U3_U2_EncReg<2>   31: U3_U4_EncReg<3> 
  6: DRV2HIGHr         19: U3_U2_EncReg<3>   32: U3_U4_EncReg<8> 
  7: DRV2LOWr          20: U3_U2_EncReg<4>   33: U3_U5_EncReg<0> 
  8: DRV3HIGHr         21: U3_U2_EncReg<5>   34: U3_U5_EncReg<1> 
  9: DRV3LOWr          22: U3_U2_EncReg<8>   35: U3_U5_EncReg<2> 
 10: DRVSTATr          23: U3_U3_EncReg<0>   36: U3_U5_EncReg<3> 
 11: N_PZ_577          24: U3_U3_EncReg<1>   37: U3_U5_EncReg<8> 
 12: R0data            25: U3_U3_EncReg<2>   38: U3_U6_PWRflgier 
 13: R0enable          26: U3_U3_EncReg<3>  

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
AD<3>             .XXXXXXXXX........X......X....X....X.... 13      13
AD<2>             .XXXXXXXXX.......X......X....X....X..... 13      13
N_PZ_577          X...........XX.......................... 3       3
U3_U2_EncReg<5>   X.........X.XX.....XX................... 6       6
U3_U2_EncReg<4>   X.........X.XX....XX.................... 6       6
U3_U2_EncReg<0>   X.........XXXX.X........................ 6       6
U3_U2_EncReg<3>   X.........X.XX...XX..................... 6       6
AD<1>             .XXXXXXXXX......X......X....X....X...X.. 14      14
U3_U2_EncReg<2>   X.........X.XX..XX...................... 6       6
U3_U2_EncReg<1>   X.........X.XX.XX....................... 6       6
AD<0>             .XXXXXXXXX....XX.....XX...XX...XX...X... 18      18
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  38
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   41/7
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB2_1           (b)      
AD<4>                              10    FB2_2      96   I/O   I/O
AD<5>                              10    FB2_3      97   I/O   I/O
AD<6>                              10    FB2_4      98   I/O   I/O
AD<7>                              10    FB2_5      99   I/O   I/O
(unused)                            0    FB2_6           (b)      
(unused)                            0    FB2_7           (b)      
N_PZ_580                            2    FB2_8           (b)   (b)
N_PZ_579                            2    FB2_9           (b)   (b)
U3_U4_EncReg<4>                     2    FB2_10          (b)   (b)
U3_U4_EncReg<7>                     2    FB2_11          (b)   (b)
U3_U4_EncReg<6>                     2    FB2_12          (b)   (b)
U3_U4_EncReg<5>                     2    FB2_13          (b)   (b)
R3clk                               4    FB2_14    101   I/O     O
(unused)                            0    FB2_15    102   I/O     I
R2clk                               2    FB2_16    103   I/O     O

Signals Used by Logic in Function Block
  1: BUSReset          14: R2enable          27: U3_U3_EncReg<5> 
  2: DRV0HIGHr         15: R2flg             28: U3_U3_EncReg<6> 
  3: DRV0LOWr          16: R3clk             29: U3_U3_EncReg<7> 
  4: DRV1HIGHr         17: R3enable          30: U3_U4_EncReg<3> 
  5: DRV1LOWr          18: R3flg             31: U3_U4_EncReg<4> 
  6: DRV2HIGHr         19: U3_NET282         32: U3_U4_EncReg<5> 
  7: DRV2LOWr          20: U3_U1/CEr         33: U3_U4_EncReg<6> 
  8: DRV3HIGHr         21: U3_U1/SS          34: U3_U4_EncReg<7> 
  9: DRV3LOWr          22: U3_U2_EncReg<4>   35: U3_U5_EncReg<4> 
 10: DRVSTATr          23: U3_U2_EncReg<5>   36: U3_U5_EncReg<5> 
 11: N_PZ_579          24: U3_U2_EncReg<6>   37: U3_U5_EncReg<6> 
 12: R0flg             25: U3_U2_EncReg<7>   38: U3_U5_EncReg<7> 
 13: R1flg             26: U3_U3_EncReg<4>  

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
AD<4>             .XXXXXXXXX.X.........X...X....X...X..... 14      14
AD<5>             .XXXXXXXXX..X.........X...X....X...X.... 14      14
AD<6>             .XXXXXXXXX....X........X...X....X...X... 14      14
AD<7>             .XXXXXXXXX.......X......X...X....X...X.. 14      14
N_PZ_580          X...............X.X..................... 3       3
N_PZ_579          X............X....X..................... 3       3
U3_U4_EncReg<4>   X.........X..X....X..........XX......... 6       6
U3_U4_EncReg<7>   X.........X..X....X.............XX...... 6       6
U3_U4_EncReg<6>   X.........X..X....X............XX....... 6       6
U3_U4_EncReg<5>   X.........X..X....X...........XX........ 6       6
R3clk             X..............XX..XX................... 5       5
R2clk             .............X.X........................ 2       2
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  23
Number of function block inputs used/remaining:               23/17
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   39/9
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
DRV1LOWr                            1    FB3_1           (b)   (b)
DRV1HIGHr                           1    FB3_2           (b)   (b)
DRV0LOWr                            1    FB3_3           (b)   (b)
U1_ASedge                           0    FB3_4      90   I/O     I
DRV3HIGHr                           1    FB3_5      89   I/O     I
DRV0HIGHr                           1    FB3_6           (b)   (b)
U1_ADDR_reg<4>                      6    FB3_7           (b)   (b)
U1_ADDR_reg<3>                      5    FB3_8           (b)   (b)
U1_ADDR_reg<1>                      5    FB3_9           (b)   (b)
U1_ADDR_reg<2>                      4    FB3_10          (b)   (b)
U1_ADDR_reg<0>                      5    FB3_11          (b)   (b)
U1_ADDR_reg<5>                      3    FB3_12          (b)   (b)
U1_AutoInc                          2    FB3_13          (b)   (b)
DRV2LOWr                            1    FB3_14     88   I/O     I
U1_WRRDedge                         1    FB3_15          (b)   (b)
DRV2HIGHr                           1    FB3_16     87   I/O     I

Signals Used by Logic in Function Block
  1: AD<0>.PIN          9: N_PZ_581          17: U1_ADDR_reg<5> 
  2: AD<1>.PIN         10: N_PZ_628          18: U1_ADDR_reg<6> 
  3: AD<2>.PIN         11: RD                19: U1_ADDR_reg<7> 
  4: AD<3>.PIN         12: U1_ADDR_reg<0>    20: U1_ASedge 
  5: AD<4>.PIN         13: U1_ADDR_reg<1>    21: U1_AutoInc 
  6: AD<5>.PIN         14: U1_ADDR_reg<2>    22: U1_WRRDedge 
  7: AS                15: U1_ADDR_reg<3>    23: WR 
  8: BUSReset          16: U1_ADDR_reg<4>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
DRV1LOWr          ..........XXXXXXXXX...X................. 10      10
DRV1HIGHr         ..........XXXXXXXXX...X................. 10      10
DRV0LOWr          ..........XXXXXXXXX...X................. 10      10
DRV3HIGHr         ..........XXXXXXXXX...X................. 10      10
DRV0HIGHr         ..........XXXXXXXXX...X................. 10      10
U1_ADDR_reg<4>    ....X.XXXX.XXXXXXXXXX................... 15      15
U1_ADDR_reg<3>    ...X..XXXX.XXXXXXXXXX................... 15      15
U1_ADDR_reg<1>    .X....XXXX.XXXXXXXXXX................... 15      15
U1_ADDR_reg<2>    ..X...XXXX.XXXXXXXXXX................... 15      15
U1_ADDR_reg<0>    X.....XXXX.X.XXXXXXXX................... 14      14
U1_ADDR_reg<5>    .....XXXX.......X..X.................... 6       6
U1_AutoInc        ......X.X............X.................. 3       3
DRV2LOWr          ..........XXXXXXXXX...X................. 10      10
U1_WRRDedge       ........X............................... 1       1
DRV2HIGHr         ..........XXXXXXXXX...X................. 10      10
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  23
Number of function block inputs used/remaining:               23/17
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   37/11
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
U3_U1/DAVr                          4    FB4_1           (b)   (b)
U3_U3_EncReg<3>                     2    FB4_2     106   I/O     I
R1clk                               2    FB4_3     107   I/O     O
U3_U1/SS                            4    FB4_4           (b)   (b)
Motor_Power_n                       3    FB4_5     111   I/O     O
U3_U3_EncReg<2>                     2    FB4_6           (b)   (b)
U3_U3_EncReg<1>                     2    FB4_7           (b)   (b)
U3_U3_EncReg<0>                     2    FB4_8           (b)   (b)
U3_U1/BitCounter<0>                 2    FB4_9           (b)   (b)
U3_U1/BitCounter<1>                 2    FB4_10          (b)   (b)
U3_U1/BitCounter<2>                 3    FB4_11          (b)   (b)
U3_U1/BitCounter<3>                 3    FB4_12          (b)   (b)
Motor4_Phase_B_LIN                  2    FB4_13    112   I/O     O
Motor4_Phase_B_HIN                  1    FB4_14    113   I/O     O
Motor4_Phase_A_LIN                  2    FB4_15    114   I/O     O
Motor4_Phase_A_HIN                  1    FB4_16    116   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN          9: R1enable          17: U3_U1/SS 
  2: AD<2>.PIN         10: R3clk             18: U3_U3_EncReg<0> 
  3: BUSReset          11: U3_NET282         19: U3_U3_EncReg<1> 
  4: DRVCTLw           12: U3_U1/BitCounter<0> 
                                             20: U3_U3_EncReg<2> 
  5: GPIO8             13: U3_U1/BitCounter<1> 
                                             21: U3_U3_EncReg<3> 
  6: Motor_Power_n     14: U3_U1/BitCounter<2> 
                                             22: U4/M30 
  7: N_PZ_578          15: U3_U1/BitCounter<3> 
                                             23: U4/M31 
  8: R1data            16: U3_U1/DAVr       

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
U3_U1/DAVr        X.XX.....X.XXXXX........................ 9       9
U3_U3_EncReg<3>   ..X...X.X.X........XX................... 6       6
R1clk             ........XX.............................. 2       2
U3_U1/SS          X.XX.....X.XXXX.X....................... 9       9
Motor_Power_n     .XXX.X.................................. 4       4
U3_U3_EncReg<2>   ..X...X.X.X.......XX.................... 6       6
U3_U3_EncReg<1>   ..X...X.X.X......XX..................... 6       6
U3_U3_EncReg<0>   ..X...XXX.X......X...................... 6       6
U3_U1/BitCounter<0> 
                  ..X.......XX....X....................... 4       4
U3_U1/BitCounter<1> 
                  ..X.......XXX...X....................... 5       5
U3_U1/BitCounter<2> 
                  ..X.......XXXX..X....................... 6       6
U3_U1/BitCounter<3> 
                  ..X.......XXXXX.X....................... 7       7
Motor4_Phase_B_LIN 
                  ....X................XX................. 3       3
Motor4_Phase_B_HIN 
                  ....X................XX................. 3       3
Motor4_Phase_A_LIN 
                  ....X................XX................. 3       3
Motor4_Phase_A_HIN 
                  ....X................XX................. 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block:  38
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   40/8
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB5_1           (b)      
N_PZ_1048                          24    FB5_2      86TCK/I/O   (b)
(unused)                            0    FB5_3           (b)      
(unused)                            0    FB5_4           (b)      
U3_U2_EncReg<6>                     2    FB5_5           (b)   (b)
(unused)                            0    FB5_6           (b)      
(unused)                            0    FB5_7           (b)      
(unused)                            0    FB5_8           (b)      
(unused)                            0    FB5_9           (b)      
N_PZ_578                            2    FB5_10          (b)   (b)
U3_U3_EncReg<4>                     2    FB5_11          (b)   (b)
U3_U3_EncReg<7>                     2    FB5_12          (b)   (b)
U3_U3_EncReg<6>                     2    FB5_13          (b)   (b)
U3_U2_EncReg<7>                     2    FB5_14          (b)   (b)
U3_U2_EncReg<8>                     2    FB5_15          (b)   (b)
U3_U3_EncReg<5>                     2    FB5_16          (b)   (b)

Signals Used by Logic in Function Block
  1: BUSReset          14: R0flg             27: U3_U3_EncReg<5> 
  2: DRV0HIGHr         15: R1enable          28: U3_U3_EncReg<6> 
  3: DRV0LOWr          16: R1flg             29: U3_U3_EncReg<7> 
  4: DRV1HIGHr         17: R2flg             30: U3_U4_EncReg<4> 
  5: DRV1LOWr          18: R3flg             31: U3_U4_EncReg<5> 
  6: DRV2HIGHr         19: U3_NET282         32: U3_U4_EncReg<6> 
  7: DRV2LOWr          20: U3_U2_EncReg<4>   33: U3_U4_EncReg<7> 
  8: DRV3HIGHr         21: U3_U2_EncReg<5>   34: U3_U5_EncReg<4> 
  9: DRV3LOWr          22: U3_U2_EncReg<6>   35: U3_U5_EncReg<5> 
 10: DRVSTATr          23: U3_U2_EncReg<7>   36: U3_U5_EncReg<6> 
 11: N_PZ_577          24: U3_U2_EncReg<8>   37: U3_U5_EncReg<7> 
 12: N_PZ_578          25: U3_U3_EncReg<3>   38: U3_U6_PWRflgier 
 13: R0enable          26: U3_U3_EncReg<4>  

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
N_PZ_1048         .XXXXXXXXX...X.XXX.XXXX..XXXXXXXXXXXXX.. 30      30
U3_U2_EncReg<6>   X.........X.X.....X.XX.................. 6       6
N_PZ_578          X.............X...X..................... 3       3
U3_U3_EncReg<4>   X..........X..X...X.....XX.............. 6       6
U3_U3_EncReg<7>   X..........X..X...X........XX........... 6       6
U3_U3_EncReg<6>   X..........X..X...X.......XX............ 6       6
U3_U2_EncReg<7>   X.........X.X.....X..XX................. 6       6
U3_U2_EncReg<8>   X.........X.X.....X...XX................ 6       6
U3_U3_EncReg<5>   X..........X..X...X......XX............. 6       6
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block:  30
Number of function block inputs used/remaining:               30/10
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   34/14
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
U1_ADDR_reg<6>                      3    FB6_1      67   I/O     I
U4/M30                              2    FB6_2           (b)   (b)
U4/M21                              2    FB6_3           (b)   (b)
U4/M20                              2    FB6_4           (b)   (b)
U4/M11                              2    FB6_5           (b)   (b)
U4/M10                              2    FB6_6           (b)   (b)
U4/M00                              2    FB6_7           (b)   (b)
U4/M01                              2    FB6_8           (b)   (b)
U3_U6_PWRflgier                     2    FB6_9           (b)   (b)
U3_U1/divider<3>                    1    FB6_10          (b)   (b)
U3_NET282                           3    FB6_11          (b)   (b)
U3_U1/CEr                           3    FB6_12          (b)   (b)
U3_U1/divider<1>                    3    FB6_13          (b)   (b)
U3_U1/divider<0>                    2    FB6_14          (b)   (b)
U3_U1/divider<2>                    1    FB6_15          (b)   (b)
U4/M31                              2    FB6_16     69   I/O     I

Signals Used by Logic in Function Block
  1: AD<0>.PIN         11: DRVCTLw           21: U3_U1/divider<3> 
  2: AD<1>.PIN         12: DRVMTRCTLw        22: U3_U6_PWRflgier 
  3: AD<2>.PIN         13: N_PZ_581          23: U4/M00 
  4: AD<3>.PIN         14: R3clk             24: U4/M01 
  5: AD<4>.PIN         15: U1_ADDR_reg<6>    25: U4/M10 
  6: AD<5>.PIN         16: U1_ASedge         26: U4/M11 
  7: AD<6>.PIN         17: U3_U1/SS          27: U4/M20 
  8: AD<7>.PIN         18: U3_U1/divider<0>  28: U4/M21 
  9: AS                19: U3_U1/divider<1>  29: U4/M30 
 10: BUSReset          20: U3_U1/divider<2>  30: U4/M31 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
U1_ADDR_reg<6>    ......X.XX..X.XX........................ 6       6
U4/M30            ......X..X.X................X........... 4       4
U4/M21            .....X...X.X...............X............ 4       4
U4/M20            ....X....X.X..............X............. 4       4
U4/M11            ...X.....X.X.............X.............. 4       4
U4/M10            ..X......X.X............X............... 4       4
U4/M00            X........X.X..........X................. 4       4
U4/M01            .X.......X.X...........X................ 4       4
U3_U6_PWRflgier   .X.......XX..........X.................. 4       4
U3_U1/divider<3>  .........X......X...X................... 3       3
U3_NET282         .........X...X...XXXX................... 6       6
U3_U1/CEr         .........X.......XXXX................... 5       5
U3_U1/divider<1>  .........X......XXXXX................... 6       6
U3_U1/divider<0>  .........X......XX.XX................... 5       5
U3_U1/divider<2>  .........X......X..X.................... 3       3
U4/M31            .......X.X.X.................X.......... 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block:  32
Number of function block inputs used/remaining:               32/8
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   33/15
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
U3_U3_EncReg<8>                     2    FB7_1           (b)   (b)
U1_ADDR_reg<7>                      3    FB7_2      79   I/O     I
U3_U4_EncReg<0>                     2    FB7_3           (b)   (b)
U3_U4_EncReg<1>                     2    FB7_4           (b)   (b)
U3_U5_EncReg<8>                     2    FB7_5           (b)   (b)
U3_U5_EncReg<7>                     2    FB7_6           (b)   (b)
U3_U5_EncReg<6>                     2    FB7_7           (b)   (b)
U3_U5_EncReg<5>                     2    FB7_8           (b)   (b)
U3_U5_EncReg<4>                     2    FB7_9           (b)   (b)
U3_U5_EncReg<3>                     2    FB7_10          (b)   (b)
U3_U5_EncReg<2>                     2    FB7_11          (b)   (b)
U3_U5_EncReg<1>                     2    FB7_12          (b)   (b)
U3_U5_EncReg<0>                     2    FB7_13          (b)   (b)
U3_U4_EncReg<8>                     2    FB7_14          (b)   (b)
U3_U4_EncReg<2>                     2    FB7_15          (b)   (b)
U3_U4_EncReg<3>                     2    FB7_16          (b)   (b)

Signals Used by Logic in Function Block
  1: AD<7>.PIN         12: R3enable          23: U3_U4_EncReg<8> 
  2: AS                13: U1_ADDR_reg<7>    24: U3_U5_EncReg<0> 
  3: BUSReset          14: U1_ASedge         25: U3_U5_EncReg<1> 
  4: N_PZ_578          15: U3_NET282         26: U3_U5_EncReg<2> 
  5: N_PZ_579          16: U3_U3_EncReg<7>   27: U3_U5_EncReg<3> 
  6: N_PZ_580          17: U3_U3_EncReg<8>   28: U3_U5_EncReg<4> 
  7: N_PZ_581          18: U3_U4_EncReg<0>   29: U3_U5_EncReg<5> 
  8: R1enable          19: U3_U4_EncReg<1>   30: U3_U5_EncReg<6> 
  9: R2data            20: U3_U4_EncReg<2>   31: U3_U5_EncReg<7> 
 10: R2enable          21: U3_U4_EncReg<3>   32: U3_U5_EncReg<8> 
 11: R3data            22: U3_U4_EncReg<7>  

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
U3_U3_EncReg<8>   ..XX...X......XXX....................... 6       6
U1_ADDR_reg<7>    XXX...X.....XX.......................... 6       6
U3_U4_EncReg<0>   ..X.X...XX....X..X...................... 6       6
U3_U4_EncReg<1>   ..X.X....X....X..XX..................... 6       6
U3_U5_EncReg<8>   ..X..X.....X..X...............XX........ 6       6
U3_U5_EncReg<7>   ..X..X.....X..X..............XX......... 6       6
U3_U5_EncReg<6>   ..X..X.....X..X.............XX.......... 6       6
U3_U5_EncReg<5>   ..X..X.....X..X............XX........... 6       6
U3_U5_EncReg<4>   ..X..X.....X..X...........XX............ 6       6
U3_U5_EncReg<3>   ..X..X.....X..X..........XX............. 6       6
U3_U5_EncReg<2>   ..X..X.....X..X.........XX.............. 6       6
U3_U5_EncReg<1>   ..X..X.....X..X........XX............... 6       6
U3_U5_EncReg<0>   ..X..X....XX..X........X................ 6       6
U3_U4_EncReg<8>   ..X.X....X....X......XX................. 6       6
U3_U4_EncReg<2>   ..X.X....X....X...XX.................... 6       6
U3_U4_EncReg<3>   ..X.X....X....X....XX................... 6       6
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block:  20
Number of function block inputs used/remaining:               20/20
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   16/32
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
N_PZ_581                            1    FB8_1           (b)   (b)
R0enable                            3    FB8_2      71   I/O     O
R1enable                            3    FB8_3      72   I/O     O
(unused)                            0    FB8_4           (b)      
(unused)                            0    FB8_5           (b)      
(unused)                            0    FB8_6           (b)      
(unused)                            0    FB8_7           (b)      
DRVVALV1w                           1    FB8_8           (b)   (b)
DRVVALV0w                           1    FB8_9           (b)   (b)
DRVSTATr                            1    FB8_10          (b)   (b)
DRVMTRCTLw                          1    FB8_11          (b)   (b)
DRVCTLw                             1    FB8_12          (b)   (b)
DRV3LOWr                            1    FB8_13          (b)   (b)
U1_Enable_AD                        2    FB8_14          (b)   (b)
N_PZ_628                            2    FB8_15          (b)   (b)
BusINT                              1    FB8_16     74   I/O     O

Signals Used by Logic in Function Block
  1: AD<4>.PIN          8: R1enable          15: U1_ADDR_reg<5> 
  2: AD<5>.PIN          9: RD                16: U1_ADDR_reg<6> 
  3: AS                10: U1_ADDR_reg<0>    17: U1_ADDR_reg<7> 
  4: BUSReset          11: U1_ADDR_reg<1>    18: U1_ASedge 
  5: DRVCTLw           12: U1_ADDR_reg<2>    19: U1_WRRDedge 
  6: N_PZ_1048         13: U1_ADDR_reg<3>    20: WR 
  7: R0enable          14: U1_ADDR_reg<4>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
N_PZ_581          ........X..........X.................... 2       2
R0enable          X..XX.X................................. 4       4
R1enable          .X.XX..X................................ 4       4
DRVVALV1w         ........XXXXXXXXX..X.................... 10      10
DRVVALV0w         ........XXXXXXXXX..X.................... 10      10
DRVSTATr          ........XXXXXXXXX..X.................... 10      10
DRVMTRCTLw        ........XXXXXXXXX..X.................... 10      10
DRVCTLw           ........XXXXXXXXX..X.................... 10      10
DRV3LOWr          ........XXXXXXXXX..X.................... 10      10
U1_Enable_AD      ........X..XXXXXX..X.................... 8       8
N_PZ_628          ..X.....X........XXX.................... 5       5
BusINT            .....X.................................. 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB9 ***********************************
Number of signals used by logic mapping into function block:  3
Number of function block inputs used/remaining:               3/37
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   1/47
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB9_1     122   I/O      
(unused)                            0    FB9_2           (b)      
(unused)                            0    FB9_3     121TDO/I/O      
(unused)                            0    FB9_4           (b)      
Motor3_Phase_A_HIN                  1    FB9_5     120   I/O     O
(unused)                            0    FB9_6           (b)      
(unused)                            0    FB9_7           (b)      
(unused)                            0    FB9_8           (b)      
(unused)                            0    FB9_9           (b)      
(unused)                            0    FB9_10          (b)      
(unused)                            0    FB9_11          (b)      
(unused)                            0    FB9_12          (b)      
(unused)                            0    FB9_13          (b)      
(unused)                            0    FB9_14          (b)      
(unused)                            0    FB9_15          (b)      
(unused)                            0    FB9_16          (b)      

Signals Used by Logic in Function Block
  1: GPIO8              2: U4/M20             3: U4/M21 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
Motor3_Phase_A_HIN 
                  XXX..................................... 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB10 ***********************************
Number of signals used by logic mapping into function block:  3
Number of function block inputs used/remaining:               3/37
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB10_1          (b)      
(unused)                            0    FB10_2          (b)      
(unused)                            0    FB10_3    131TDI/I/O      
Motor2_Phase_B_LIN                  2    FB10_4    132   I/O     O
(unused)                            0    FB10_5          (b)      
(unused)                            0    FB10_6          (b)      
(unused)                            0    FB10_7          (b)      
(unused)                            0    FB10_8          (b)      
(unused)                            0    FB10_9          (b)      
(unused)                            0    FB10_10         (b)      
(unused)                            0    FB10_11         (b)      
(unused)                            0    FB10_12         (b)      
(unused)                            0    FB10_13         (b)      
(unused)                            0    FB10_14         (b)      
Motor2_Phase_B_HIN                  1    FB10_15   133   I/O     O
Motor2_Phase_A_LIN                  2    FB10_16   134   I/O     O

Signals Used by Logic in Function Block
  1: GPIO8              2: U4/M10             3: U4/M11 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
Motor2_Phase_B_LIN 
                  XXX..................................... 3       3
Motor2_Phase_B_HIN 
                  XXX..................................... 3       3
Motor2_Phase_A_LIN 
                  XXX..................................... 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB11 ***********************************
Number of signals used by logic mapping into function block:  3
Number of function block inputs used/remaining:               3/37
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB11_1          (b)      
(unused)                            0    FB11_2          (b)      
(unused)                            0    FB11_3          (b)      
(unused)                            0    FB11_4          (b)      
Motor3_Phase_B_LIN                  2    FB11_5    117   I/O     O
(unused)                            0    FB11_6          (b)      
(unused)                            0    FB11_7          (b)      
(unused)                            0    FB11_8          (b)      
(unused)                            0    FB11_9          (b)      
(unused)                            0    FB11_10         (b)      
(unused)                            0    FB11_11         (b)      
(unused)                            0    FB11_12         (b)      
(unused)                            0    FB11_13         (b)      
(unused)                            0    FB11_14         (b)      
Motor3_Phase_B_HIN                  1    FB11_15   118   I/O     O
Motor3_Phase_A_LIN                  2    FB11_16   119   I/O     O

Signals Used by Logic in Function Block
  1: GPIO8              2: U4/M20             3: U4/M21 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
Motor3_Phase_B_LIN 
                  XXX..................................... 3       3
Motor3_Phase_B_HIN 
                  XXX..................................... 3       3
Motor3_Phase_A_LIN 
                  XXX..................................... 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB12 ***********************************
Number of signals used by logic mapping into function block:  5
Number of function block inputs used/remaining:               5/35
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   6/42
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
Motor1_Phase_A_LIN                  2    FB12_1    139   I/O     O
(unused)                            0    FB12_2          (b)      
Motor1_Phase_B_HIN                  1    FB12_3    138   I/O     O
Motor1_Phase_B_LIN                  2    FB12_4    137   I/O     O
(unused)                            0    FB12_5          (b)      
(unused)                            0    FB12_6          (b)      
(unused)                            0    FB12_7          (b)      
(unused)                            0    FB12_8          (b)      
(unused)                            0    FB12_9          (b)      
(unused)                            0    FB12_10         (b)      
(unused)                            0    FB12_11         (b)      
(unused)                            0    FB12_12         (b)      
Motor2_Phase_A_HIN                  1    FB12_13   136   I/O     O
(unused)                            0    FB12_14         (b)      
(unused)                            0    FB12_15         (b)      
(unused)                            0    FB12_16         (b)      

Signals Used by Logic in Function Block
  1: GPIO8              3: U4/M01             5: U4/M11 
  2: U4/M00             4: U4/M10           

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
Motor1_Phase_A_LIN 
                  XXX..................................... 3       3
Motor1_Phase_B_HIN 
                  XXX..................................... 3       3
Motor1_Phase_B_LIN 
                  XXX..................................... 3       3
Motor2_Phase_A_HIN 
                  X..XX................................... 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB13 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB13_1     61   I/O     I
(unused)                            0    FB13_2          (b)      
(unused)                            0    FB13_3     62   I/O     I
(unused)                            0    FB13_4          (b)      
(unused)                            0    FB13_5          (b)      
(unused)                            0    FB13_6          (b)      
(unused)                            0    FB13_7          (b)      
(unused)                            0    FB13_8          (b)      
(unused)                            0    FB13_9          (b)      
(unused)                            0    FB13_10         (b)      
(unused)                            0    FB13_11         (b)      
(unused)                            0    FB13_12         (b)      
(unused)                            0    FB13_13         (b)      
(unused)                            0    FB13_14    65   I/O     I
(unused)                            0    FB13_15         (b)      
(unused)                            0    FB13_16    66   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB14 ***********************************
Number of signals used by logic mapping into function block:  6
Number of function block inputs used/remaining:               6/34
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   4/44
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB14_1          (b)      
AS0                                 0    FB14_2     47   I/O     O
Current_enable                      0    FB14_3     46   I/O     O
(unused)                            0    FB14_4          (b)      
(unused)                            0    FB14_5          (b)      
(unused)                            0    FB14_6          (b)      
(unused)                            0    FB14_7          (b)      
(unused)                            0    FB14_8          (b)      
(unused)                            0    FB14_9          (b)      
(unused)                            0    FB14_10         (b)      
(unused)                            0    FB14_11         (b)      
(unused)                            0    FB14_12         (b)      
(unused)                            0    FB14_13         (b)      
R3enable                            3    FB14_14    44   I/O     O
(unused)                            0    FB14_15         (b)      
R2enable                            3    FB14_16    43   I/O     O

Signals Used by Logic in Function Block
  1: AD<6>.PIN          3: BUSReset           5: R2enable 
  2: AD<7>.PIN          4: DRVCTLw            6: R3enable 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
AS0               ........................................ 0       0
Current_enable    ........................................ 0       0
R3enable          .XXX.X.................................. 4       4
R2enable          X.XXX................................... 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB15 ***********************************
Number of signals used by logic mapping into function block:  2
Number of function block inputs used/remaining:               2/38
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   2/46
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB15_1          (b)      
(unused)                            0    FB15_2          (b)      
R0clk                               2    FB15_3     60   I/O     O
(unused)                            0    FB15_4          (b)      
(unused)                            0    FB15_5     56   I/O      
(unused)                            0    FB15_6          (b)      
(unused)                            0    FB15_7          (b)      
(unused)                            0    FB15_8          (b)      
(unused)                            0    FB15_9          (b)      
(unused)                            0    FB15_10         (b)      
(unused)                            0    FB15_11         (b)      
(unused)                            0    FB15_12         (b)      
(unused)                            0    FB15_13         (b)      
(unused)                            0    FB15_14         (b)      
(unused)                            0    FB15_15         (b)      
(unused)                            0    FB15_16         (b)      

Signals Used by Logic in Function Block
  1: R0enable           2: R3clk            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
R0clk             XX...................................... 2       2
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB16 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB16_1          (b)      
AS1                                 0    FB16_2     48   I/O     O
(unused)                            0    FB16_3          (b)      
AS2                                 0    FB16_4     49   I/O     O
(unused)                            0    FB16_5          (b)      
(unused)                            0    FB16_6          (b)      
(unused)                            0    FB16_7          (b)      
(unused)                            0    FB16_8          (b)      
(unused)                            0    FB16_9          (b)      
(unused)                            0    FB16_10         (b)      
(unused)                            0    FB16_11         (b)      
(unused)                            0    FB16_12         (b)      
(unused)                            0    FB16_13         (b)      
(unused)                            0    FB16_14         (b)      
(unused)                            0    FB16_15         (b)      
(unused)                            0    FB16_16         (b)      

Signals Used by Logic in Function Block

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
AS1               ........................................ 0       0
AS2               ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB17 ***********************************
Number of signals used by logic mapping into function block:  13
Number of function block inputs used/remaining:               13/27
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   17/31
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB17_1          (b)      
(unused)                            0    FB17_2          (b)      
PhaseB_High_7                       4    FB17_3      6   I/O     O
PhaseB_Low_7                        4    FB17_4      5   I/O     O
PhaseA_High_8                       4    FB17_5      4   I/O     O
(unused)                            0    FB17_6          (b)      
(unused)                            0    FB17_7          (b)      
(unused)                            0    FB17_8          (b)      
(unused)                            0    FB17_9          (b)      
(unused)                            0    FB17_10         (b)      
(unused)                            0    FB17_11         (b)      
(unused)                            0    FB17_12         (b)      
(unused)                            0    FB17_13         (b)      
(unused)                            0    FB17_14         (b)      
PhaseA_Low_8                        4    FB17_15     2   I/O     O
PhaseB_High_8                       4    FB17_16     1   I/O     O

Signals Used by Logic in Function Block
  1: AD<4>.PIN          6: DRVVALV0w         10: PhaseB_High_7 
  2: AD<5>.PIN          7: DRVVALV1w         11: PhaseB_High_8 
  3: AD<6>.PIN          8: PhaseA_High_8     12: PhaseB_Low_7 
  4: AD<7>.PIN          9: PhaseA_Low_8      13: PhaseB_Low_8 
  5: BUSReset         

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PhaseB_High_7     XX..XXX..X.X............................ 7       7
PhaseB_Low_7      XX..XXX..X.X............................ 7       7
PhaseA_High_8     ..XXXXXX..X.X........................... 8       8
PhaseA_Low_8      ..XXXXX.X.X.X........................... 8       8
PhaseB_High_8     ..XXXXX...X.X........................... 7       7
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB18 ***********************************
Number of signals used by logic mapping into function block:  15
Number of function block inputs used/remaining:               15/25
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   18/30
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
PhaseA_Low_7                        4    FB18_1      7   I/O     O
PhaseA_High_7                       4    FB18_2      8   I/O     O
PhaseB_Low_6                        4    FB18_3      9   I/O     O
PhaseB_High_6                       4    FB18_4     10   I/O     O
(unused)                            0    FB18_5          (b)      
(unused)                            0    FB18_6          (b)      
(unused)                            0    FB18_7          (b)      
(unused)                            0    FB18_8          (b)      
(unused)                            0    FB18_9          (b)      
(unused)                            0    FB18_10         (b)      
(unused)                            0    FB18_11         (b)      
(unused)                            0    FB18_12         (b)      
(unused)                            0    FB18_13         (b)      
(unused)                            0    FB18_14         (b)      
PhaseA_Low_6                        4    FB18_15    11   I/O     O
PhaseA_High_6                       4    FB18_16    12   I/O     O

Signals Used by Logic in Function Block
  1: AD<2>.PIN          6: DRVVALV0w         11: PhaseA_Low_7 
  2: AD<3>.PIN          7: DRVVALV1w         12: PhaseB_High_6 
  3: AD<4>.PIN          8: PhaseA_High_6     13: PhaseB_High_7 
  4: AD<5>.PIN          9: PhaseA_High_7     14: PhaseB_Low_6 
  5: BUSReset          10: PhaseA_Low_6      15: PhaseB_Low_7 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PhaseA_Low_7      ..XXXXX...X.X.X......................... 8       8
PhaseA_High_7     ..XXXXX.X...X.X......................... 8       8
PhaseB_Low_6      XX..XXX....X.X.......................... 7       7
PhaseB_High_6     XX..XXX....X.X.......................... 7       7
PhaseA_Low_6      XX..XXX..X.X.X.......................... 8       8
PhaseA_High_6     XX..XXXX...X.X.......................... 8       8
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB19 ***********************************
Number of signals used by logic mapping into function block:  10
Number of function block inputs used/remaining:               10/30
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB19_1          (b)      
PhaseB_Low_8                        4    FB19_2    143   I/O     O
(unused)                            0    FB19_3          (b)      
(unused)                            0    FB19_4          (b)      
(unused)                            0    FB19_5          (b)      
(unused)                            0    FB19_6          (b)      
(unused)                            0    FB19_7          (b)      
(unused)                            0    FB19_8          (b)      
(unused)                            0    FB19_9          (b)      
(unused)                            0    FB19_10         (b)      
(unused)                            0    FB19_11         (b)      
(unused)                            0    FB19_12         (b)      
(unused)                            0    FB19_13         (b)      
(unused)                            0    FB19_14         (b)      
Motor1_Phase_A_HIN                  1    FB19_15   140   I/O     O
(unused)                            0    FB19_16         (b)      

Signals Used by Logic in Function Block
  1: AD<6>.PIN          5: DRVVALV1w          8: PhaseB_Low_8 
  2: AD<7>.PIN          6: GPIO8              9: U4/M00 
  3: BUSReset           7: PhaseB_High_8     10: U4/M01 
  4: DRVVALV0w        

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PhaseB_Low_8      XXXXX.XX................................ 7       7
Motor1_Phase_A_HIN 
                  .....X..XX.............................. 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB20 ***********************************
Number of signals used by logic mapping into function block:  9
Number of function block inputs used/remaining:               9/31
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   10/38
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
PhaseB_Low_5                        4    FB20_1     14   I/O     O
(unused)                            0    FB20_2          (b)      
(unused)                            0    FB20_3          (b)      
PhaseB_High_5                       4    FB20_4     15   I/O     O
(unused)                            0    FB20_5          (b)      
(unused)                            0    FB20_6          (b)      
(unused)                            0    FB20_7          (b)      
(unused)                            0    FB20_8          (b)      
(unused)                            0    FB20_9          (b)      
(unused)                            0    FB20_10         (b)      
(unused)                            0    FB20_11         (b)      
(unused)                            0    FB20_12         (b)      
(unused)                            0    FB20_13         (b)      
PhaseA_Low_5                        4    FB20_14    16   I/O     O
(unused)                            0    FB20_15         (b)      
PhaseA_High_5                       4    FB20_16    18   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN          4: DRVVALV0w          7: PhaseA_Low_5 
  2: AD<1>.PIN          5: DRVVALV1w          8: PhaseB_High_5 
  3: BUSReset           6: PhaseA_High_5      9: PhaseB_Low_5 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PhaseB_Low_5      XXXXX..XX............................... 7       7
PhaseB_High_5     XXXXX..XX............................... 7       7
PhaseA_Low_5      XXXXX.XXX............................... 8       8
PhaseA_High_5     XXXXXX.XX............................... 8       8
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB21 ***********************************
Number of signals used by logic mapping into function block:  11
Number of function block inputs used/remaining:               11/29
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   6/42
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB21_1          (b)      
(unused)                            0    FB21_2          (b)      
(unused)                            0    FB21_3          (b)      
(unused)                            0    FB21_4          (b)      
(unused)                            0    FB21_5          (b)      
(unused)                            0    FB21_6          (b)      
(unused)                            0    FB21_7          (b)      
(unused)                            0    FB21_8          (b)      
(unused)                            0    FB21_9          (b)      
(unused)                            0    FB21_10         (b)      
(unused)                            0    FB21_11         (b)      
(unused)                            0    FB21_12         (b)      
Motor_Power                         2    FB21_13    40   I/O     O
(unused)                            0    FB21_14         (b)      
(unused)                            0    FB21_15         (b)      
PhaseA_High_1                       4    FB21_16    37   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN          5: DRVCTLw            9: PhaseA_High_1 
  2: AD<1>.PIN          6: DRVVALV0w         10: PhaseB_High_1 
  3: AD<2>.PIN          7: DRVVALV1w         11: PhaseB_Low_1 
  4: BUSReset           8: Motor_Power      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
Motor_Power       ..XXX..X................................ 4       4
PhaseA_High_1     XX.X.XX.XXX............................. 8       8
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB22 ***********************************
Number of signals used by logic mapping into function block:  13
Number of function block inputs used/remaining:               13/27
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   15/33
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
PhaseB_Low_4                        3    FB22_1     19   I/O     O
(unused)                            0    FB22_2          (b)      
PhaseB_High_4                       3    FB22_3     20   I/O     O
PhaseA_Low_4                        4    FB22_4     21   I/O     O
(unused)                            0    FB22_5     22TMS/I/O      
(unused)                            0    FB22_6          (b)      
(unused)                            0    FB22_7          (b)      
(unused)                            0    FB22_8          (b)      
(unused)                            0    FB22_9          (b)      
(unused)                            0    FB22_10         (b)      
(unused)                            0    FB22_11         (b)      
(unused)                            0    FB22_12         (b)      
PhaseA_High_4                       4    FB22_13    23   I/O     O
(unused)                            0    FB22_14         (b)      
(unused)                            0    FB22_15         (b)      
PhaseB_Low_3                        3    FB22_16    25   I/O     O

Signals Used by Logic in Function Block
  1: AD<4>.PIN          6: DRVVALV0w         10: PhaseB_High_3 
  2: AD<5>.PIN          7: DRVVALV1w         11: PhaseB_High_4 
  3: AD<6>.PIN          8: PhaseA_High_4     12: PhaseB_Low_3 
  4: AD<7>.PIN          9: PhaseA_Low_4      13: PhaseB_Low_4 
  5: BUSReset         

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PhaseB_Low_4      ..XXXX....X.X........................... 6       6
PhaseB_High_4     ..XXXX....X.X........................... 6       6
PhaseA_Low_4      ..XXXXX.X.X.X........................... 8       8
PhaseA_High_4     ..XXXXXX..X.X........................... 8       8
PhaseB_Low_3      XX..XX...X.X............................ 6       6
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB23 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   6/42
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
PhaseA_Low_1                        4    FB23_1     36   I/O     O
(unused)                            0    FB23_2          (b)      
(unused)                            0    FB23_3          (b)      
(unused)                            0    FB23_4          (b)      
(unused)                            0    FB23_5          (b)      
(unused)                            0    FB23_6          (b)      
(unused)                            0    FB23_7          (b)      
(unused)                            0    FB23_8          (b)      
(unused)                            0    FB23_9          (b)      
(unused)                            0    FB23_10         (b)      
(unused)                            0    FB23_11         (b)      
(unused)                            0    FB23_12         (b)      
(unused)                            0    FB23_13         (b)      
PhaseB_High_1                       3    FB23_14    35   I/O     O
(unused)                            0    FB23_15         (b)      
(unused)                            0    FB23_16         (b)      

Signals Used by Logic in Function Block
  1: AD<0>.PIN          4: DRVVALV0w          7: PhaseB_High_1 
  2: AD<1>.PIN          5: DRVVALV1w          8: PhaseB_Low_1 
  3: BUSReset           6: PhaseA_Low_1     

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PhaseA_Low_1      XXXXXXXX................................ 8       8
PhaseB_High_1     XXXX..XX................................ 6       6
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB24 ***********************************
Number of signals used by logic mapping into function block:  19
Number of function block inputs used/remaining:               19/21
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   25/23
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
PhaseB_High_3                       3    FB24_1     26   I/O     O
PhaseA_Low_3                        4    FB24_2     27   I/O     O
PhaseA_High_3                       4    FB24_3     28   I/O     O
PhaseB_Low_2                        3    FB24_4     29   I/O     O
PhaseB_High_2                       3    FB24_5     30   I/O     O
(unused)                            0    FB24_6          (b)      
(unused)                            0    FB24_7          (b)      
(unused)                            0    FB24_8          (b)      
(unused)                            0    FB24_9          (b)      
(unused)                            0    FB24_10         (b)      
(unused)                            0    FB24_11         (b)      
(unused)                            0    FB24_12         (b)      
PhaseA_Low_2                        4    FB24_13    31   I/O     O
PhaseA_High_2                       4    FB24_14    32   I/O     O
(unused)                            0    FB24_15         (b)      
PhaseB_Low_1                        3    FB24_16    34   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN          8: DRVVALV0w         14: PhaseB_High_1 
  2: AD<1>.PIN          9: DRVVALV1w         15: PhaseB_High_2 
  3: AD<2>.PIN         10: PhaseA_High_2     16: PhaseB_High_3 
  4: AD<3>.PIN         11: PhaseA_High_3     17: PhaseB_Low_1 
  5: AD<4>.PIN         12: PhaseA_Low_2      18: PhaseB_Low_2 
  6: AD<5>.PIN         13: PhaseA_Low_3      19: PhaseB_Low_3 
  7: BUSReset         

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PhaseB_High_3     ....XXXX.......X..X..................... 6       6
PhaseA_Low_3      ....XXXXX...X..X..X..................... 8       8
PhaseA_High_3     ....XXXXX.X....X..X..................... 8       8
PhaseB_Low_2      ..XX..XX......X..X...................... 6       6
PhaseB_High_2     ..XX..XX......X..X...................... 6       6
PhaseA_Low_2      ..XX..XXX..X..X..X...................... 8       8
PhaseA_High_2     ..XX..XXXX....X..X...................... 8       8
PhaseB_Low_1      XX....XX.....X..X....................... 6       6
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.

!AD<0> = !U3_U1/DAVr * DRVSTATr
	# !U3_U2_EncReg<8> * DRV0HIGHr
	# !U3_U3_EncReg<8> * DRV1HIGHr
	# !U3_U4_EncReg<8> * DRV2HIGHr
	# !U3_U5_EncReg<8> * DRV3HIGHr
	# !U3_U2_EncReg<0> * !DRV0HIGHr * DRV0LOWr
	# !U3_U3_EncReg<0> * !DRV1HIGHr * DRV1LOWr
	# !U3_U4_EncReg<0> * !DRV2HIGHr * DRV2LOWr
	# !U3_U5_EncReg<0> * !DRV3HIGHr * DRV3LOWr;
    AD<0>.OE = U1_Enable_AD;

U3_U1/DAVr := U3_U1/DAVr * BUSReset * !AD<0>.PIN
	# U3_U1/DAVr * BUSReset * !DRVCTLw
	# R3clk * BUSReset * !AD<0>.PIN * 
	!U3_U1/BitCounter<0> * U3_U1/BitCounter<1> * !U3_U1/BitCounter<2> * 
	U3_U1/BitCounter<3>
	# R3clk * BUSReset * !U3_U1/BitCounter<0> * 
	U3_U1/BitCounter<1> * !U3_U1/BitCounter<2> * U3_U1/BitCounter<3> * 
	!DRVCTLw;
   U3_U1/DAVr.CLK  =  !Mclk;	// GCK

R3clk.T := !R3clk * !BUSReset
	# !R3clk * !U3_U1/SS
	# BUSReset * U3_U1/SS * U3_U1/CEr;
   !R3clk.OE = R3enable;
   R3clk.CLK  =  Mclk;	// GCK

!U3_U1/SS := !BUSReset
	# !U3_U1/SS * !AD<0>.PIN
	# !U3_U1/SS * !DRVCTLw
	# R3clk * !U3_U1/BitCounter<0> * 
	U3_U1/BitCounter<1> * !U3_U1/BitCounter<2> * U3_U1/BitCounter<3>;
   U3_U1/SS.CLK  =  !Mclk;	// GCK

U3_U1/BitCounter<0> := BUSReset * U3_U1/SS * U3_U1/BitCounter<0> * 
	!U3_NET282
	# BUSReset * U3_U1/SS * !U3_U1/BitCounter<0> * 
	U3_NET282;
   U3_U1/BitCounter<0>.CLK  =  Mclk;	// GCK

U3_NET282 := R3clk * BUSReset * U3_U1/divider<2>
	# R3clk * BUSReset * U3_U1/divider<3>
	# R3clk * BUSReset * U3_U1/divider<0> * 
	U3_U1/divider<1>;
   U3_NET282.CLK  =  !Mclk;	// GCK

U3_U1/divider<2> := BUSReset * !U3_U1/SS * U3_U1/divider<2>;
   U3_U1/divider<2>.CLK  =  Mclk;	// GCK

U3_U1/divider<0> := BUSReset * !U3_U1/SS * U3_U1/divider<0>
	# U3_U1/SS * !U3_U1/divider<2> * !U3_U1/divider<0> * 
	!U3_U1/divider<3>;
   U3_U1/divider<0>.CLK  =  Mclk;	// GCK

U3_U1/divider<3> := BUSReset * !U3_U1/SS * U3_U1/divider<3>;
   U3_U1/divider<3>.CLK  =  Mclk;	// GCK

U3_U1/divider<1> := BUSReset * !U3_U1/SS * U3_U1/divider<1>
	# U3_U1/SS * !U3_U1/divider<2> * U3_U1/divider<0> * 
	!U3_U1/divider<3> * !U3_U1/divider<1>
	# U3_U1/SS * !U3_U1/divider<2> * !U3_U1/divider<0> * 
	!U3_U1/divider<3> * U3_U1/divider<1>;
   U3_U1/divider<1>.CLK  =  Mclk;	// GCK

U3_U1/BitCounter<1> := BUSReset * U3_U1/SS * U3_U1/BitCounter<1>
	$ BUSReset * U3_U1/SS * U3_U1/BitCounter<0> * 
	U3_NET282;
   U3_U1/BitCounter<1>.CLK  =  Mclk;	// GCK

U3_U1/BitCounter<2>.T := !BUSReset * U3_U1/BitCounter<2>
	# !U3_U1/SS * U3_U1/BitCounter<2>
	# BUSReset * U3_U1/SS * U3_U1/BitCounter<0> * 
	U3_NET282 * U3_U1/BitCounter<1>;
   U3_U1/BitCounter<2>.CLK  =  Mclk;	// GCK

U3_U1/BitCounter<3>.T := !BUSReset * U3_U1/BitCounter<3>
	# !U3_U1/SS * U3_U1/BitCounter<3>
	# BUSReset * U3_U1/SS * U3_U1/BitCounter<0> * 
	U3_NET282 * U3_U1/BitCounter<1> * U3_U1/BitCounter<2>;
   U3_U1/BitCounter<3>.CLK  =  Mclk;	// GCK

DRVCTLw = RD * !WR * !U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	!U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

U1_ADDR_reg<0>.T := !BUSReset * U1_ADDR_reg<0>
	# !AD<0>.PIN * U1_ADDR_reg<0> * !AS * U1_ASedge * 
	N_PZ_581
	# BUSReset * AD<0>.PIN * !U1_ADDR_reg<0> * !AS * 
	U1_ASedge * N_PZ_581
	# BUSReset * !U1_ADDR_reg<2> * U1_ADDR_reg<4> * 
	!U1_ADDR_reg<5> * !U1_ADDR_reg<6> * !U1_ADDR_reg<7> * U1_AutoInc * 
	N_PZ_628
	# BUSReset * !U1_ADDR_reg<3> * U1_ADDR_reg<4> * 
	!U1_ADDR_reg<5> * !U1_ADDR_reg<6> * !U1_ADDR_reg<7> * U1_AutoInc * 
	N_PZ_628;
   U1_ADDR_reg<0>.CLK  =  !Mclk;	// GCK


// Fast Input Register
U1_ASedge := AS;
   U1_ASedge.CLK  =  !Mclk;	// GCK

N_PZ_581 = RD * WR;

U1_ADDR_reg<2>.T := !BUSReset * U1_ADDR_reg<2>
	# !AS * U1_ASedge * N_PZ_581 * U1_ADDR_reg<2> * 
	!AD<2>.PIN
	# BUSReset * !AS * U1_ASedge * N_PZ_581 * 
	!U1_ADDR_reg<2> * AD<2>.PIN
	# BUSReset * U1_ADDR_reg<0> * !U1_ADDR_reg<3> * 
	U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * U1_ADDR_reg<1> * 
	!U1_ADDR_reg<7> * U1_AutoInc * N_PZ_628;
   U1_ADDR_reg<2>.CLK  =  !Mclk;	// GCK

U1_ADDR_reg<3>.T := !BUSReset * U1_ADDR_reg<3>
	# !AS * U1_ASedge * N_PZ_581 * U1_ADDR_reg<3> * 
	!AD<3>.PIN
	# BUSReset * !AS * U1_ASedge * N_PZ_581 * 
	!U1_ADDR_reg<3> * AD<3>.PIN
	# U1_ADDR_reg<0> * !U1_ADDR_reg<2> * U1_ADDR_reg<3> * 
	U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * U1_ADDR_reg<1> * 
	!U1_ADDR_reg<7> * U1_AutoInc * N_PZ_628
	# BUSReset * U1_ADDR_reg<0> * U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	U1_ADDR_reg<1> * !U1_ADDR_reg<7> * U1_AutoInc * N_PZ_628;
   U1_ADDR_reg<3>.CLK  =  !Mclk;	// GCK

!U1_ADDR_reg<4> := !BUSReset
	# AS * !U1_ADDR_reg<4>
	# !U1_ASedge * !U1_ADDR_reg<4>
	# !N_PZ_581 * !U1_ADDR_reg<4>
	# !AS * U1_ASedge * N_PZ_581 * !AD<4>.PIN
	# U1_ADDR_reg<0> * !U1_ADDR_reg<2> * U1_ADDR_reg<3> * 
	!U1_ADDR_reg<5> * !U1_ADDR_reg<6> * U1_ADDR_reg<1> * !U1_ADDR_reg<7> * 
	U1_AutoInc * N_PZ_628;
   U1_ADDR_reg<4>.CLK  =  !Mclk;	// GCK

U1_ADDR_reg<5>.T := !BUSReset * U1_ADDR_reg<5>
	# !AS * U1_ASedge * N_PZ_581 * U1_ADDR_reg<5> * 
	!AD<5>.PIN
	# BUSReset * !AS * U1_ASedge * N_PZ_581 * 
	!U1_ADDR_reg<5> * AD<5>.PIN;
   U1_ADDR_reg<5>.CLK  =  !Mclk;	// GCK

U1_ADDR_reg<6>.T := !BUSReset * U1_ADDR_reg<6>
	# !AS * U1_ASedge * N_PZ_581 * U1_ADDR_reg<6> * 
	!AD<6>.PIN
	# BUSReset * !AS * U1_ASedge * N_PZ_581 * 
	!U1_ADDR_reg<6> * AD<6>.PIN;
   U1_ADDR_reg<6>.CLK  =  !Mclk;	// GCK

U1_ADDR_reg<1>.T := !BUSReset * U1_ADDR_reg<1>
	# !AS * U1_ASedge * N_PZ_581 * U1_ADDR_reg<1> * 
	!AD<1>.PIN
	# BUSReset * !AS * U1_ASedge * N_PZ_581 * 
	!U1_ADDR_reg<1> * AD<1>.PIN
	# BUSReset * U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * !U1_ADDR_reg<7> * 
	U1_AutoInc * N_PZ_628
	# BUSReset * U1_ADDR_reg<0> * !U1_ADDR_reg<3> * 
	U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * !U1_ADDR_reg<7> * 
	U1_AutoInc * N_PZ_628;
   U1_ADDR_reg<1>.CLK  =  !Mclk;	// GCK

U1_ADDR_reg<7>.T := !BUSReset * U1_ADDR_reg<7>
	# !AS * U1_ASedge * N_PZ_581 * U1_ADDR_reg<7> * 
	!AD<7>.PIN
	# BUSReset * !AS * U1_ASedge * N_PZ_581 * 
	!U1_ADDR_reg<7> * AD<7>.PIN;
   U1_ADDR_reg<7>.CLK  =  !Mclk;	// GCK

!U1_AutoInc := AS;
   U1_AutoInc.CLK  =  !Mclk;	// GCK
    U1_AutoInc.CE = !N_PZ_581 * U1_WRRDedge;

U1_WRRDedge := N_PZ_581;
   U1_WRRDedge.CLK  =  !Mclk;	// GCK

N_PZ_628 = RD * WR * AS * !U1_WRRDedge
	# RD * WR * !U1_ASedge * !U1_WRRDedge;

U3_U1/CEr := BUSReset * U3_U1/divider<2>
	# BUSReset * U3_U1/divider<3>
	# BUSReset * U3_U1/divider<0> * U3_U1/divider<1>;
   U3_U1/CEr.CLK  =  !Mclk;	// GCK

!R3enable := BUSReset * DRVCTLw * AD<7>.PIN
	# BUSReset * !DRVCTLw * !R3enable;
   R3enable.CLK  =  !Mclk;	// GCK

DRVSTATr = !RD * WR * !U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	!U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

U3_U2_EncReg<8> := U3_U2_EncReg<8> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<7>;
   U3_U2_EncReg<8>.CLK  =  Mclk;	// GCK

!R0enable := BUSReset * DRVCTLw * AD<4>.PIN
	# BUSReset * !DRVCTLw * !R0enable;
   R0enable.CLK  =  !Mclk;	// GCK

U3_U2_EncReg<7> := U3_U2_EncReg<7> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<6>;
   U3_U2_EncReg<7>.CLK  =  Mclk;	// GCK

U3_U2_EncReg<6> := U3_U2_EncReg<6> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<5>;
   U3_U2_EncReg<6>.CLK  =  Mclk;	// GCK

U3_U2_EncReg<5> := U3_U2_EncReg<5> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<4>;
   U3_U2_EncReg<5>.CLK  =  Mclk;	// GCK

U3_U2_EncReg<4> := U3_U2_EncReg<4> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<3>;
   U3_U2_EncReg<4>.CLK  =  Mclk;	// GCK

U3_U2_EncReg<3> := U3_U2_EncReg<3> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<2>;
   U3_U2_EncReg<3>.CLK  =  Mclk;	// GCK

U3_U2_EncReg<2> := U3_U2_EncReg<2> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<1>;
   U3_U2_EncReg<2>.CLK  =  Mclk;	// GCK

U3_U2_EncReg<1> := U3_U2_EncReg<1> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * 
	U3_U2_EncReg<0>;
   U3_U2_EncReg<1>.CLK  =  Mclk;	// GCK

U3_U2_EncReg<0> := U3_U2_EncReg<0> * N_PZ_577
	# BUSReset * U3_NET282 * !R0enable * R0data;
   U3_U2_EncReg<0>.CLK  =  Mclk;	// GCK

N_PZ_577 = BUSReset * !U3_NET282
	# BUSReset * R0enable;

DRV0HIGHr = !RD * WR * !U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

DRV0LOWr = !RD * WR * U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	!U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

U3_U3_EncReg<8> := U3_U3_EncReg<8> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<7>;
   U3_U3_EncReg<8>.CLK  =  Mclk;	// GCK

!R1enable := BUSReset * DRVCTLw * AD<5>.PIN
	# BUSReset * !DRVCTLw * !R1enable;
   R1enable.CLK  =  !Mclk;	// GCK

U3_U3_EncReg<7> := U3_U3_EncReg<7> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<6>;
   U3_U3_EncReg<7>.CLK  =  Mclk;	// GCK

U3_U3_EncReg<6> := U3_U3_EncReg<6> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<5>;
   U3_U3_EncReg<6>.CLK  =  Mclk;	// GCK

U3_U3_EncReg<5> := U3_U3_EncReg<5> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<4>;
   U3_U3_EncReg<5>.CLK  =  Mclk;	// GCK

U3_U3_EncReg<4> := U3_U3_EncReg<4> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<3>;
   U3_U3_EncReg<4>.CLK  =  Mclk;	// GCK

U3_U3_EncReg<3> := U3_U3_EncReg<3> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<2>;
   U3_U3_EncReg<3>.CLK  =  Mclk;	// GCK

U3_U3_EncReg<2> := U3_U3_EncReg<2> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<1>;
   U3_U3_EncReg<2>.CLK  =  Mclk;	// GCK

U3_U3_EncReg<1> := U3_U3_EncReg<1> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * 
	U3_U3_EncReg<0>;
   U3_U3_EncReg<1>.CLK  =  Mclk;	// GCK

U3_U3_EncReg<0> := U3_U3_EncReg<0> * N_PZ_578
	# BUSReset * U3_NET282 * !R1enable * R1data;
   U3_U3_EncReg<0>.CLK  =  Mclk;	// GCK

N_PZ_578 = BUSReset * !U3_NET282
	# BUSReset * R1enable;

DRV1HIGHr = !RD * WR * !U1_ADDR_reg<0> * U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	!U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

DRV1LOWr = !RD * WR * U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

U3_U4_EncReg<8> := U3_U4_EncReg<8> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<7>;
   U3_U4_EncReg<8>.CLK  =  Mclk;	// GCK

!R2enable := BUSReset * DRVCTLw * AD<6>.PIN
	# BUSReset * !DRVCTLw * !R2enable;
   R2enable.CLK  =  !Mclk;	// GCK

U3_U4_EncReg<7> := U3_U4_EncReg<7> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<6>;
   U3_U4_EncReg<7>.CLK  =  Mclk;	// GCK

U3_U4_EncReg<6> := U3_U4_EncReg<6> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<5>;
   U3_U4_EncReg<6>.CLK  =  Mclk;	// GCK

U3_U4_EncReg<5> := U3_U4_EncReg<5> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<4>;
   U3_U4_EncReg<5>.CLK  =  Mclk;	// GCK

U3_U4_EncReg<4> := U3_U4_EncReg<4> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<3>;
   U3_U4_EncReg<4>.CLK  =  Mclk;	// GCK

U3_U4_EncReg<3> := U3_U4_EncReg<3> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<2>;
   U3_U4_EncReg<3>.CLK  =  Mclk;	// GCK

U3_U4_EncReg<2> := U3_U4_EncReg<2> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<1>;
   U3_U4_EncReg<2>.CLK  =  Mclk;	// GCK

U3_U4_EncReg<1> := U3_U4_EncReg<1> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * 
	U3_U4_EncReg<0>;
   U3_U4_EncReg<1>.CLK  =  Mclk;	// GCK

U3_U4_EncReg<0> := U3_U4_EncReg<0> * N_PZ_579
	# BUSReset * U3_NET282 * !R2enable * R2data;
   U3_U4_EncReg<0>.CLK  =  Mclk;	// GCK

N_PZ_579 = BUSReset * !U3_NET282
	# BUSReset * R2enable;

DRV2HIGHr = !RD * WR * !U1_ADDR_reg<0> * U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

DRV2LOWr = !RD * WR * U1_ADDR_reg<0> * U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	!U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

U3_U5_EncReg<8> := U3_U5_EncReg<8> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<7>;
   U3_U5_EncReg<8>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<7> := U3_U5_EncReg<7> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<6>;
   U3_U5_EncReg<7>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<6> := U3_U5_EncReg<6> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<5>;
   U3_U5_EncReg<6>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<5> := U3_U5_EncReg<5> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<4>;
   U3_U5_EncReg<5>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<4> := U3_U5_EncReg<4> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<3>;
   U3_U5_EncReg<4>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<3> := U3_U5_EncReg<3> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<2>;
   U3_U5_EncReg<3>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<2> := U3_U5_EncReg<2> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<1>;
   U3_U5_EncReg<2>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<1> := U3_U5_EncReg<1> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * 
	U3_U5_EncReg<0>;
   U3_U5_EncReg<1>.CLK  =  Mclk;	// GCK

U3_U5_EncReg<0> := U3_U5_EncReg<0> * N_PZ_580
	# BUSReset * U3_NET282 * !R3enable * R3data;
   U3_U5_EncReg<0>.CLK  =  Mclk;	// GCK

N_PZ_580 = BUSReset * !U3_NET282
	# BUSReset * R3enable;

DRV3HIGHr = !RD * WR * !U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	!U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

DRV3LOWr = !RD * WR * U1_ADDR_reg<0> * U1_ADDR_reg<2> * 
	!U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

U1_Enable_AD = !RD * WR * !U1_ADDR_reg<2> * U1_ADDR_reg<4> * 
	!U1_ADDR_reg<5> * !U1_ADDR_reg<6> * !U1_ADDR_reg<7>
	# !RD * WR * !U1_ADDR_reg<3> * U1_ADDR_reg<4> * 
	!U1_ADDR_reg<5> * !U1_ADDR_reg<6> * !U1_ADDR_reg<7>;

!AD<1> = DRV0HIGHr
	# DRV1HIGHr
	# DRV2HIGHr
	# DRV3HIGHr
	# DRVSTATr * !U3_U6_PWRflgier
	# !U3_U2_EncReg<1> * DRV0LOWr
	# !U3_U3_EncReg<1> * DRV1LOWr
	# !U3_U4_EncReg<1> * DRV2LOWr
	# !U3_U5_EncReg<1> * DRV3LOWr;
    AD<1>.OE = U1_Enable_AD;

U3_U6_PWRflgier := BUSReset * DRVCTLw * AD<1>.PIN
	# BUSReset * !DRVCTLw * U3_U6_PWRflgier;
   U3_U6_PWRflgier.CLK  =  !Mclk;	// GCK

!AD<2> = DRVSTATr
	# DRV0HIGHr
	# DRV1HIGHr
	# DRV2HIGHr
	# DRV3HIGHr
	# !U3_U2_EncReg<2> * DRV0LOWr
	# !U3_U3_EncReg<2> * DRV1LOWr
	# !U3_U4_EncReg<2> * DRV2LOWr
	# !U3_U5_EncReg<2> * DRV3LOWr;
    AD<2>.OE = U1_Enable_AD;

!AD<3> = DRVSTATr
	# DRV0HIGHr
	# DRV1HIGHr
	# DRV2HIGHr
	# DRV3HIGHr
	# !U3_U2_EncReg<3> * DRV0LOWr
	# !U3_U3_EncReg<3> * DRV1LOWr
	# !U3_U4_EncReg<3> * DRV2LOWr
	# !U3_U5_EncReg<3> * DRV3LOWr;
    AD<3>.OE = U1_Enable_AD;

!AD<4> = DRV0HIGHr
	# DRV1HIGHr
	# DRV2HIGHr
	# DRV3HIGHr
	# DRVSTATr * !R0flg
	# !U3_U2_EncReg<4> * DRV0LOWr
	# !U3_U3_EncReg<4> * DRV1LOWr
	# !U3_U4_EncReg<4> * DRV2LOWr
	# !U3_U5_EncReg<4> * DRV3LOWr;
    AD<4>.OE = U1_Enable_AD;

!AD<5> = DRV0HIGHr
	# DRV1HIGHr
	# DRV2HIGHr
	# DRV3HIGHr
	# DRVSTATr * !R1flg
	# !U3_U2_EncReg<5> * DRV0LOWr
	# !U3_U3_EncReg<5> * DRV1LOWr
	# !U3_U4_EncReg<5> * DRV2LOWr
	# !U3_U5_EncReg<5> * DRV3LOWr;
    AD<5>.OE = U1_Enable_AD;

!AD<6> = DRV0HIGHr
	# DRV1HIGHr
	# DRV2HIGHr
	# DRV3HIGHr
	# DRVSTATr * !R2flg
	# !U3_U2_EncReg<6> * DRV0LOWr
	# !U3_U3_EncReg<6> * DRV1LOWr
	# !U3_U4_EncReg<6> * DRV2LOWr
	# !U3_U5_EncReg<6> * DRV3LOWr;
    AD<6>.OE = U1_Enable_AD;

!AD<7> = DRV0HIGHr
	# DRV1HIGHr
	# DRV2HIGHr
	# DRV3HIGHr
	# DRVSTATr * !R3flg
	# !U3_U2_EncReg<7> * DRV0LOWr
	# !U3_U3_EncReg<7> * DRV1LOWr
	# !U3_U4_EncReg<7> * DRV2LOWr
	# !U3_U5_EncReg<7> * DRV3LOWr;
    AD<7>.OE = U1_Enable_AD;

AS0 = Gnd;

AS1 = Gnd;

AS2 = Gnd;

BusINT = Gnd;
    BusINT.OE = N_PZ_1048;

N_PZ_1048 = DRV0HIGHr * U3_U6_PWRflgier
	# DRV1HIGHr * U3_U6_PWRflgier
	# DRV2HIGHr * U3_U6_PWRflgier
	# DRV3HIGHr * U3_U6_PWRflgier
	# DRVSTATr * U3_U6_PWRflgier * !R0flg
	# DRVSTATr * U3_U6_PWRflgier * !R1flg
	# DRVSTATr * U3_U6_PWRflgier * !R2flg
	# DRVSTATr * U3_U6_PWRflgier * !R3flg
	# !U3_U2_EncReg<7> * DRV0LOWr * U3_U6_PWRflgier
	# !U3_U2_EncReg<6> * DRV0LOWr * U3_U6_PWRflgier
	# !U3_U2_EncReg<5> * DRV0LOWr * U3_U6_PWRflgier
	# !U3_U2_EncReg<4> * DRV0LOWr * U3_U6_PWRflgier
	# !U3_U3_EncReg<7> * DRV1LOWr * U3_U6_PWRflgier
	# !U3_U3_EncReg<6> * DRV1LOWr * U3_U6_PWRflgier
	# !U3_U3_EncReg<5> * DRV1LOWr * U3_U6_PWRflgier
	# !U3_U3_EncReg<4> * DRV1LOWr * U3_U6_PWRflgier
	# !U3_U4_EncReg<7> * DRV2LOWr * U3_U6_PWRflgier
	# !U3_U4_EncReg<6> * DRV2LOWr * U3_U6_PWRflgier
	# !U3_U4_EncReg<5> * DRV2LOWr * U3_U6_PWRflgier
	# !U3_U4_EncReg<4> * DRV2LOWr * U3_U6_PWRflgier
	# !U3_U5_EncReg<7> * DRV3LOWr * U3_U6_PWRflgier
	# !U3_U5_EncReg<6> * DRV3LOWr * U3_U6_PWRflgier
	# !U3_U5_EncReg<5> * DRV3LOWr * U3_U6_PWRflgier
	# !U3_U5_EncReg<4> * DRV3LOWr * U3_U6_PWRflgier;

Current_enable = Gnd;

Motor1_Phase_A_HIN = GPIO8 * U4/M00 * !U4/M01;

U4/M00 := BUSReset * AD<0>.PIN * DRVMTRCTLw
	# BUSReset * U4/M00 * !DRVMTRCTLw;
   U4/M00.CLK  =  !Mclk;	// GCK

DRVMTRCTLw = RD * !WR * U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	!U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

U4/M01 := BUSReset * AD<1>.PIN * DRVMTRCTLw
	# BUSReset * !DRVMTRCTLw * U4/M01;
   U4/M01.CLK  =  !Mclk;	// GCK

!Motor1_Phase_A_LIN = GPIO8 * U4/M01
	# !GPIO8 * U4/M00;

Motor1_Phase_B_HIN = GPIO8 * !U4/M00 * U4/M01;

!Motor1_Phase_B_LIN = GPIO8 * U4/M00
	# !GPIO8 * U4/M01;

Motor2_Phase_A_HIN = GPIO8 * U4/M10 * !U4/M11;

U4/M10 := BUSReset * AD<2>.PIN * DRVMTRCTLw
	# BUSReset * !DRVMTRCTLw * U4/M10;
   U4/M10.CLK  =  !Mclk;	// GCK

U4/M11 := BUSReset * AD<3>.PIN * DRVMTRCTLw
	# BUSReset * !DRVMTRCTLw * U4/M11;
   U4/M11.CLK  =  !Mclk;	// GCK

!Motor2_Phase_A_LIN = GPIO8 * U4/M11
	# !GPIO8 * U4/M10;

Motor2_Phase_B_HIN = GPIO8 * !U4/M10 * U4/M11;

!Motor2_Phase_B_LIN = GPIO8 * U4/M10
	# !GPIO8 * U4/M11;

Motor3_Phase_A_HIN = GPIO8 * U4/M20 * !U4/M21;

U4/M20 := BUSReset * AD<4>.PIN * DRVMTRCTLw
	# BUSReset * !DRVMTRCTLw * U4/M20;
   U4/M20.CLK  =  !Mclk;	// GCK

U4/M21 := BUSReset * AD<5>.PIN * DRVMTRCTLw
	# BUSReset * !DRVMTRCTLw * U4/M21;
   U4/M21.CLK  =  !Mclk;	// GCK

!Motor3_Phase_A_LIN = GPIO8 * U4/M21
	# !GPIO8 * U4/M20;

Motor3_Phase_B_HIN = GPIO8 * !U4/M20 * U4/M21;

!Motor3_Phase_B_LIN = GPIO8 * U4/M20
	# !GPIO8 * U4/M21;

Motor4_Phase_A_HIN = GPIO8 * U4/M30 * !U4/M31;

U4/M30 := BUSReset * AD<6>.PIN * DRVMTRCTLw
	# BUSReset * !DRVMTRCTLw * U4/M30;
   U4/M30.CLK  =  !Mclk;	// GCK

U4/M31 := BUSReset * AD<7>.PIN * DRVMTRCTLw
	# BUSReset * !DRVMTRCTLw * U4/M31;
   U4/M31.CLK  =  !Mclk;	// GCK

!Motor4_Phase_A_LIN = GPIO8 * U4/M31
	# !GPIO8 * U4/M30;

Motor4_Phase_B_HIN = GPIO8 * !U4/M30 * U4/M31;

!Motor4_Phase_B_LIN = GPIO8 * U4/M30
	# !GPIO8 * U4/M31;

Motor_Power := BUSReset * DRVCTLw * AD<2>.PIN
	# BUSReset * !DRVCTLw * Motor_Power;
   Motor_Power.CLK  =  !Mclk;	// GCK

!Motor_Power_n := BUSReset * DRVCTLw * AD<2>.PIN
	# BUSReset * !DRVCTLw * !Motor_Power_n;
   Motor_Power_n.CLK  =  !Mclk;	// GCK

PhaseA_High_1 := BUSReset * PhaseB_Low_1 * !DRVVALV0w * !DRVVALV1w
	# BUSReset * !DRVVALV0w * PhaseA_High_1 * 
	DRVVALV1w
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * 
	!PhaseB_High_1 * DRVVALV0w
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * 
	!PhaseB_High_1 * PhaseB_Low_1 * DRVVALV0w;
   PhaseA_High_1.CLK  =  !Mclk;	// GCK

PhaseB_High_1 := BUSReset * PhaseB_High_1 * !DRVVALV0w
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * 
	PhaseB_High_1 * !PhaseB_Low_1
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * !PhaseB_Low_1 * 
	DRVVALV0w;
   PhaseB_High_1.CLK  =  !Mclk;	// GCK

PhaseB_Low_1 := BUSReset * PhaseB_Low_1 * !DRVVALV0w
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * 
	!PhaseB_High_1 * DRVVALV0w
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * 
	!PhaseB_High_1 * PhaseB_Low_1;
   PhaseB_Low_1.CLK  =  !Mclk;	// GCK

DRVVALV0w = RD * !WR * !U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

DRVVALV1w = RD * !WR * U1_ADDR_reg<0> * !U1_ADDR_reg<2> * 
	U1_ADDR_reg<3> * U1_ADDR_reg<4> * !U1_ADDR_reg<5> * !U1_ADDR_reg<6> * 
	U1_ADDR_reg<1> * !U1_ADDR_reg<7>;

PhaseA_High_2 := BUSReset * !DRVVALV0w * DRVVALV1w * 
	PhaseA_High_2
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_2
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * DRVVALV0w * 
	!PhaseB_High_2
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * DRVVALV0w * 
	!PhaseB_High_2 * PhaseB_Low_2;
   PhaseA_High_2.CLK  =  !Mclk;	// GCK

PhaseB_High_2 := BUSReset * !DRVVALV0w * PhaseB_High_2
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * 
	PhaseB_High_2 * !PhaseB_Low_2
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * DRVVALV0w * 
	!PhaseB_Low_2;
   PhaseB_High_2.CLK  =  !Mclk;	// GCK

PhaseB_Low_2 := BUSReset * !DRVVALV0w * PhaseB_Low_2
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * DRVVALV0w * 
	!PhaseB_High_2
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * 
	!PhaseB_High_2 * PhaseB_Low_2;
   PhaseB_Low_2.CLK  =  !Mclk;	// GCK

PhaseA_High_3 := BUSReset * !DRVVALV0w * DRVVALV1w * 
	PhaseA_High_3
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_3
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * DRVVALV0w * 
	!PhaseB_High_3
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * DRVVALV0w * 
	!PhaseB_High_3 * PhaseB_Low_3;
   PhaseA_High_3.CLK  =  !Mclk;	// GCK

PhaseB_High_3 := BUSReset * !DRVVALV0w * PhaseB_High_3
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * 
	PhaseB_High_3 * !PhaseB_Low_3
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * DRVVALV0w * 
	!PhaseB_Low_3;
   PhaseB_High_3.CLK  =  !Mclk;	// GCK

PhaseB_Low_3 := BUSReset * !DRVVALV0w * PhaseB_Low_3
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * DRVVALV0w * 
	!PhaseB_High_3
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * 
	!PhaseB_High_3 * PhaseB_Low_3;
   PhaseB_Low_3.CLK  =  !Mclk;	// GCK

PhaseA_High_4 := BUSReset * !DRVVALV0w * DRVVALV1w * 
	PhaseA_High_4
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_4
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * DRVVALV0w * 
	!PhaseB_High_4
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * DRVVALV0w * 
	!PhaseB_High_4 * PhaseB_Low_4;
   PhaseA_High_4.CLK  =  !Mclk;	// GCK

PhaseB_High_4 := BUSReset * !DRVVALV0w * PhaseB_High_4
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * 
	PhaseB_High_4 * !PhaseB_Low_4
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * DRVVALV0w * 
	!PhaseB_Low_4;
   PhaseB_High_4.CLK  =  !Mclk;	// GCK

PhaseB_Low_4 := BUSReset * !DRVVALV0w * PhaseB_Low_4
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * DRVVALV0w * 
	!PhaseB_High_4
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * 
	!PhaseB_High_4 * PhaseB_Low_4;
   PhaseB_Low_4.CLK  =  !Mclk;	// GCK

PhaseA_High_5 := BUSReset * DRVVALV0w * PhaseA_High_5
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_5
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_5
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * !DRVVALV0w * 
	!PhaseB_High_5 * PhaseB_Low_5;
   PhaseA_High_5.CLK  =  !Mclk;	// GCK

PhaseB_High_5 := BUSReset * DRVVALV0w * PhaseB_High_5
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_5
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * !DRVVALV0w * 
	PhaseB_High_5 * !PhaseB_Low_5
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_5;
   PhaseB_High_5.CLK  =  !Mclk;	// GCK

PhaseB_Low_5 := BUSReset * DRVVALV0w * PhaseB_Low_5
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_5
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_5
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * !DRVVALV0w * 
	!PhaseB_High_5 * PhaseB_Low_5;
   PhaseB_Low_5.CLK  =  !Mclk;	// GCK

PhaseA_High_6 := BUSReset * DRVVALV0w * PhaseA_High_6
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_6
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_6
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * !DRVVALV0w * 
	!PhaseB_High_6 * PhaseB_Low_6;
   PhaseA_High_6.CLK  =  !Mclk;	// GCK

PhaseB_High_6 := BUSReset * DRVVALV0w * PhaseB_High_6
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_6
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * !DRVVALV0w * 
	PhaseB_High_6 * !PhaseB_Low_6
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_6;
   PhaseB_High_6.CLK  =  !Mclk;	// GCK

PhaseB_Low_6 := BUSReset * DRVVALV0w * PhaseB_Low_6
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_6
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_6
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * !DRVVALV0w * 
	!PhaseB_High_6 * PhaseB_Low_6;
   PhaseB_Low_6.CLK  =  !Mclk;	// GCK

PhaseA_High_7 := BUSReset * DRVVALV0w * PhaseA_High_7
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_7
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_7
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * !DRVVALV0w * 
	!PhaseB_High_7 * PhaseB_Low_7;
   PhaseA_High_7.CLK  =  !Mclk;	// GCK

PhaseB_High_7 := BUSReset * DRVVALV0w * PhaseB_High_7
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_7
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * !DRVVALV0w * 
	PhaseB_High_7 * !PhaseB_Low_7
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_7;
   PhaseB_High_7.CLK  =  !Mclk;	// GCK

PhaseB_Low_7 := BUSReset * DRVVALV0w * PhaseB_Low_7
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_7
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_7
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * !DRVVALV0w * 
	!PhaseB_High_7 * PhaseB_Low_7;
   PhaseB_Low_7.CLK  =  !Mclk;	// GCK

PhaseA_High_8 := BUSReset * DRVVALV0w * PhaseA_High_8
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_8
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_8
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * !DRVVALV0w * 
	!PhaseB_High_8 * PhaseB_Low_8;
   PhaseA_High_8.CLK  =  !Mclk;	// GCK

PhaseB_High_8 := BUSReset * DRVVALV0w * PhaseB_High_8
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_8
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * !DRVVALV0w * 
	PhaseB_High_8 * !PhaseB_Low_8
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_8;
   PhaseB_High_8.CLK  =  !Mclk;	// GCK

PhaseB_Low_8 := BUSReset * DRVVALV0w * PhaseB_Low_8
	# BUSReset * !DRVVALV0w * !DRVVALV1w * PhaseB_Low_8
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_High_8
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * !DRVVALV0w * 
	!PhaseB_High_8 * PhaseB_Low_8;
   PhaseB_Low_8.CLK  =  !Mclk;	// GCK

PhaseA_Low_1 := BUSReset * PhaseB_High_1 * !DRVVALV0w * 
	!DRVVALV1w
	# BUSReset * !DRVVALV0w * DRVVALV1w * PhaseA_Low_1
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * !PhaseB_Low_1 * 
	DRVVALV0w
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * 
	PhaseB_High_1 * !PhaseB_Low_1 * DRVVALV0w;
   PhaseA_Low_1.CLK  =  !Mclk;	// GCK

PhaseA_Low_2 := BUSReset * !DRVVALV0w * DRVVALV1w * PhaseA_Low_2
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_2
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * DRVVALV0w * 
	!PhaseB_Low_2
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * DRVVALV0w * 
	PhaseB_High_2 * !PhaseB_Low_2;
   PhaseA_Low_2.CLK  =  !Mclk;	// GCK

PhaseA_Low_3 := BUSReset * !DRVVALV0w * DRVVALV1w * PhaseA_Low_3
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_3
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * DRVVALV0w * 
	!PhaseB_Low_3
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * DRVVALV0w * 
	PhaseB_High_3 * !PhaseB_Low_3;
   PhaseA_Low_3.CLK  =  !Mclk;	// GCK

PhaseA_Low_4 := BUSReset * !DRVVALV0w * DRVVALV1w * PhaseA_Low_4
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_4
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * DRVVALV0w * 
	!PhaseB_Low_4
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * DRVVALV0w * 
	PhaseB_High_4 * !PhaseB_Low_4;
   PhaseA_Low_4.CLK  =  !Mclk;	// GCK

PhaseA_Low_5 := BUSReset * DRVVALV0w * PhaseA_Low_5
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_5
	# BUSReset * AD<0>.PIN * !AD<1>.PIN * !DRVVALV0w * 
	PhaseB_High_5 * !PhaseB_Low_5
	# BUSReset * !AD<0>.PIN * AD<1>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_5;
   PhaseA_Low_5.CLK  =  !Mclk;	// GCK

PhaseA_Low_6 := BUSReset * DRVVALV0w * PhaseA_Low_6
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_6
	# BUSReset * AD<2>.PIN * !AD<3>.PIN * !DRVVALV0w * 
	PhaseB_High_6 * !PhaseB_Low_6
	# BUSReset * !AD<2>.PIN * AD<3>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_6;
   PhaseA_Low_6.CLK  =  !Mclk;	// GCK

PhaseA_Low_7 := BUSReset * DRVVALV0w * PhaseA_Low_7
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_7
	# BUSReset * AD<4>.PIN * !AD<5>.PIN * !DRVVALV0w * 
	PhaseB_High_7 * !PhaseB_Low_7
	# BUSReset * !AD<4>.PIN * AD<5>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_7;
   PhaseA_Low_7.CLK  =  !Mclk;	// GCK

PhaseA_Low_8 := BUSReset * DRVVALV0w * PhaseA_Low_8
	# BUSReset * !DRVVALV0w * !DRVVALV1w * 
	PhaseB_High_8
	# BUSReset * AD<6>.PIN * !AD<7>.PIN * !DRVVALV0w * 
	PhaseB_High_8 * !PhaseB_Low_8
	# BUSReset * !AD<6>.PIN * AD<7>.PIN * !DRVVALV0w * 
	DRVVALV1w * !PhaseB_Low_8;
   PhaseA_Low_8.CLK  =  !Mclk;	// GCK

R0clk = R3clk;
   !R0clk.OE = R0enable;

R1clk = R3clk;
   !R1clk.OE = R1enable;

R2clk = R3clk;
   !R2clk.OE = R2enable;



Legend:  <signame>.COMB = combinational node mapped to the same physical macrocell
                          as the FastInput "signal" (not logically related)
****************************  Device Pin Out ****************************

Device : XCR3384XL-10-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 PhaseB_High_8                    73 VCC                           
  2 PhaseA_Low_8                     74 BusINT                        
  3 GND                              75 PROHIBITED                    
  4 PhaseA_High_8                    76 VCC                           
  5 PhaseB_Low_7                     77 PROHIBITED                    
  6 PhaseB_High_7                    78 PROHIBITED                    
  7 PhaseA_Low_7                     79 GPIO8                         
  8 PhaseA_High_7                    80 PROHIBITED                    
  9 PhaseB_Low_6                     81 PROHIBITED                    
 10 PhaseB_High_6                    82 PROHIBITED                    
 11 PhaseA_Low_6                     83 PROHIBITED                    
 12 PhaseA_High_6                    84 PROHIBITED                    
 13 GND                              85 GND                           
 14 PhaseB_Low_5                     86 TCK                           
 15 PhaseB_High_5                    87 BUSReset                      
 16 PhaseA_Low_5                     88 WR                            
 17 GND                              89 RD                            
 18 PhaseA_High_5                    90 AS                            
 19 PhaseB_Low_4                     91 AD<0>                         
 20 PhaseB_High_4                    92 AD<1>                         
 21 PhaseA_Low_4                     93 AD<2>                         
 22 TMS                              94 AD<3>                         
 23 PhaseA_High_4                    95 VCC                           
 24 VCC                              96 AD<4>                         
 25 PhaseB_Low_3                     97 AD<5>                         
 26 PhaseB_High_3                    98 AD<6>                         
 27 PhaseA_Low_3                     99 AD<7>                         
 28 PhaseA_High_3                   100 PROHIBITED                    
 29 PhaseB_Low_2                    101 R3clk                         
 30 PhaseB_High_2                   102 R2data                        
 31 PhaseA_Low_2                    103 R2clk                         
 32 PhaseA_High_2                   104 PROHIBITED                    
 33 PE                              105 GND                           
 34 PhaseB_Low_1                    106 R1data                        
 35 PhaseB_High_1                   107 R1clk                         
 36 PhaseA_Low_1                    108 NC                            
 37 PhaseA_High_1                   109 NC                            
 38 PROHIBITED                      110 PROHIBITED                    
 39 PROHIBITED                      111 Motor_Power_n                 
 40 Motor_Power                     112 Motor4_Phase_B_LIN            
 41 PROHIBITED                      113 Motor4_Phase_B_HIN            
 42 PROHIBITED                      114 Motor4_Phase_A_LIN            
 43 R2enable                        115 VCC                           
 44 R3enable                        116 Motor4_Phase_A_HIN            
 45 PROHIBITED                      117 Motor3_Phase_B_LIN            
 46 Current_enable                  118 Motor3_Phase_B_HIN            
 47 AS0                             119 Motor3_Phase_A_LIN            
 48 AS1                             120 Motor3_Phase_A_HIN            
 49 AS2                             121 TDO                           
 50 VCC                             122 WPU                           
 51 VCC                             123 VCC                           
 52 GND                             124 GND                           
 53 PROHIBITED                      125 PROHIBITED                    
 54 PROHIBITED                      126 Mclk                          
 55 PROHIBITED                      127 PROHIBITED                    
 56 WPU                             128 PROHIBITED                    
 57 GND                             129 GND                           
 58 VCC                             130 VCC                           
 59 GND                             131 TDI                           
 60 R0clk                           132 Motor2_Phase_B_LIN            
 61 R0data                          133 Motor2_Phase_B_HIN            
 62 R0flg                           134 Motor2_Phase_A_LIN            
 63 PROHIBITED                      135 GND                           
 64 GND                             136 Motor2_Phase_A_HIN            
 65 R1flg                           137 Motor1_Phase_B_LIN            
 66 R2flg                           138 Motor1_Phase_B_HIN            
 67 R3flg                           139 Motor1_Phase_A_LIN            
 68 PROHIBITED                      140 Motor1_Phase_A_HIN            
 69 R3data                          141 PROHIBITED                    
 70 PROHIBITED                      142 PROHIBITED                    
 71 R0enable                        143 PhaseB_Low_8                  
 72 R1enable                        144 VCC                           


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XCR3384XL-10-TQ144
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : OFF
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Input Limit                                 : 32
Pterm Limit                                 : 28
