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<!DOCTYPE document SYSTEM "file:///C:/Xilinx/xpla3/data/xmlReportxpla3.dtd">
<document><ascFile>U4.rpt</ascFile><devFile>C:/Xilinx/xpla3/data/xcr3384xl.chp</devFile><mfdFile>U4.mfd</mfdFile><htmlFile logo="coolrunner_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="TQ144" date=" 5-19-2004" time="  6:47AM" speed="-10" design="U4" device="XCR3384XL" status="1" eqnType="0" version="1.0" statusStr="Successful" swVersion="G.26"/><inputs id="BUSReset"/><inputs id="AD0PIN_SPECSIG"/><inputs id="RD"/><inputs id="WR"/><inputs id="AS"/><inputs id="AD2PIN_SPECSIG"/><inputs id="AD3PIN_SPECSIG"/><inputs id="AD4PIN_SPECSIG"/><inputs id="AD5PIN_SPECSIG"/><inputs id="AD6PIN_SPECSIG"/><inputs id="AD1PIN_SPECSIG"/><inputs id="AD7PIN_SPECSIG"/><inputs id="xPUP_0"/><inputs id="R0data"/><inputs id="R1data"/><inputs id="R2data"/><inputs id="R3data"/><inputs id="R0flg"/><inputs id="R1flg"/><inputs id="R2flg"/><inputs id="R3flg"/><inputs id="GPIO8"/><inputs id="GPIO9"/><global_inputs id="Mclk" use="GCK"/><pin id="FB1_MC1_PIN94" use="IO_SPECSIG" slew="SLOW" pinnum="94" signal="AD3_SPECSIG"/><pin id="FB1_MC5_PIN93" use="IO_SPECSIG" slew="SLOW" pinnum="93" signal="AD2_SPECSIG"/><pin id="FB1_MC13_PIN92" use="IO_SPECSIG" slew="SLOW" pinnum="92" signal="AD1_SPECSIG"/><pin id="FB1_MC16_PIN91" use="IO_SPECSIG" slew="SLOW" pinnum="91" signal="AD0_SPECSIG"/><pin id="FB2_MC2_PIN96" use="IO_SPECSIG" slew="SLOW" pinnum="96" signal="AD4_SPECSIG"/><pin id="FB2_MC3_PIN97" use="IO_SPECSIG" slew="SLOW" pinnum="97" signal="AD5_SPECSIG"/><pin id="FB2_MC4_PIN98" use="IO_SPECSIG" slew="SLOW" pinnum="98" signal="AD6_SPECSIG"/><pin id="FB2_MC5_PIN99" use="IO_SPECSIG" slew="SLOW" pinnum="99" signal="AD7_SPECSIG"/><pin id="FB2_MC14_PIN101" use="O" slew="SLOW" pinnum="101" signal="R3clk"/><pin id="FB2_MC15_PIN102" use="I" pinnum="102" signal="R2data"/><pin id="FB2_MC16_PIN103" use="O" slew="SLOW" pinnum="103" signal="R2clk"/><pin id="FB3_MC4_PIN90" use="I" pinnum="90" signal="AS"/><pin id="FB3_MC5_PIN89" use="I" pinnum="89" signal="RD"/><pin id="FB3_MC14_PIN88" use="I" pinnum="88" signal="WR"/><pin id="FB3_MC16_PIN87" use="I" pinnum="87" signal="BUSReset"/><pin id="FB4_MC2_PIN106" use="I" pinnum="106" signal="R1data"/><pin id="FB4_MC3_PIN107" use="O" slew="SLOW" pinnum="107" signal="R1clk"/><pin id="FB4_MC5_PIN111" use="O" slew="SLOW" pinnum="111" signal="Motor_Power_n"/><pin id="FB4_MC13_PIN112" use="O" slew="SLOW" pinnum="112" signal="Motor4_Phase_B_LIN"/><pin id="FB4_MC14_PIN113" use="O" slew="SLOW" pinnum="113" signal="Motor4_Phase_B_HIN"/><pin id="FB4_MC15_PIN114" use="O" slew="SLOW" pinnum="114" signal="Motor4_Phase_A_LIN"/><pin id="FB4_MC16_PIN116" use="O" slew="SLOW" pinnum="116" signal="Motor4_Phase_A_HIN"/><pin id="FB5_MC2_PIN86" use="b_SPECSIG" pinnum="86" signal="N_PZ_1049"/><pin id="FB6_MC1_PIN67" use="I" pinnum="67" signal="R3flg"/><pin id="FB6_MC16_PIN69" use="I" pinnum="69" signal="R3data"/><pin id="FB7_MC2_PIN79" use="I" pinnum="79" signal="GPIO8"/><pin id="FB7_MC3_PIN78" use="I" pinnum="78" signal="GPIO9"/><pin id="FB8_MC2_PIN71" use="O" slew="SLOW" pinnum="71" signal="R0enable"/><pin id="FB8_MC3_PIN72" use="O" slew="SLOW" pinnum="72" signal="R1enable"/><pin id="FB8_MC16_PIN74" use="O" slew="SLOW" pinnum="74" signal="BusINT"/><pin id="FB9_MC1_PIN122" pinnum="122"/><pin id="FB9_MC3_PIN121" pinnum="121"/><pin id="FB9_MC5_PIN120" use="O" slew="SLOW" pinnum="120" signal="Motor3_Phase_A_HIN"/><pin id="FB10_MC3_PIN131" pinnum="131"/><pin id="FB10_MC4_PIN132" use="O" slew="SLOW" pinnum="132" signal="Motor2_Phase_B_LIN"/><pin id="FB10_MC15_PIN133" use="O" slew="SLOW" pinnum="133" signal="Motor2_Phase_B_HIN"/><pin id="FB10_MC16_PIN134" use="O" slew="SLOW" pinnum="134" signal="Motor2_Phase_A_LIN"/><pin id="FB11_MC5_PIN117" use="O" slew="SLOW" pinnum="117" signal="Motor3_Phase_B_LIN"/><pin id="FB11_MC15_PIN118" use="O" slew="SLOW" pinnum="118" signal="Motor3_Phase_B_HIN"/><pin id="FB11_MC16_PIN119" use="O" slew="SLOW" pinnum="119" signal="Motor3_Phase_A_LIN"/><pin id="FB12_MC1_PIN139" use="O" slew="SLOW" pinnum="139" signal="Motor1_Phase_A_LIN"/><pin id="FB12_MC3_PIN138" use="O" slew="SLOW" pinnum="138" signal="Motor1_Phase_B_HIN"/><pin id="FB12_MC4_PIN137" use="O" slew="SLOW" pinnum="137" signal="Motor1_Phase_B_LIN"/><pin id="FB12_MC13_PIN136" use="O" slew="SLOW" pinnum="136" signal="Motor2_Phase_A_HIN"/><pin id="FB13_MC1_PIN61" use="I" pinnum="61" signal="R0data"/><pin id="FB13_MC3_PIN62" use="I" pinnum="62" signal="R0flg"/><pin id="FB13_MC14_PIN65" use="I" pinnum="65" signal="R1flg"/><pin id="FB13_MC16_PIN66" use="I" pinnum="66" signal="R2flg"/><pin id="FB14_MC2_PIN47" use="O" slew="SLOW" pinnum="47" signal="AS0"/><pin id="FB14_MC3_PIN46" use="O" slew="SLOW" pinnum="46" signal="Current_enable"/><pin id="FB14_MC14_PIN44" use="O" slew="SLOW" pinnum="44" signal="R3enable"/><pin id="FB14_MC16_PIN43" use="O" slew="SLOW" pinnum="43" signal="R2enable"/><pin id="FB15_MC3_PIN60" use="O" slew="SLOW" pinnum="60" signal="R0clk"/><pin id="FB15_MC5_PIN56" pinnum="56"/><pin id="FB16_MC2_PIN48" use="O" slew="SLOW" pinnum="48" signal="AS1"/><pin id="FB16_MC4_PIN49" use="O" slew="SLOW" pinnum="49" signal="AS2"/><pin id="FB17_MC3_PIN6" use="O" slew="SLOW" pinnum="6" signal="PhaseB_High_7"/><pin id="FB17_MC4_PIN5" use="O" slew="SLOW" pinnum="5" signal="PhaseB_Low_7"/><pin id="FB17_MC5_PIN4" use="O" slew="SLOW" pinnum="4" signal="PhaseA_High_8"/><pin id="FB17_MC15_PIN2" use="O" slew="SLOW" pinnum="2" signal="PhaseA_Low_8"/><pin id="FB17_MC16_PIN1" use="O" slew="SLOW" pinnum="1" signal="PhaseB_High_8"/><pin id="FB18_MC1_PIN7" use="O" slew="SLOW" pinnum="7" signal="PhaseA_Low_7"/><pin id="FB18_MC2_PIN8" use="O" slew="SLOW" pinnum="8" signal="PhaseA_High_7"/><pin id="FB18_MC3_PIN9" use="O" slew="SLOW" pinnum="9" signal="PhaseB_Low_6"/><pin id="FB18_MC4_PIN10" use="O" slew="SLOW" pinnum="10" signal="PhaseB_High_6"/><pin id="FB18_MC15_PIN11" use="O" slew="SLOW" pinnum="11" signal="PhaseA_Low_6"/><pin id="FB18_MC16_PIN12" use="O" slew="SLOW" pinnum="12" signal="PhaseA_High_6"/><pin id="FB19_MC2_PIN143" use="O" slew="SLOW" pinnum="143" signal="PhaseB_Low_8"/><pin id="FB19_MC4_PIN142" use="O" slew="SLOW" pinnum="142" signal="Heater_Control"/><pin id="FB19_MC15_PIN140" use="O" slew="SLOW" pinnum="140" signal="Motor1_Phase_A_HIN"/><pin id="FB20_MC1_PIN14" use="O" slew="SLOW" pinnum="14" signal="PhaseB_Low_5"/><pin id="FB20_MC4_PIN15" use="O" slew="SLOW" pinnum="15" signal="PhaseB_High_5"/><pin id="FB20_MC14_PIN16" use="O" slew="SLOW" pinnum="16" signal="PhaseA_Low_5"/><pin id="FB20_MC16_PIN18" use="O" slew="SLOW" pinnum="18" signal="PhaseA_High_5"/><pin id="FB21_MC13_PIN40" use="O" slew="SLOW" pinnum="40" signal="Motor_Power"/><pin id="FB21_MC16_PIN37" use="O" slew="SLOW" pinnum="37" signal="PhaseA_High_1"/><pin id="FB22_MC1_PIN19" use="O" slew="SLOW" pinnum="19" signal="PhaseB_Low_4"/><pin id="FB22_MC3_PIN20" use="O" slew="SLOW" pinnum="20" signal="PhaseB_High_4"/><pin id="FB22_MC4_PIN21" use="O" slew="SLOW" pinnum="21" signal="PhaseA_Low_4"/><pin id="FB22_MC5_PIN22" pinnum="22"/><pin id="FB22_MC13_PIN23" use="O" slew="SLOW" pinnum="23" signal="PhaseA_High_4"/><pin id="FB22_MC16_PIN25" use="O" slew="SLOW" pinnum="25" signal="PhaseB_Low_3"/><pin id="FB23_MC1_PIN36" use="O" slew="SLOW" pinnum="36" signal="PhaseA_Low_1"/><pin id="FB23_MC14_PIN35" use="O" slew="SLOW" pinnum="35" signal="PhaseB_High_1"/><pin id="FB24_MC1_PIN26" use="O" slew="SLOW" pinnum="26" signal="PhaseB_High_3"/><pin id="FB24_MC2_PIN27" use="O" slew="SLOW" pinnum="27" signal="PhaseA_Low_3"/><pin id="FB24_MC3_PIN28" use="O" slew="SLOW" pinnum="28" signal="PhaseA_High_3"/><pin id="FB24_MC4_PIN29" use="O" slew="SLOW" pinnum="29" signal="PhaseB_Low_2"/><pin id="FB24_MC5_PIN30" use="O" slew="SLOW" pinnum="30" signal="PhaseB_High_2"/><pin id="FB24_MC13_PIN31" use="O" slew="SLOW" pinnum="31" signal="PhaseA_Low_2"/><pin id="FB24_MC14_PIN32" use="O" slew="SLOW" pinnum="32" signal="PhaseA_High_2"/><pin id="FB24_MC16_PIN34" use="O" slew="SLOW" pinnum="34" signal="PhaseB_Low_1"/><pin id="GLOBAL_PIN3" use="GCK" pinnum="126" signal="Mclk"/><prohibit pinnum="38"/><prohibit pinnum="39"/><prohibit pinnum="41"/><prohibit pinnum="42"/><prohibit pinnum="45"/><prohibit pinnum="53"/><prohibit pinnum="54"/><prohibit pinnum="55"/><prohibit pinnum="63"/><prohibit pinnum="68"/><prohibit pinnum="70"/><prohibit pinnum="75"/><prohibit pinnum="77"/><prohibit pinnum="80"/><prohibit pinnum="81"/><prohibit pinnum="82"/><prohibit pinnum="83"/><prohibit pinnum="84"/><prohibit pinnum="100"/><prohibit pinnum="104"/><prohibit pinnum="110"/><prohibit pinnum="125"/><prohibit pinnum="127"/><prohibit pinnum="128"/><prohibit pinnum="141"/><uct id="UCT2" bct="FB3_bct7"/><uct id="UCT3" bct="FB4_bct7"/><fblock id="FB1" pinUse="4"><macrocell id="FB1_MC1" pin="FB1_MC1_PIN94" sigUse="13" signal="AD3_SPECSIG"><eq_pterm ptindx="FB1_18"/><eq_pterm ptindx="FB1_10"/><eq_pterm ptindx="FB1_12"/><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_16"/><eq_pterm ptindx="FB1_23"/><eq_pterm ptindx="FB1_24"/><eq_pterm ptindx="FB1_25"/><eq_pterm ptindx="FB1_26"/></macrocell><macrocell id="FB1_MC2"/><macrocell id="FB1_MC3"/><macrocell id="FB1_MC4"/><macrocell id="FB1_MC5" pin="FB1_MC5_PIN93" sigUse="13" signal="AD2_SPECSIG"><eq_pterm ptindx="FB1_18"/><eq_pterm ptindx="FB1_10"/><eq_pterm ptindx="FB1_12"/><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_16"/><eq_pterm ptindx="FB1_19"/><eq_pterm ptindx="FB1_20"/><eq_pterm ptindx="FB1_21"/><eq_pterm ptindx="FB1_22"/></macrocell><macrocell id="FB1_MC6"/><macrocell id="FB1_MC7"/><macrocell id="FB1_MC8" sigUse="3" signal="N_PZ_578"><eq_pterm ptindx="FB1_40"/><eq_pterm ptindx="FB1_39"/></macrocell><macrocell id="FB1_MC9" sigUse="6" signal="U3_U2_EncReg5_SPECSIG"><eq_pterm ptindx="FB1_38"/><eq_pterm ptindx="FB1_37"/></macrocell><macrocell id="FB1_MC10" sigUse="6" signal="U3_U2_EncReg4_SPECSIG"><eq_pterm ptindx="FB1_36"/><eq_pterm ptindx="FB1_35"/></macrocell><macrocell id="FB1_MC11" sigUse="6" signal="U3_U2_EncReg0_SPECSIG"><eq_pterm ptindx="FB1_34"/><eq_pterm ptindx="FB1_33"/></macrocell><macrocell id="FB1_MC12" sigUse="6" signal="U3_U2_EncReg3_SPECSIG"><eq_pterm ptindx="FB1_32"/><eq_pterm ptindx="FB1_31"/></macrocell><macrocell id="FB1_MC13" pin="FB1_MC13_PIN92" sigUse="14" signal="AD1_SPECSIG"><eq_pterm ptindx="FB1_10"/><eq_pterm ptindx="FB1_12"/><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_16"/><eq_pterm ptindx="FB1_9"/><eq_pterm ptindx="FB1_11"/><eq_pterm ptindx="FB1_13"/><eq_pterm ptindx="FB1_15"/><eq_pterm ptindx="FB1_17"/></macrocell><macrocell id="FB1_MC14" sigUse="6" signal="U3_U2_EncReg2_SPECSIG"><eq_pterm ptindx="FB1_30"/><eq_pterm ptindx="FB1_29"/></macrocell><macrocell id="FB1_MC15" sigUse="6" signal="U3_U2_EncReg1_SPECSIG"><eq_pterm ptindx="FB1_28"/><eq_pterm ptindx="FB1_27"/></macrocell><macrocell id="FB1_MC16" pin="FB1_MC16_PIN91" sigUse="18" signal="AD0_SPECSIG"><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_1"/><eq_pterm ptindx="FB1_3"/><eq_pterm ptindx="FB1_5"/><eq_pterm ptindx="FB1_7"/><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_4"/><eq_pterm ptindx="FB1_6"/><eq_pterm ptindx="FB1_8"/></macrocell><fbinput id="FB1_I1" signal="BUSReset"/><fbinput id="FB1_I2" signal="DRV0HIGHr"/><fbinput id="FB1_I3" signal="DRV0LOWr"/><fbinput id="FB1_I4" signal="DRV1HIGHr"/><fbinput id="FB1_I5" signal="DRV1LOWr"/><fbinput id="FB1_I6" signal="DRV2HIGHr"/><fbinput id="FB1_I7" signal="DRV2LOWr"/><fbinput id="FB1_I8" signal="DRV3HIGHr"/><fbinput id="FB1_I9" signal="DRV3LOWr"/><fbinput id="FB1_I10" signal="DRVSTATr"/><fbinput id="FB1_I11" signal="N_PZ_578"/><fbinput id="FB1_I12" signal="R0data"/><fbinput id="FB1_I13" signal="R0enable"/><fbinput id="FB1_I14" signal="U3_NET282"/><fbinput id="FB1_I15" signal="U3_U1DAVr_SPECSIG"/><fbinput id="FB1_I16" signal="U3_U2_EncReg0_SPECSIG"/><fbinput id="FB1_I17" signal="U3_U2_EncReg1_SPECSIG"/><fbinput id="FB1_I18" signal="U3_U2_EncReg2_SPECSIG"/><fbinput id="FB1_I19" signal="U3_U2_EncReg3_SPECSIG"/><fbinput id="FB1_I20" signal="U3_U2_EncReg4_SPECSIG"/><fbinput id="FB1_I21" signal="U3_U2_EncReg5_SPECSIG"/><fbinput id="FB1_I22" signal="U3_U2_EncReg8_SPECSIG"/><fbinput id="FB1_I23" signal="U3_U3_EncReg0_SPECSIG"/><fbinput id="FB1_I24" signal="U3_U3_EncReg1_SPECSIG"/><fbinput id="FB1_I25" signal="U3_U3_EncReg2_SPECSIG"/><fbinput id="FB1_I26" signal="U3_U3_EncReg3_SPECSIG"/><fbinput id="FB1_I27" signal="U3_U3_EncReg8_SPECSIG"/><fbinput id="FB1_I28" signal="U3_U4_EncReg0_SPECSIG"/><fbinput id="FB1_I29" signal="U3_U4_EncReg1_SPECSIG"/><fbinput id="FB1_I30" signal="U3_U4_EncReg2_SPECSIG"/><fbinput id="FB1_I31" signal="U3_U4_EncReg3_SPECSIG"/><fbinput id="FB1_I32" signal="U3_U4_EncReg8_SPECSIG"/><fbinput id="FB1_I33" signal="U3_U5_EncReg0_SPECSIG"/><fbinput id="FB1_I34" signal="U3_U5_EncReg1_SPECSIG"/><fbinput id="FB1_I35" signal="U3_U5_EncReg2_SPECSIG"/><fbinput id="FB1_I36" signal="U3_U5_EncReg3_SPECSIG"/><fbinput id="FB1_I37" signal="U3_U5_EncReg8_SPECSIG"/><fbinput id="FB1_I38" signal="U3_U6_PWRflgier"/><PAL><pterm id="FB1_0"><signal id="U3_U1DAVr_SPECSIG" negated="ON"/><signal id="DRVSTATr"/></pterm><pterm id="FB1_1"><signal id="U3_U2_EncReg8_SPECSIG" negated="ON"/><signal id="DRV0HIGHr"/></pterm><pterm id="FB1_2"><signal id="U3_U2_EncReg0_SPECSIG" negated="ON"/><signal id="DRV0HIGHr" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB1_3"><signal id="U3_U3_EncReg8_SPECSIG" negated="ON"/><signal id="DRV1HIGHr"/></pterm><pterm id="FB1_4"><signal id="U3_U3_EncReg0_SPECSIG" negated="ON"/><signal id="DRV1HIGHr" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB1_5"><signal id="U3_U4_EncReg8_SPECSIG" negated="ON"/><signal id="DRV2HIGHr"/></pterm><pterm id="FB1_6"><signal id="U3_U4_EncReg0_SPECSIG" negated="ON"/><signal id="DRV2HIGHr" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB1_7"><signal id="U3_U5_EncReg8_SPECSIG" negated="ON"/><signal id="DRV3HIGHr"/></pterm><pterm id="FB1_8"><signal id="U3_U5_EncReg0_SPECSIG" negated="ON"/><signal id="DRV3HIGHr" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB1_9"><signal id="DRVSTATr"/><signal id="U3_U6_PWRflgier" negated="ON"/></pterm><pterm id="FB1_10"><signal id="DRV0HIGHr"/></pterm><pterm id="FB1_11"><signal id="U3_U2_EncReg1_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB1_12"><signal id="DRV1HIGHr"/></pterm><pterm id="FB1_13"><signal id="U3_U3_EncReg1_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB1_14"><signal id="DRV2HIGHr"/></pterm><pterm id="FB1_15"><signal id="U3_U4_EncReg1_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB1_16"><signal id="DRV3HIGHr"/></pterm><pterm id="FB1_17"><signal id="U3_U5_EncReg1_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB1_18"><signal id="DRVSTATr"/></pterm><pterm id="FB1_19"><signal id="U3_U2_EncReg2_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB1_20"><signal id="U3_U3_EncReg2_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB1_21"><signal id="U3_U4_EncReg2_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB1_22"><signal id="U3_U5_EncReg2_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB1_23"><signal id="U3_U2_EncReg3_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB1_24"><signal id="U3_U3_EncReg3_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB1_25"><signal id="U3_U4_EncReg3_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB1_26"><signal id="U3_U5_EncReg3_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB1_27"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg0_SPECSIG"/></pterm><pterm id="FB1_28"><signal id="U3_U2_EncReg1_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB1_29"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg1_SPECSIG"/></pterm><pterm id="FB1_30"><signal id="U3_U2_EncReg2_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB1_31"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg2_SPECSIG"/></pterm><pterm id="FB1_32"><signal id="U3_U2_EncReg3_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB1_33"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="R0data"/></pterm><pterm id="FB1_34"><signal id="U3_U2_EncReg0_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB1_35"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg3_SPECSIG"/></pterm><pterm id="FB1_36"><signal id="U3_U2_EncReg4_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB1_37"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg4_SPECSIG"/></pterm><pterm id="FB1_38"><signal id="U3_U2_EncReg5_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB1_39"><signal id="BUSReset"/><signal id="R0enable"/></pterm><pterm id="FB1_40"><signal id="BUSReset"/><signal id="U3_NET282" negated="ON"/></pterm></PAL><equation id="AD3_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB1_18"/><eq_pterm ptindx="FB1_10"/><eq_pterm ptindx="FB1_12"/><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_16"/><eq_pterm ptindx="FB1_23"/><eq_pterm ptindx="FB1_24"/><eq_pterm ptindx="FB1_25"/><eq_pterm ptindx="FB1_26"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation><equation id="AD2_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB1_18"/><eq_pterm ptindx="FB1_10"/><eq_pterm ptindx="FB1_12"/><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_16"/><eq_pterm ptindx="FB1_19"/><eq_pterm ptindx="FB1_20"/><eq_pterm ptindx="FB1_21"/><eq_pterm ptindx="FB1_22"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation><equation id="N_PZ_578"><d2><eq_pterm ptindx="FB1_40"/><eq_pterm ptindx="FB1_39"/></d2></equation><equation id="U3_U2_EncReg5_SPECSIG"><d2><eq_pterm ptindx="FB1_38"/><eq_pterm ptindx="FB1_37"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U2_EncReg4_SPECSIG"><d2><eq_pterm ptindx="FB1_36"/><eq_pterm ptindx="FB1_35"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U2_EncReg0_SPECSIG"><d2><eq_pterm ptindx="FB1_34"/><eq_pterm ptindx="FB1_33"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U2_EncReg3_SPECSIG"><d2><eq_pterm ptindx="FB1_32"/><eq_pterm ptindx="FB1_31"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="AD1_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB1_10"/><eq_pterm ptindx="FB1_12"/><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_16"/><eq_pterm ptindx="FB1_9"/><eq_pterm ptindx="FB1_11"/><eq_pterm ptindx="FB1_13"/><eq_pterm ptindx="FB1_15"/><eq_pterm ptindx="FB1_17"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation><equation id="U3_U2_EncReg2_SPECSIG"><d2><eq_pterm ptindx="FB1_30"/><eq_pterm ptindx="FB1_29"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U2_EncReg1_SPECSIG"><d2><eq_pterm ptindx="FB1_28"/><eq_pterm ptindx="FB1_27"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="AD0_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_1"/><eq_pterm ptindx="FB1_3"/><eq_pterm ptindx="FB1_5"/><eq_pterm ptindx="FB1_7"/><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_4"/><eq_pterm ptindx="FB1_6"/><eq_pterm ptindx="FB1_8"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation></fblock><fblock id="FB2" pinUse="7"><macrocell id="FB2_MC1"/><macrocell id="FB2_MC2" pin="FB2_MC2_PIN96" sigUse="14" signal="AD4_SPECSIG"><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_5"/><eq_pterm ptindx="FB2_7"/><eq_pterm ptindx="FB2_9"/><eq_pterm ptindx="FB2_11"/><eq_pterm ptindx="FB2_13"/></macrocell><macrocell id="FB2_MC3" pin="FB2_MC3_PIN97" sigUse="14" signal="AD5_SPECSIG"><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_14"/><eq_pterm ptindx="FB2_15"/><eq_pterm ptindx="FB2_16"/><eq_pterm ptindx="FB2_17"/><eq_pterm ptindx="FB2_18"/></macrocell><macrocell id="FB2_MC4" pin="FB2_MC4_PIN98" sigUse="14" signal="AD6_SPECSIG"><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_19"/><eq_pterm ptindx="FB2_20"/><eq_pterm ptindx="FB2_21"/><eq_pterm ptindx="FB2_22"/><eq_pterm ptindx="FB2_23"/></macrocell><macrocell id="FB2_MC5" pin="FB2_MC5_PIN99" sigUse="14" signal="AD7_SPECSIG"><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_24"/><eq_pterm ptindx="FB2_25"/><eq_pterm ptindx="FB2_26"/><eq_pterm ptindx="FB2_27"/><eq_pterm ptindx="FB2_28"/></macrocell><macrocell id="FB2_MC6"/><macrocell id="FB2_MC7"/><macrocell id="FB2_MC8" sigUse="3" signal="N_PZ_581"><eq_pterm ptindx="FB2_39"/><eq_pterm ptindx="FB2_40"/></macrocell><macrocell id="FB2_MC9" sigUse="3" signal="N_PZ_580"><eq_pterm ptindx="FB2_39"/><eq_pterm ptindx="FB2_37"/></macrocell><macrocell id="FB2_MC10" sigUse="6" signal="U3_U4_EncReg4_SPECSIG"><eq_pterm ptindx="FB2_36"/><eq_pterm ptindx="FB2_35"/></macrocell><macrocell id="FB2_MC11" sigUse="6" signal="U3_U4_EncReg7_SPECSIG"><eq_pterm ptindx="FB2_34"/><eq_pterm ptindx="FB2_33"/></macrocell><macrocell id="FB2_MC12" sigUse="6" signal="U3_U4_EncReg6_SPECSIG"><eq_pterm ptindx="FB2_32"/><eq_pterm ptindx="FB2_31"/></macrocell><macrocell id="FB2_MC13" sigUse="6" signal="U3_U4_EncReg5_SPECSIG"><eq_pterm ptindx="FB2_30"/><eq_pterm ptindx="FB2_29"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIN101" sigUse="5" signal="R3clk"><eq_pterm ptindx="FB2_2"/><eq_pterm ptindx="FB2_3"/><eq_pterm ptindx="FB2_4"/></macrocell><macrocell id="FB2_MC15" pin="FB2_MC15_PIN102"/><macrocell id="FB2_MC16" pin="FB2_MC16_PIN103" sigUse="2" signal="R2clk"><eq_pterm ptindx="FB2_38"/></macrocell><fbinput id="FB2_I1" signal="BUSReset"/><fbinput id="FB2_I2" signal="DRV0HIGHr"/><fbinput id="FB2_I3" signal="DRV0LOWr"/><fbinput id="FB2_I4" signal="DRV1HIGHr"/><fbinput id="FB2_I5" signal="DRV1LOWr"/><fbinput id="FB2_I6" signal="DRV2HIGHr"/><fbinput id="FB2_I7" signal="DRV2LOWr"/><fbinput id="FB2_I8" signal="DRV3HIGHr"/><fbinput id="FB2_I9" signal="DRV3LOWr"/><fbinput id="FB2_I10" signal="DRVSTATr"/><fbinput id="FB2_I11" signal="N_PZ_580"/><fbinput id="FB2_I12" signal="R0flg"/><fbinput id="FB2_I13" signal="R1flg"/><fbinput id="FB2_I14" signal="R2enable"/><fbinput id="FB2_I15" signal="R2flg"/><fbinput id="FB2_I16" signal="R3clk"/><fbinput id="FB2_I17" signal="R3enable"/><fbinput id="FB2_I18" signal="R3flg"/><fbinput id="FB2_I19" signal="U3_NET282"/><fbinput id="FB2_I20" signal="U3_U1CEr_SPECSIG"/><fbinput id="FB2_I21" signal="U3_U1SS_SPECSIG"/><fbinput id="FB2_I22" signal="U3_U2_EncReg4_SPECSIG"/><fbinput id="FB2_I23" signal="U3_U2_EncReg5_SPECSIG"/><fbinput id="FB2_I24" signal="U3_U2_EncReg6_SPECSIG"/><fbinput id="FB2_I25" signal="U3_U2_EncReg7_SPECSIG"/><fbinput id="FB2_I26" signal="U3_U3_EncReg4_SPECSIG"/><fbinput id="FB2_I27" signal="U3_U3_EncReg5_SPECSIG"/><fbinput id="FB2_I28" signal="U3_U3_EncReg6_SPECSIG"/><fbinput id="FB2_I29" signal="U3_U3_EncReg7_SPECSIG"/><fbinput id="FB2_I30" signal="U3_U4_EncReg3_SPECSIG"/><fbinput id="FB2_I31" signal="U3_U4_EncReg4_SPECSIG"/><fbinput id="FB2_I32" signal="U3_U4_EncReg5_SPECSIG"/><fbinput id="FB2_I33" signal="U3_U4_EncReg6_SPECSIG"/><fbinput id="FB2_I34" signal="U3_U4_EncReg7_SPECSIG"/><fbinput id="FB2_I35" signal="U3_U5_EncReg4_SPECSIG"/><fbinput id="FB2_I36" signal="U3_U5_EncReg5_SPECSIG"/><fbinput id="FB2_I37" signal="U3_U5_EncReg6_SPECSIG"/><fbinput id="FB2_I38" signal="U3_U5_EncReg7_SPECSIG"/><PAL><pterm id="FB2_0"><signal id="R3enable"/></pterm><pterm id="FB2_1"><signal id="R2enable"/></pterm><pterm id="FB2_2"><signal id="R3clk" negated="ON"/><signal id="BUSReset" negated="ON"/></pterm><pterm id="FB2_3"><signal id="R3clk" negated="ON"/><signal id="U3_U1SS_SPECSIG" negated="ON"/></pterm><pterm id="FB2_4"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1CEr_SPECSIG"/></pterm><pterm id="FB2_5"><signal id="DRVSTATr"/><signal id="R0flg" negated="ON"/></pterm><pterm id="FB2_6"><signal id="DRV0HIGHr"/></pterm><pterm id="FB2_7"><signal id="U3_U2_EncReg4_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB2_8"><signal id="DRV1HIGHr"/></pterm><pterm id="FB2_9"><signal id="U3_U3_EncReg4_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB2_10"><signal id="DRV2HIGHr"/></pterm><pterm id="FB2_11"><signal id="U3_U4_EncReg4_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB2_12"><signal id="DRV3HIGHr"/></pterm><pterm id="FB2_13"><signal id="U3_U5_EncReg4_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB2_14"><signal id="DRVSTATr"/><signal id="R1flg" negated="ON"/></pterm><pterm id="FB2_15"><signal id="U3_U2_EncReg5_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB2_16"><signal id="U3_U3_EncReg5_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB2_17"><signal id="U3_U4_EncReg5_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB2_18"><signal id="U3_U5_EncReg5_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB2_19"><signal id="DRVSTATr"/><signal id="R2flg" negated="ON"/></pterm><pterm id="FB2_20"><signal id="U3_U2_EncReg6_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB2_21"><signal id="U3_U3_EncReg6_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB2_22"><signal id="U3_U4_EncReg6_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB2_23"><signal id="U3_U5_EncReg6_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB2_24"><signal id="DRVSTATr"/><signal id="R3flg" negated="ON"/></pterm><pterm id="FB2_25"><signal id="U3_U2_EncReg7_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/></pterm><pterm id="FB2_26"><signal id="U3_U3_EncReg7_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/></pterm><pterm id="FB2_27"><signal id="U3_U4_EncReg7_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/></pterm><pterm id="FB2_28"><signal id="U3_U5_EncReg7_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/></pterm><pterm id="FB2_29"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg4_SPECSIG"/></pterm><pterm id="FB2_30"><signal id="U3_U4_EncReg5_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB2_31"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg5_SPECSIG"/></pterm><pterm id="FB2_32"><signal id="U3_U4_EncReg6_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB2_33"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg6_SPECSIG"/></pterm><pterm id="FB2_34"><signal id="U3_U4_EncReg7_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB2_35"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg3_SPECSIG"/></pterm><pterm id="FB2_36"><signal id="U3_U4_EncReg4_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB2_37"><signal id="BUSReset"/><signal id="R2enable"/></pterm><pterm id="FB2_38"><signal id="R3clk"/></pterm><pterm id="FB2_39"><signal id="BUSReset"/><signal id="U3_NET282" negated="ON"/></pterm><pterm id="FB2_40"><signal id="BUSReset"/><signal id="R3enable"/></pterm></PAL><equation id="AD4_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_5"/><eq_pterm ptindx="FB2_7"/><eq_pterm ptindx="FB2_9"/><eq_pterm ptindx="FB2_11"/><eq_pterm ptindx="FB2_13"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation><equation id="AD5_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_14"/><eq_pterm ptindx="FB2_15"/><eq_pterm ptindx="FB2_16"/><eq_pterm ptindx="FB2_17"/><eq_pterm ptindx="FB2_18"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation><equation id="AD6_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_19"/><eq_pterm ptindx="FB2_20"/><eq_pterm ptindx="FB2_21"/><eq_pterm ptindx="FB2_22"/><eq_pterm ptindx="FB2_23"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation><equation id="AD7_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_8"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_24"/><eq_pterm ptindx="FB2_25"/><eq_pterm ptindx="FB2_26"/><eq_pterm ptindx="FB2_27"/><eq_pterm ptindx="FB2_28"/></d2><oe><eq_pterm ptindx="FB3_7"/></oe></equation><equation id="N_PZ_581"><d2><eq_pterm ptindx="FB2_39"/><eq_pterm ptindx="FB2_40"/></d2></equation><equation id="N_PZ_580"><d2><eq_pterm ptindx="FB2_39"/><eq_pterm ptindx="FB2_37"/></d2></equation><equation id="U3_U4_EncReg4_SPECSIG"><d2><eq_pterm ptindx="FB2_36"/><eq_pterm ptindx="FB2_35"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg7_SPECSIG"><d2><eq_pterm ptindx="FB2_34"/><eq_pterm ptindx="FB2_33"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg6_SPECSIG"><d2><eq_pterm ptindx="FB2_32"/><eq_pterm ptindx="FB2_31"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg5_SPECSIG"><d2><eq_pterm ptindx="FB2_30"/><eq_pterm ptindx="FB2_29"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="R3clk" regUse="T"><d2><eq_pterm ptindx="FB2_2"/><eq_pterm ptindx="FB2_3"/><eq_pterm ptindx="FB2_4"/></d2><clk><fastsig signal="Mclk"/></clk><oe><eq_pterm ptindx="FB2_0"/></oe><prld ptindx="GND"/></equation><equation id="R2clk"><d1><eq_pterm ptindx="FB2_38"/></d1><oe><eq_pterm ptindx="FB2_1"/></oe></equation></fblock><fblock id="FB3" pinUse="4"><macrocell id="FB3_MC1" sigUse="10" signal="DRV1LOWr"><eq_pterm ptindx="FB3_8"/></macrocell><macrocell id="FB3_MC2" sigUse="10" signal="DRV1HIGHr"><eq_pterm ptindx="FB3_10"/></macrocell><macrocell id="FB3_MC3" sigUse="10" signal="DRV0LOWr"><eq_pterm ptindx="FB3_12"/></macrocell><macrocell id="FB3_MC4" pin="FB3_MC4_PIN90" inreg="U1_ASedge" sigUse="0"/><macrocell id="FB3_MC5" pin="FB3_MC5_PIN89" sigUse="10" signal="DRV3HIGHr"><eq_pterm ptindx="FB3_16"/></macrocell><macrocell id="FB3_MC6" sigUse="10" signal="DRV0HIGHr"><eq_pterm ptindx="FB3_18"/></macrocell><macrocell id="FB3_MC7" sigUse="15" signal="U1_ADDR_reg4_SPECSIG"><eq_pterm ptindx="FB3_29"/><eq_pterm ptindx="FB3_30"/><eq_pterm ptindx="FB3_31"/><eq_pterm ptindx="FB3_35"/><eq_pterm ptindx="FB3_33"/><eq_pterm ptindx="FB3_37"/></macrocell><macrocell id="FB3_MC8" sigUse="15" signal="U1_ADDR_reg3_SPECSIG"><eq_pterm ptindx="FB3_24"/><eq_pterm ptindx="FB3_25"/><eq_pterm ptindx="FB3_26"/><eq_pterm ptindx="FB3_27"/><eq_pterm ptindx="FB3_28"/></macrocell><macrocell id="FB3_MC9" sigUse="15" signal="U1_ADDR_reg1_SPECSIG"><eq_pterm ptindx="FB3_19"/><eq_pterm ptindx="FB3_20"/><eq_pterm ptindx="FB3_21"/><eq_pterm ptindx="FB3_22"/><eq_pterm ptindx="FB3_23"/></macrocell><macrocell id="FB3_MC10" sigUse="15" signal="U1_ADDR_reg2_SPECSIG"><eq_pterm ptindx="FB3_13"/><eq_pterm ptindx="FB3_14"/><eq_pterm ptindx="FB3_15"/><eq_pterm ptindx="FB3_17"/></macrocell><macrocell id="FB3_MC11" sigUse="14" signal="U1_ADDR_reg0_SPECSIG"><eq_pterm ptindx="FB3_3"/><eq_pterm ptindx="FB3_5"/><eq_pterm ptindx="FB3_6"/><eq_pterm ptindx="FB3_9"/><eq_pterm ptindx="FB3_11"/></macrocell><macrocell id="FB3_MC12" sigUse="6" signal="U1_ADDR_reg5_SPECSIG"><eq_pterm ptindx="FB3_0"/><eq_pterm ptindx="FB3_1"/><eq_pterm ptindx="FB3_2"/></macrocell><macrocell id="FB3_MC13" sigUse="3" signal="U1_AutoInc"><eq_pterm ptindx="FB3_32"/></macrocell><macrocell id="FB3_MC14" pin="FB3_MC14_PIN88" sigUse="10" signal="DRV2LOWr"><eq_pterm ptindx="FB3_34"/></macrocell><macrocell id="FB3_MC15" sigUse="1" signal="U1_WRRDedge"><eq_pterm ptindx="FB3_36"/></macrocell><macrocell id="FB3_MC16" pin="FB3_MC16_PIN87" sigUse="10" signal="DRV2HIGHr"><eq_pterm ptindx="FB3_38"/></macrocell><fbinput id="FB3_I1" fbk="PIN" signal="AD0PIN_SPECSIG"/><fbinput id="FB3_I2" fbk="PIN" signal="AD1PIN_SPECSIG"/><fbinput id="FB3_I3" fbk="PIN" signal="AD2PIN_SPECSIG"/><fbinput id="FB3_I4" fbk="PIN" signal="AD3PIN_SPECSIG"/><fbinput id="FB3_I5" fbk="PIN" signal="AD4PIN_SPECSIG"/><fbinput id="FB3_I6" fbk="PIN" signal="AD5PIN_SPECSIG"/><fbinput id="FB3_I7" signal="AS"/><fbinput id="FB3_I8" signal="BUSReset"/><fbinput id="FB3_I9" signal="N_PZ_582"/><fbinput id="FB3_I10" signal="N_PZ_629"/><fbinput id="FB3_I11" signal="RD"/><fbinput id="FB3_I12" signal="U1_ADDR_reg0_SPECSIG"/><fbinput id="FB3_I13" signal="U1_ADDR_reg1_SPECSIG"/><fbinput id="FB3_I14" signal="U1_ADDR_reg2_SPECSIG"/><fbinput id="FB3_I15" signal="U1_ADDR_reg3_SPECSIG"/><fbinput id="FB3_I16" signal="U1_ADDR_reg4_SPECSIG"/><fbinput id="FB3_I17" signal="U1_ADDR_reg5_SPECSIG"/><fbinput id="FB3_I18" signal="U1_ADDR_reg6_SPECSIG"/><fbinput id="FB3_I19" signal="U1_ADDR_reg7_SPECSIG"/><fbinput id="FB3_I20" signal="U1_ASedge"/><fbinput id="FB3_I21" signal="U1_AutoInc"/><fbinput id="FB3_I22" signal="U1_WRRDedge"/><fbinput id="FB3_I23" signal="WR"/><PAL><pterm id="FB3_0"><signal id="BUSReset" negated="ON"/><signal id="U1_ADDR_reg5_SPECSIG"/></pterm><pterm id="FB3_1"><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg5_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB3_2"><signal id="BUSReset"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/></pterm><pterm id="FB3_3"><signal id="BUSReset" negated="ON"/><signal id="U1_ADDR_reg0_SPECSIG"/></pterm><pterm id="FB3_4"><signal id="N_PZ_582" negated="ON"/><signal id="U1_WRRDedge"/></pterm><pterm id="FB3_5"><signal id="AD0PIN_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/></pterm><pterm id="FB3_6"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/></pterm><pterm id="FB3_7"><signal id="U1_Enable_AD"/></pterm><pterm id="FB3_8"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB3_9"><signal id="BUSReset"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_10"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB3_11"><signal id="BUSReset"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_12"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB3_13"><signal id="BUSReset" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG"/></pterm><pterm id="FB3_14"><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg2_SPECSIG"/><signal id="AD2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB3_15"><signal id="BUSReset"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="AD2PIN_SPECSIG"/></pterm><pterm id="FB3_16"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB3_17"><signal id="BUSReset"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_18"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB3_19"><signal id="BUSReset" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/></pterm><pterm id="FB3_20"><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="AD1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB3_21"><signal id="BUSReset"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="AD1PIN_SPECSIG"/></pterm><pterm id="FB3_22"><signal id="BUSReset"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_23"><signal id="BUSReset"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_24"><signal id="BUSReset" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG"/></pterm><pterm id="FB3_25"><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg3_SPECSIG"/><signal id="AD3PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB3_26"><signal id="BUSReset"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="AD3PIN_SPECSIG"/></pterm><pterm id="FB3_27"><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_28"><signal id="BUSReset"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_29"><signal id="BUSReset" negated="ON"/></pterm><pterm id="FB3_30"><signal id="AS"/><signal id="U1_ADDR_reg4_SPECSIG" negated="ON"/></pterm><pterm id="FB3_31"><signal id="U1_ASedge" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG" negated="ON"/></pterm><pterm id="FB3_32"><signal id="AS"/></pterm><pterm id="FB3_33"><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="AD4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB3_34"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB3_35"><signal id="N_PZ_582" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG" negated="ON"/></pterm><pterm id="FB3_36"><signal id="N_PZ_582"/></pterm><pterm id="FB3_37"><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="U1_AutoInc"/><signal id="N_PZ_629"/></pterm><pterm id="FB3_38"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm></PAL><bct id="FB3_bct7"><eq_pterm ptindx="FB3_7"/></bct><equation id="DRV1LOWr"><d1><eq_pterm ptindx="FB3_8"/></d1></equation><equation id="DRV1HIGHr"><d1><eq_pterm ptindx="FB3_10"/></d1></equation><equation id="DRV0LOWr"><d1><eq_pterm ptindx="FB3_12"/></d1></equation><equation id="U1_ASedge"><inreg inputs="AS"/><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="DRV3HIGHr"><d1><eq_pterm ptindx="FB3_16"/></d1></equation><equation id="DRV0HIGHr"><d1><eq_pterm ptindx="FB3_18"/></d1></equation><equation id="U1_ADDR_reg4_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB3_29"/><eq_pterm ptindx="FB3_30"/><eq_pterm ptindx="FB3_31"/><eq_pterm ptindx="FB3_35"/><eq_pterm ptindx="FB3_33"/><eq_pterm ptindx="FB3_37"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U1_ADDR_reg3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_24"/><eq_pterm ptindx="FB3_25"/><eq_pterm ptindx="FB3_26"/><eq_pterm ptindx="FB3_27"/><eq_pterm ptindx="FB3_28"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U1_ADDR_reg1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_19"/><eq_pterm ptindx="FB3_20"/><eq_pterm ptindx="FB3_21"/><eq_pterm ptindx="FB3_22"/><eq_pterm ptindx="FB3_23"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U1_ADDR_reg2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_13"/><eq_pterm ptindx="FB3_14"/><eq_pterm ptindx="FB3_15"/><eq_pterm ptindx="FB3_17"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U1_ADDR_reg0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_3"/><eq_pterm ptindx="FB3_5"/><eq_pterm ptindx="FB3_6"/><eq_pterm ptindx="FB3_9"/><eq_pterm ptindx="FB3_11"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U1_ADDR_reg5_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_0"/><eq_pterm ptindx="FB3_1"/><eq_pterm ptindx="FB3_2"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U1_AutoInc" negated="ON"><d1><eq_pterm ptindx="FB3_32"/></d1><clk negated="ON"><fastsig signal="Mclk"/></clk><ce><eq_pterm ptindx="FB3_4"/></ce><prld ptindx="GND"/></equation><equation id="DRV2LOWr"><d1><eq_pterm ptindx="FB3_34"/></d1></equation><equation id="U1_WRRDedge"><d1><eq_pterm ptindx="FB3_36"/></d1><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="DRV2HIGHr"><d1><eq_pterm ptindx="FB3_38"/></d1></equation></fblock><fblock id="FB4" pinUse="7"><macrocell id="FB4_MC1" sigUse="9" signal="U3_U1DAVr_SPECSIG"><eq_pterm ptindx="FB4_9"/><eq_pterm ptindx="FB4_11"/><eq_pterm ptindx="FB4_8"/><eq_pterm ptindx="FB4_10"/></macrocell><macrocell id="FB4_MC2" pin="FB4_MC2_PIN106" sigUse="6" signal="U3_U3_EncReg3_SPECSIG"><eq_pterm ptindx="FB4_35"/><eq_pterm ptindx="FB4_33"/></macrocell><macrocell id="FB4_MC3" pin="FB4_MC3_PIN107" sigUse="2" signal="R1clk"><eq_pterm ptindx="FB4_12"/></macrocell><macrocell id="FB4_MC4" sigUse="9" signal="U3_U1SS_SPECSIG"><eq_pterm ptindx="FB4_13"/><eq_pterm ptindx="FB4_14"/><eq_pterm ptindx="FB4_16"/><eq_pterm ptindx="FB4_15"/></macrocell><macrocell id="FB4_MC5" pin="FB4_MC5_PIN111" sigUse="4" signal="Motor_Power_n"><eq_pterm ptindx="FB4_1"/><eq_pterm ptindx="FB4_2"/></macrocell><macrocell id="FB4_MC6" sigUse="6" signal="U3_U3_EncReg2_SPECSIG"><eq_pterm ptindx="FB4_32"/><eq_pterm ptindx="FB4_31"/></macrocell><macrocell id="FB4_MC7" sigUse="6" signal="U3_U3_EncReg1_SPECSIG"><eq_pterm ptindx="FB4_30"/><eq_pterm ptindx="FB4_29"/></macrocell><macrocell id="FB4_MC8" sigUse="6" signal="U3_U3_EncReg0_SPECSIG"><eq_pterm ptindx="FB4_28"/><eq_pterm ptindx="FB4_27"/></macrocell><macrocell id="FB4_MC9" sigUse="4" signal="U3_U1BitCounter0_SPECSIG"><eq_pterm ptindx="FB4_25"/><eq_pterm ptindx="FB4_24"/></macrocell><macrocell id="FB4_MC10" sigUse="5" signal="U3_U1BitCounter1_SPECSIG"><eq_pterm ptindx="FB4_26"/><eq_pterm ptindx="FB4_23"/></macrocell><macrocell id="FB4_MC11" sigUse="6" signal="U3_U1BitCounter2_SPECSIG"><eq_pterm ptindx="FB4_20"/><eq_pterm ptindx="FB4_21"/><eq_pterm ptindx="FB4_22"/></macrocell><macrocell id="FB4_MC12" sigUse="7" signal="U3_U1BitCounter3_SPECSIG"><eq_pterm ptindx="FB4_17"/><eq_pterm ptindx="FB4_18"/><eq_pterm ptindx="FB4_19"/></macrocell><macrocell id="FB4_MC13" pin="FB4_MC13_PIN112" sigUse="3" signal="Motor4_Phase_B_LIN"><eq_pterm ptindx="FB4_5"/><eq_pterm ptindx="FB4_6"/></macrocell><macrocell id="FB4_MC14" pin="FB4_MC14_PIN113" sigUse="3" signal="Motor4_Phase_B_HIN"><eq_pterm ptindx="FB4_34"/></macrocell><macrocell id="FB4_MC15" pin="FB4_MC15_PIN114" sigUse="3" signal="Motor4_Phase_A_LIN"><eq_pterm ptindx="FB4_4"/><eq_pterm ptindx="FB4_3"/></macrocell><macrocell id="FB4_MC16" pin="FB4_MC16_PIN116" sigUse="3" signal="Motor4_Phase_A_HIN"><eq_pterm ptindx="FB4_38"/></macrocell><fbinput id="FB4_I1" fbk="PIN" signal="AD0PIN_SPECSIG"/><fbinput id="FB4_I2" fbk="PIN" signal="AD2PIN_SPECSIG"/><fbinput id="FB4_I3" signal="BUSReset"/><fbinput id="FB4_I4" signal="DRVCTLw"/><fbinput id="FB4_I5" signal="GPIO8"/><fbinput id="FB4_I6" signal="Motor_Power_n"/><fbinput id="FB4_I7" signal="N_PZ_579"/><fbinput id="FB4_I8" signal="R1data"/><fbinput id="FB4_I9" signal="R1enable"/><fbinput id="FB4_I10" signal="R3clk"/><fbinput id="FB4_I11" signal="U3_NET282"/><fbinput id="FB4_I12" signal="U3_U1BitCounter0_SPECSIG"/><fbinput id="FB4_I13" signal="U3_U1BitCounter1_SPECSIG"/><fbinput id="FB4_I14" signal="U3_U1BitCounter2_SPECSIG"/><fbinput id="FB4_I15" signal="U3_U1BitCounter3_SPECSIG"/><fbinput id="FB4_I16" signal="U3_U1DAVr_SPECSIG"/><fbinput id="FB4_I17" signal="U3_U1SS_SPECSIG"/><fbinput id="FB4_I18" signal="U3_U3_EncReg0_SPECSIG"/><fbinput id="FB4_I19" signal="U3_U3_EncReg1_SPECSIG"/><fbinput id="FB4_I20" signal="U3_U3_EncReg2_SPECSIG"/><fbinput id="FB4_I21" signal="U3_U3_EncReg3_SPECSIG"/><fbinput id="FB4_I22" signal="U4M30_SPECSIG"/><fbinput id="FB4_I23" signal="U4M31_SPECSIG"/><PAL><pterm id="FB4_0"><signal id="R1enable"/></pterm><pterm id="FB4_1"><signal id="BUSReset"/><signal id="DRVCTLw"/><signal id="AD2PIN_SPECSIG"/></pterm><pterm id="FB4_2"><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/><signal id="Motor_Power_n" negated="ON"/></pterm><pterm id="FB4_3"><signal id="GPIO8" negated="ON"/><signal id="U4M30_SPECSIG"/></pterm><pterm id="FB4_4"><signal id="GPIO8"/><signal id="U4M31_SPECSIG"/></pterm><pterm id="FB4_5"><signal id="GPIO8"/><signal id="U4M30_SPECSIG"/></pterm><pterm id="FB4_6"><signal id="GPIO8" negated="ON"/><signal id="U4M31_SPECSIG"/></pterm><pterm id="FB4_7"><signal id="xPUP_0" negated="ON"/></pterm><pterm id="FB4_8"><signal id="R3clk"/><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter0_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter1_SPECSIG"/><signal id="U3_U1BitCounter2_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter3_SPECSIG"/></pterm><pterm id="FB4_9"><signal id="U3_U1DAVr_SPECSIG"/><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_10"><signal id="R3clk"/><signal id="BUSReset"/><signal id="U3_U1BitCounter0_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter1_SPECSIG"/><signal id="U3_U1BitCounter2_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter3_SPECSIG"/><signal id="DRVCTLw" negated="ON"/></pterm><pterm id="FB4_11"><signal id="U3_U1DAVr_SPECSIG"/><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/></pterm><pterm id="FB4_12"><signal id="R3clk"/></pterm><pterm id="FB4_13"><signal id="BUSReset" negated="ON"/></pterm><pterm id="FB4_14"><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="AD0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_15"><signal id="R3clk"/><signal id="U3_U1BitCounter0_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter1_SPECSIG"/><signal id="U3_U1BitCounter2_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter3_SPECSIG"/></pterm><pterm id="FB4_16"><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="DRVCTLw" negated="ON"/></pterm><pterm id="FB4_17"><signal id="BUSReset" negated="ON"/><signal id="U3_U1BitCounter3_SPECSIG"/></pterm><pterm id="FB4_18"><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter3_SPECSIG"/></pterm><pterm id="FB4_19"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1BitCounter0_SPECSIG"/><signal id="U3_NET282"/><signal id="U3_U1BitCounter1_SPECSIG"/><signal id="U3_U1BitCounter2_SPECSIG"/></pterm><pterm id="FB4_20"><signal id="BUSReset" negated="ON"/><signal id="U3_U1BitCounter2_SPECSIG"/></pterm><pterm id="FB4_21"><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="U3_U1BitCounter2_SPECSIG"/></pterm><pterm id="FB4_22"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1BitCounter0_SPECSIG"/><signal id="U3_NET282"/><signal id="U3_U1BitCounter1_SPECSIG"/></pterm><pterm id="FB4_23"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1BitCounter0_SPECSIG"/><signal id="U3_NET282"/></pterm><pterm id="FB4_24"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1BitCounter0_SPECSIG" negated="ON"/><signal id="U3_NET282"/></pterm><pterm id="FB4_25"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1BitCounter0_SPECSIG"/><signal id="U3_NET282" negated="ON"/></pterm><pterm id="FB4_26"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1BitCounter1_SPECSIG"/></pterm><pterm id="FB4_27"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="R1data"/></pterm><pterm id="FB4_28"><signal id="U3_U3_EncReg0_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB4_29"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg0_SPECSIG"/></pterm><pterm id="FB4_30"><signal id="U3_U3_EncReg1_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB4_31"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg1_SPECSIG"/></pterm><pterm id="FB4_32"><signal id="U3_U3_EncReg2_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB4_33"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg2_SPECSIG"/></pterm><pterm id="FB4_34"><signal id="GPIO8"/><signal id="U4M30_SPECSIG" negated="ON"/><signal id="U4M31_SPECSIG"/></pterm><pterm id="FB4_35"><signal id="U3_U3_EncReg3_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB4_38"><signal id="GPIO8"/><signal id="U4M30_SPECSIG"/><signal id="U4M31_SPECSIG" negated="ON"/></pterm></PAL><bct id="FB4_bct7" negated="ON"><eq_pterm ptindx="FB4_7"/></bct><equation id="U3_U1DAVr_SPECSIG"><d2><eq_pterm ptindx="FB4_9"/><eq_pterm ptindx="FB4_11"/><eq_pterm ptindx="FB4_8"/><eq_pterm ptindx="FB4_10"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U3_EncReg3_SPECSIG"><d2><eq_pterm ptindx="FB4_35"/><eq_pterm ptindx="FB4_33"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="R1clk"><d1><eq_pterm ptindx="FB4_12"/></d1><oe><eq_pterm ptindx="FB4_0"/></oe></equation><equation id="U3_U1SS_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB4_13"/><eq_pterm ptindx="FB4_14"/><eq_pterm ptindx="FB4_16"/><eq_pterm ptindx="FB4_15"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="Motor_Power_n" negated="ON"><d2><eq_pterm ptindx="FB4_1"/><eq_pterm ptindx="FB4_2"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><set><eq_pterm ptindx="FB4_7"/></set><prld ptindx="VCC"/></equation><equation id="U3_U3_EncReg2_SPECSIG"><d2><eq_pterm ptindx="FB4_32"/><eq_pterm ptindx="FB4_31"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U3_EncReg1_SPECSIG"><d2><eq_pterm ptindx="FB4_30"/><eq_pterm ptindx="FB4_29"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U3_EncReg0_SPECSIG"><d2><eq_pterm ptindx="FB4_28"/><eq_pterm ptindx="FB4_27"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1BitCounter0_SPECSIG"><d2><eq_pterm ptindx="FB4_25"/><eq_pterm ptindx="FB4_24"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1BitCounter1_SPECSIG"><d1><eq_pterm ptindx="FB4_26"/></d1><d2><eq_pterm ptindx="FB4_23"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1BitCounter2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_20"/><eq_pterm ptindx="FB4_21"/><eq_pterm ptindx="FB4_22"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1BitCounter3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_17"/><eq_pterm ptindx="FB4_18"/><eq_pterm ptindx="FB4_19"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="Motor4_Phase_B_LIN" negated="ON"><d2><eq_pterm ptindx="FB4_5"/><eq_pterm ptindx="FB4_6"/></d2></equation><equation id="Motor4_Phase_B_HIN"><d1><eq_pterm ptindx="FB4_34"/></d1></equation><equation id="Motor4_Phase_A_LIN" negated="ON"><d2><eq_pterm ptindx="FB4_4"/><eq_pterm ptindx="FB4_3"/></d2></equation><equation id="Motor4_Phase_A_HIN"><d1><eq_pterm ptindx="FB4_38"/></d1></equation></fblock><fblock id="FB5" pinUse="0"><macrocell id="FB5_MC1"/><macrocell id="FB5_MC2" pin="FB5_MC2_PIN86" sigUse="30" signal="N_PZ_1049"><eq_pterm ptindx="FB5_4"/><eq_pterm ptindx="FB5_9"/><eq_pterm ptindx="FB5_14"/><eq_pterm ptindx="FB5_19"/><eq_pterm ptindx="FB5_0"/><eq_pterm ptindx="FB5_1"/><eq_pterm ptindx="FB5_2"/><eq_pterm ptindx="FB5_3"/><eq_pterm ptindx="FB5_8"/><eq_pterm ptindx="FB5_7"/><eq_pterm ptindx="FB5_6"/><eq_pterm ptindx="FB5_5"/><eq_pterm ptindx="FB5_13"/><eq_pterm ptindx="FB5_12"/><eq_pterm ptindx="FB5_11"/><eq_pterm ptindx="FB5_10"/><eq_pterm ptindx="FB5_18"/><eq_pterm ptindx="FB5_17"/><eq_pterm ptindx="FB5_16"/><eq_pterm ptindx="FB5_15"/><eq_pterm ptindx="FB5_23"/><eq_pterm ptindx="FB5_22"/><eq_pterm ptindx="FB5_21"/><eq_pterm ptindx="FB5_20"/></macrocell><macrocell id="FB5_MC3"/><macrocell id="FB5_MC4"/><macrocell id="FB5_MC5" sigUse="6" signal="U3_U2_EncReg6_SPECSIG"><eq_pterm ptindx="FB5_25"/><eq_pterm ptindx="FB5_24"/></macrocell><macrocell id="FB5_MC6"/><macrocell id="FB5_MC7"/><macrocell id="FB5_MC8"/><macrocell id="FB5_MC9"/><macrocell id="FB5_MC10" sigUse="3" signal="N_PZ_579"><eq_pterm ptindx="FB5_39"/><eq_pterm ptindx="FB5_38"/></macrocell><macrocell id="FB5_MC11" sigUse="6" signal="U3_U3_EncReg4_SPECSIG"><eq_pterm ptindx="FB5_37"/><eq_pterm ptindx="FB5_36"/></macrocell><macrocell id="FB5_MC12" sigUse="6" signal="U3_U3_EncReg7_SPECSIG"><eq_pterm ptindx="FB5_35"/><eq_pterm ptindx="FB5_34"/></macrocell><macrocell id="FB5_MC13" sigUse="6" signal="U3_U3_EncReg6_SPECSIG"><eq_pterm ptindx="FB5_33"/><eq_pterm ptindx="FB5_32"/></macrocell><macrocell id="FB5_MC14" sigUse="6" signal="U3_U2_EncReg7_SPECSIG"><eq_pterm ptindx="FB5_27"/><eq_pterm ptindx="FB5_26"/></macrocell><macrocell id="FB5_MC15" sigUse="6" signal="U3_U2_EncReg8_SPECSIG"><eq_pterm ptindx="FB5_29"/><eq_pterm ptindx="FB5_28"/></macrocell><macrocell id="FB5_MC16" sigUse="6" signal="U3_U3_EncReg5_SPECSIG"><eq_pterm ptindx="FB5_31"/><eq_pterm ptindx="FB5_30"/></macrocell><fbinput id="FB5_I1" signal="BUSReset"/><fbinput id="FB5_I2" signal="DRV0HIGHr"/><fbinput id="FB5_I3" signal="DRV0LOWr"/><fbinput id="FB5_I4" signal="DRV1HIGHr"/><fbinput id="FB5_I5" signal="DRV1LOWr"/><fbinput id="FB5_I6" signal="DRV2HIGHr"/><fbinput id="FB5_I7" signal="DRV2LOWr"/><fbinput id="FB5_I8" signal="DRV3HIGHr"/><fbinput id="FB5_I9" signal="DRV3LOWr"/><fbinput id="FB5_I10" signal="DRVSTATr"/><fbinput id="FB5_I11" signal="N_PZ_578"/><fbinput id="FB5_I12" signal="N_PZ_579"/><fbinput id="FB5_I13" signal="R0enable"/><fbinput id="FB5_I14" signal="R0flg"/><fbinput id="FB5_I15" signal="R1enable"/><fbinput id="FB5_I16" signal="R1flg"/><fbinput id="FB5_I17" signal="R2flg"/><fbinput id="FB5_I18" signal="R3flg"/><fbinput id="FB5_I19" signal="U3_NET282"/><fbinput id="FB5_I20" signal="U3_U2_EncReg4_SPECSIG"/><fbinput id="FB5_I21" signal="U3_U2_EncReg5_SPECSIG"/><fbinput id="FB5_I22" signal="U3_U2_EncReg6_SPECSIG"/><fbinput id="FB5_I23" signal="U3_U2_EncReg7_SPECSIG"/><fbinput id="FB5_I24" signal="U3_U2_EncReg8_SPECSIG"/><fbinput id="FB5_I25" signal="U3_U3_EncReg3_SPECSIG"/><fbinput id="FB5_I26" signal="U3_U3_EncReg4_SPECSIG"/><fbinput id="FB5_I27" signal="U3_U3_EncReg5_SPECSIG"/><fbinput id="FB5_I28" signal="U3_U3_EncReg6_SPECSIG"/><fbinput id="FB5_I29" signal="U3_U3_EncReg7_SPECSIG"/><fbinput id="FB5_I30" signal="U3_U4_EncReg4_SPECSIG"/><fbinput id="FB5_I31" signal="U3_U4_EncReg5_SPECSIG"/><fbinput id="FB5_I32" signal="U3_U4_EncReg6_SPECSIG"/><fbinput id="FB5_I33" signal="U3_U4_EncReg7_SPECSIG"/><fbinput id="FB5_I34" signal="U3_U5_EncReg4_SPECSIG"/><fbinput id="FB5_I35" signal="U3_U5_EncReg5_SPECSIG"/><fbinput id="FB5_I36" signal="U3_U5_EncReg6_SPECSIG"/><fbinput id="FB5_I37" signal="U3_U5_EncReg7_SPECSIG"/><fbinput id="FB5_I38" signal="U3_U6_PWRflgier"/><PAL><pterm id="FB5_0"><signal id="DRVSTATr"/><signal id="U3_U6_PWRflgier"/><signal id="R0flg" negated="ON"/></pterm><pterm id="FB5_1"><signal id="DRVSTATr"/><signal id="U3_U6_PWRflgier"/><signal id="R1flg" negated="ON"/></pterm><pterm id="FB5_2"><signal id="DRVSTATr"/><signal id="U3_U6_PWRflgier"/><signal id="R2flg" negated="ON"/></pterm><pterm id="FB5_3"><signal id="DRVSTATr"/><signal id="U3_U6_PWRflgier"/><signal id="R3flg" negated="ON"/></pterm><pterm id="FB5_4"><signal id="DRV0HIGHr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_5"><signal id="U3_U2_EncReg4_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_6"><signal id="U3_U2_EncReg5_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_7"><signal id="U3_U2_EncReg6_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_8"><signal id="U3_U2_EncReg7_SPECSIG" negated="ON"/><signal id="DRV0LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_9"><signal id="DRV1HIGHr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_10"><signal id="U3_U3_EncReg4_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_11"><signal id="U3_U3_EncReg5_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_12"><signal id="U3_U3_EncReg6_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_13"><signal id="U3_U3_EncReg7_SPECSIG" negated="ON"/><signal id="DRV1LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_14"><signal id="DRV2HIGHr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_15"><signal id="U3_U4_EncReg4_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_16"><signal id="U3_U4_EncReg5_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_17"><signal id="U3_U4_EncReg6_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_18"><signal id="U3_U4_EncReg7_SPECSIG" negated="ON"/><signal id="DRV2LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_19"><signal id="DRV3HIGHr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_20"><signal id="U3_U5_EncReg4_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_21"><signal id="U3_U5_EncReg5_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_22"><signal id="U3_U5_EncReg6_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_23"><signal id="U3_U5_EncReg7_SPECSIG" negated="ON"/><signal id="DRV3LOWr"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB5_24"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg5_SPECSIG"/></pterm><pterm id="FB5_25"><signal id="U3_U2_EncReg6_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB5_26"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg6_SPECSIG"/></pterm><pterm id="FB5_27"><signal id="U3_U2_EncReg7_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB5_28"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R0enable" negated="ON"/><signal id="U3_U2_EncReg7_SPECSIG"/></pterm><pterm id="FB5_29"><signal id="U3_U2_EncReg8_SPECSIG"/><signal id="N_PZ_578"/></pterm><pterm id="FB5_30"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg4_SPECSIG"/></pterm><pterm id="FB5_31"><signal id="U3_U3_EncReg5_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB5_32"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg5_SPECSIG"/></pterm><pterm id="FB5_33"><signal id="U3_U3_EncReg6_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB5_34"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg6_SPECSIG"/></pterm><pterm id="FB5_35"><signal id="U3_U3_EncReg7_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB5_36"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg3_SPECSIG"/></pterm><pterm id="FB5_37"><signal id="U3_U3_EncReg4_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB5_38"><signal id="BUSReset"/><signal id="R1enable"/></pterm><pterm id="FB5_39"><signal id="BUSReset"/><signal id="U3_NET282" negated="ON"/></pterm></PAL><equation id="N_PZ_1049"><d2><eq_pterm ptindx="FB5_4"/><eq_pterm ptindx="FB5_9"/><eq_pterm ptindx="FB5_14"/><eq_pterm ptindx="FB5_19"/><eq_pterm ptindx="FB5_0"/><eq_pterm ptindx="FB5_1"/><eq_pterm ptindx="FB5_2"/><eq_pterm ptindx="FB5_3"/><eq_pterm ptindx="FB5_8"/><eq_pterm ptindx="FB5_7"/><eq_pterm ptindx="FB5_6"/><eq_pterm ptindx="FB5_5"/><eq_pterm ptindx="FB5_13"/><eq_pterm ptindx="FB5_12"/><eq_pterm ptindx="FB5_11"/><eq_pterm ptindx="FB5_10"/><eq_pterm ptindx="FB5_18"/><eq_pterm ptindx="FB5_17"/><eq_pterm ptindx="FB5_16"/><eq_pterm ptindx="FB5_15"/><eq_pterm ptindx="FB5_23"/><eq_pterm ptindx="FB5_22"/><eq_pterm ptindx="FB5_21"/><eq_pterm ptindx="FB5_20"/></d2></equation><equation id="U3_U2_EncReg6_SPECSIG"><d2><eq_pterm ptindx="FB5_25"/><eq_pterm ptindx="FB5_24"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="N_PZ_579"><d2><eq_pterm ptindx="FB5_39"/><eq_pterm ptindx="FB5_38"/></d2></equation><equation id="U3_U3_EncReg4_SPECSIG"><d2><eq_pterm ptindx="FB5_37"/><eq_pterm ptindx="FB5_36"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U3_EncReg7_SPECSIG"><d2><eq_pterm ptindx="FB5_35"/><eq_pterm ptindx="FB5_34"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U3_EncReg6_SPECSIG"><d2><eq_pterm ptindx="FB5_33"/><eq_pterm ptindx="FB5_32"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U2_EncReg7_SPECSIG"><d2><eq_pterm ptindx="FB5_27"/><eq_pterm ptindx="FB5_26"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U2_EncReg8_SPECSIG"><d2><eq_pterm ptindx="FB5_29"/><eq_pterm ptindx="FB5_28"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U3_EncReg5_SPECSIG"><d2><eq_pterm ptindx="FB5_31"/><eq_pterm ptindx="FB5_30"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB6" pinUse="2"><macrocell id="FB6_MC1" pin="FB6_MC1_PIN67" sigUse="6" signal="U1_ADDR_reg6_SPECSIG"><eq_pterm ptindx="FB6_30"/><eq_pterm ptindx="FB6_31"/><eq_pterm ptindx="FB6_32"/></macrocell><macrocell id="FB6_MC2" sigUse="4" signal="U4M30_SPECSIG"><eq_pterm ptindx="FB6_25"/><eq_pterm ptindx="FB6_27"/></macrocell><macrocell id="FB6_MC3" sigUse="4" signal="U4M21_SPECSIG"><eq_pterm ptindx="FB6_23"/><eq_pterm ptindx="FB6_24"/></macrocell><macrocell id="FB6_MC4" sigUse="4" signal="U4M20_SPECSIG"><eq_pterm ptindx="FB6_21"/><eq_pterm ptindx="FB6_22"/></macrocell><macrocell id="FB6_MC5" sigUse="4" signal="U4M11_SPECSIG"><eq_pterm ptindx="FB6_19"/><eq_pterm ptindx="FB6_20"/></macrocell><macrocell id="FB6_MC6" sigUse="4" signal="U4M10_SPECSIG"><eq_pterm ptindx="FB6_17"/><eq_pterm ptindx="FB6_18"/></macrocell><macrocell id="FB6_MC7" sigUse="4" signal="U4M00_SPECSIG"><eq_pterm ptindx="FB6_15"/><eq_pterm ptindx="FB6_16"/></macrocell><macrocell id="FB6_MC8" sigUse="4" signal="U4M01_SPECSIG"><eq_pterm ptindx="FB6_13"/><eq_pterm ptindx="FB6_14"/></macrocell><macrocell id="FB6_MC9" sigUse="4" signal="U3_U6_PWRflgier"><eq_pterm ptindx="FB6_11"/><eq_pterm ptindx="FB6_12"/></macrocell><macrocell id="FB6_MC10" sigUse="3" signal="U3_U1divider3_SPECSIG"><eq_pterm ptindx="FB6_26"/></macrocell><macrocell id="FB6_MC11" sigUse="6" signal="U3_NET282"><eq_pterm ptindx="FB6_8"/><eq_pterm ptindx="FB6_10"/><eq_pterm ptindx="FB6_9"/></macrocell><macrocell id="FB6_MC12" sigUse="5" signal="U3_U1CEr_SPECSIG"><eq_pterm ptindx="FB6_5"/><eq_pterm ptindx="FB6_7"/><eq_pterm ptindx="FB6_6"/></macrocell><macrocell id="FB6_MC13" sigUse="6" signal="U3_U1divider1_SPECSIG"><eq_pterm ptindx="FB6_2"/><eq_pterm ptindx="FB6_4"/><eq_pterm ptindx="FB6_3"/></macrocell><macrocell id="FB6_MC14" sigUse="5" signal="U3_U1divider0_SPECSIG"><eq_pterm ptindx="FB6_0"/><eq_pterm ptindx="FB6_1"/></macrocell><macrocell id="FB6_MC15" sigUse="3" signal="U3_U1divider2_SPECSIG"><eq_pterm ptindx="FB6_36"/></macrocell><macrocell id="FB6_MC16" pin="FB6_MC16_PIN69" sigUse="4" signal="U4M31_SPECSIG"><eq_pterm ptindx="FB6_28"/><eq_pterm ptindx="FB6_29"/></macrocell><fbinput id="FB6_I1" fbk="PIN" signal="AD0PIN_SPECSIG"/><fbinput id="FB6_I2" fbk="PIN" signal="AD1PIN_SPECSIG"/><fbinput id="FB6_I3" fbk="PIN" signal="AD2PIN_SPECSIG"/><fbinput id="FB6_I4" fbk="PIN" signal="AD3PIN_SPECSIG"/><fbinput id="FB6_I5" fbk="PIN" signal="AD4PIN_SPECSIG"/><fbinput id="FB6_I6" fbk="PIN" signal="AD5PIN_SPECSIG"/><fbinput id="FB6_I7" fbk="PIN" signal="AD6PIN_SPECSIG"/><fbinput id="FB6_I8" fbk="PIN" signal="AD7PIN_SPECSIG"/><fbinput id="FB6_I9" signal="AS"/><fbinput id="FB6_I10" signal="BUSReset"/><fbinput id="FB6_I11" signal="DRVCTLw"/><fbinput id="FB6_I12" signal="DRVMTRCTLw"/><fbinput id="FB6_I13" signal="N_PZ_582"/><fbinput id="FB6_I14" signal="R3clk"/><fbinput id="FB6_I15" signal="U1_ADDR_reg6_SPECSIG"/><fbinput id="FB6_I16" signal="U1_ASedge"/><fbinput id="FB6_I17" signal="U3_U1SS_SPECSIG"/><fbinput id="FB6_I18" signal="U3_U1divider0_SPECSIG"/><fbinput id="FB6_I19" signal="U3_U1divider1_SPECSIG"/><fbinput id="FB6_I20" signal="U3_U1divider2_SPECSIG"/><fbinput id="FB6_I21" signal="U3_U1divider3_SPECSIG"/><fbinput id="FB6_I22" signal="U3_U6_PWRflgier"/><fbinput id="FB6_I23" signal="U4M00_SPECSIG"/><fbinput id="FB6_I24" signal="U4M01_SPECSIG"/><fbinput id="FB6_I25" signal="U4M10_SPECSIG"/><fbinput id="FB6_I26" signal="U4M11_SPECSIG"/><fbinput id="FB6_I27" signal="U4M20_SPECSIG"/><fbinput id="FB6_I28" signal="U4M21_SPECSIG"/><fbinput id="FB6_I29" signal="U4M30_SPECSIG"/><fbinput id="FB6_I30" signal="U4M31_SPECSIG"/><PAL><pterm id="FB6_0"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="U3_U1divider0_SPECSIG"/></pterm><pterm id="FB6_1"><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1divider2_SPECSIG" negated="ON"/><signal id="U3_U1divider0_SPECSIG" negated="ON"/><signal id="U3_U1divider3_SPECSIG" negated="ON"/></pterm><pterm id="FB6_2"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="U3_U1divider1_SPECSIG"/></pterm><pterm id="FB6_3"><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1divider2_SPECSIG" negated="ON"/><signal id="U3_U1divider0_SPECSIG" negated="ON"/><signal id="U3_U1divider3_SPECSIG" negated="ON"/><signal id="U3_U1divider1_SPECSIG"/></pterm><pterm id="FB6_4"><signal id="U3_U1SS_SPECSIG"/><signal id="U3_U1divider2_SPECSIG" negated="ON"/><signal id="U3_U1divider0_SPECSIG"/><signal id="U3_U1divider3_SPECSIG" negated="ON"/><signal id="U3_U1divider1_SPECSIG" negated="ON"/></pterm><pterm id="FB6_5"><signal id="BUSReset"/><signal id="U3_U1divider2_SPECSIG"/></pterm><pterm id="FB6_6"><signal id="BUSReset"/><signal id="U3_U1divider0_SPECSIG"/><signal id="U3_U1divider1_SPECSIG"/></pterm><pterm id="FB6_7"><signal id="BUSReset"/><signal id="U3_U1divider3_SPECSIG"/></pterm><pterm id="FB6_8"><signal id="R3clk"/><signal id="BUSReset"/><signal id="U3_U1divider2_SPECSIG"/></pterm><pterm id="FB6_9"><signal id="R3clk"/><signal id="BUSReset"/><signal id="U3_U1divider0_SPECSIG"/><signal id="U3_U1divider1_SPECSIG"/></pterm><pterm id="FB6_10"><signal id="R3clk"/><signal id="BUSReset"/><signal id="U3_U1divider3_SPECSIG"/></pterm><pterm id="FB6_11"><signal id="BUSReset"/><signal id="DRVCTLw"/><signal id="AD1PIN_SPECSIG"/></pterm><pterm id="FB6_12"><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/><signal id="U3_U6_PWRflgier"/></pterm><pterm id="FB6_13"><signal id="BUSReset"/><signal id="AD1PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_14"><signal id="BUSReset"/><signal id="DRVMTRCTLw" negated="ON"/><signal id="U4M01_SPECSIG"/></pterm><pterm id="FB6_15"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_16"><signal id="BUSReset"/><signal id="U4M00_SPECSIG"/><signal id="DRVMTRCTLw" negated="ON"/></pterm><pterm id="FB6_17"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_18"><signal id="BUSReset"/><signal id="DRVMTRCTLw" negated="ON"/><signal id="U4M10_SPECSIG"/></pterm><pterm id="FB6_19"><signal id="BUSReset"/><signal id="AD3PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_20"><signal id="BUSReset"/><signal id="DRVMTRCTLw" negated="ON"/><signal id="U4M11_SPECSIG"/></pterm><pterm id="FB6_21"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_22"><signal id="BUSReset"/><signal id="DRVMTRCTLw" negated="ON"/><signal id="U4M20_SPECSIG"/></pterm><pterm id="FB6_23"><signal id="BUSReset"/><signal id="AD5PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_24"><signal id="BUSReset"/><signal id="DRVMTRCTLw" negated="ON"/><signal id="U4M21_SPECSIG"/></pterm><pterm id="FB6_25"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_26"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="U3_U1divider3_SPECSIG"/></pterm><pterm id="FB6_27"><signal id="BUSReset"/><signal id="DRVMTRCTLw" negated="ON"/><signal id="U4M30_SPECSIG"/></pterm><pterm id="FB6_28"><signal id="BUSReset"/><signal id="AD7PIN_SPECSIG"/><signal id="DRVMTRCTLw"/></pterm><pterm id="FB6_29"><signal id="BUSReset"/><signal id="DRVMTRCTLw" negated="ON"/><signal id="U4M31_SPECSIG"/></pterm><pterm id="FB6_30"><signal id="BUSReset" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG"/></pterm><pterm id="FB6_31"><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg6_SPECSIG"/><signal id="AD6PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB6_32"><signal id="BUSReset"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="AD6PIN_SPECSIG"/></pterm><pterm id="FB6_36"><signal id="BUSReset"/><signal id="U3_U1SS_SPECSIG" negated="ON"/><signal id="U3_U1divider2_SPECSIG"/></pterm></PAL><equation id="U1_ADDR_reg6_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB6_30"/><eq_pterm ptindx="FB6_31"/><eq_pterm ptindx="FB6_32"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M30_SPECSIG"><d2><eq_pterm ptindx="FB6_25"/><eq_pterm ptindx="FB6_27"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M21_SPECSIG"><d2><eq_pterm ptindx="FB6_23"/><eq_pterm ptindx="FB6_24"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M20_SPECSIG"><d2><eq_pterm ptindx="FB6_21"/><eq_pterm ptindx="FB6_22"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M11_SPECSIG"><d2><eq_pterm ptindx="FB6_19"/><eq_pterm ptindx="FB6_20"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M10_SPECSIG"><d2><eq_pterm ptindx="FB6_17"/><eq_pterm ptindx="FB6_18"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M00_SPECSIG"><d2><eq_pterm ptindx="FB6_15"/><eq_pterm ptindx="FB6_16"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M01_SPECSIG"><d2><eq_pterm ptindx="FB6_13"/><eq_pterm ptindx="FB6_14"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U6_PWRflgier"><d2><eq_pterm ptindx="FB6_11"/><eq_pterm ptindx="FB6_12"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1divider3_SPECSIG"><d1><eq_pterm ptindx="FB6_26"/></d1><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_NET282"><d2><eq_pterm ptindx="FB6_8"/><eq_pterm ptindx="FB6_10"/><eq_pterm ptindx="FB6_9"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1CEr_SPECSIG"><d2><eq_pterm ptindx="FB6_5"/><eq_pterm ptindx="FB6_7"/><eq_pterm ptindx="FB6_6"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1divider1_SPECSIG"><d2><eq_pterm ptindx="FB6_2"/><eq_pterm ptindx="FB6_4"/><eq_pterm ptindx="FB6_3"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1divider0_SPECSIG"><d2><eq_pterm ptindx="FB6_0"/><eq_pterm ptindx="FB6_1"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U1divider2_SPECSIG"><d1><eq_pterm ptindx="FB6_36"/></d1><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U4M31_SPECSIG"><d2><eq_pterm ptindx="FB6_28"/><eq_pterm ptindx="FB6_29"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB7" pinUse="2"><macrocell id="FB7_MC1" sigUse="6" signal="U3_U3_EncReg8_SPECSIG"><eq_pterm ptindx="FB7_1"/><eq_pterm ptindx="FB7_0"/></macrocell><macrocell id="FB7_MC2" pin="FB7_MC2_PIN79" sigUse="6" signal="U1_ADDR_reg7_SPECSIG"><eq_pterm ptindx="FB7_30"/><eq_pterm ptindx="FB7_31"/><eq_pterm ptindx="FB7_32"/></macrocell><macrocell id="FB7_MC3" pin="FB7_MC3_PIN78" sigUse="6" signal="U3_U5_EncReg8_SPECSIG"><eq_pterm ptindx="FB7_29"/><eq_pterm ptindx="FB7_28"/></macrocell><macrocell id="FB7_MC4" sigUse="6" signal="U3_U4_EncReg0_SPECSIG"><eq_pterm ptindx="FB7_3"/><eq_pterm ptindx="FB7_2"/></macrocell><macrocell id="FB7_MC5" sigUse="6" signal="U3_U5_EncReg7_SPECSIG"><eq_pterm ptindx="FB7_27"/><eq_pterm ptindx="FB7_26"/></macrocell><macrocell id="FB7_MC6" sigUse="6" signal="U3_U5_EncReg6_SPECSIG"><eq_pterm ptindx="FB7_25"/><eq_pterm ptindx="FB7_24"/></macrocell><macrocell id="FB7_MC7" sigUse="6" signal="U3_U5_EncReg5_SPECSIG"><eq_pterm ptindx="FB7_23"/><eq_pterm ptindx="FB7_22"/></macrocell><macrocell id="FB7_MC8" sigUse="6" signal="U3_U5_EncReg4_SPECSIG"><eq_pterm ptindx="FB7_21"/><eq_pterm ptindx="FB7_20"/></macrocell><macrocell id="FB7_MC9" sigUse="6" signal="U3_U5_EncReg3_SPECSIG"><eq_pterm ptindx="FB7_19"/><eq_pterm ptindx="FB7_18"/></macrocell><macrocell id="FB7_MC10" sigUse="6" signal="U3_U5_EncReg2_SPECSIG"><eq_pterm ptindx="FB7_17"/><eq_pterm ptindx="FB7_16"/></macrocell><macrocell id="FB7_MC11" sigUse="6" signal="U3_U5_EncReg1_SPECSIG"><eq_pterm ptindx="FB7_15"/><eq_pterm ptindx="FB7_14"/></macrocell><macrocell id="FB7_MC12" sigUse="6" signal="U3_U5_EncReg0_SPECSIG"><eq_pterm ptindx="FB7_13"/><eq_pterm ptindx="FB7_12"/></macrocell><macrocell id="FB7_MC13" sigUse="6" signal="U3_U4_EncReg8_SPECSIG"><eq_pterm ptindx="FB7_11"/><eq_pterm ptindx="FB7_10"/></macrocell><macrocell id="FB7_MC14" sigUse="6" signal="U3_U4_EncReg3_SPECSIG"><eq_pterm ptindx="FB7_9"/><eq_pterm ptindx="FB7_8"/></macrocell><macrocell id="FB7_MC15" sigUse="6" signal="U3_U4_EncReg1_SPECSIG"><eq_pterm ptindx="FB7_5"/><eq_pterm ptindx="FB7_4"/></macrocell><macrocell id="FB7_MC16" sigUse="6" signal="U3_U4_EncReg2_SPECSIG"><eq_pterm ptindx="FB7_7"/><eq_pterm ptindx="FB7_6"/></macrocell><fbinput id="FB7_I1" fbk="PIN" signal="AD7PIN_SPECSIG"/><fbinput id="FB7_I2" signal="AS"/><fbinput id="FB7_I3" signal="BUSReset"/><fbinput id="FB7_I4" signal="N_PZ_579"/><fbinput id="FB7_I5" signal="N_PZ_580"/><fbinput id="FB7_I6" signal="N_PZ_581"/><fbinput id="FB7_I7" signal="N_PZ_582"/><fbinput id="FB7_I8" signal="R1enable"/><fbinput id="FB7_I9" signal="R2data"/><fbinput id="FB7_I10" signal="R2enable"/><fbinput id="FB7_I11" signal="R3data"/><fbinput id="FB7_I12" signal="R3enable"/><fbinput id="FB7_I13" signal="U1_ADDR_reg7_SPECSIG"/><fbinput id="FB7_I14" signal="U1_ASedge"/><fbinput id="FB7_I15" signal="U3_NET282"/><fbinput id="FB7_I16" signal="U3_U3_EncReg7_SPECSIG"/><fbinput id="FB7_I17" signal="U3_U3_EncReg8_SPECSIG"/><fbinput id="FB7_I18" signal="U3_U4_EncReg0_SPECSIG"/><fbinput id="FB7_I19" signal="U3_U4_EncReg1_SPECSIG"/><fbinput id="FB7_I20" signal="U3_U4_EncReg2_SPECSIG"/><fbinput id="FB7_I21" signal="U3_U4_EncReg3_SPECSIG"/><fbinput id="FB7_I22" signal="U3_U4_EncReg7_SPECSIG"/><fbinput id="FB7_I23" signal="U3_U4_EncReg8_SPECSIG"/><fbinput id="FB7_I24" signal="U3_U5_EncReg0_SPECSIG"/><fbinput id="FB7_I25" signal="U3_U5_EncReg1_SPECSIG"/><fbinput id="FB7_I26" signal="U3_U5_EncReg2_SPECSIG"/><fbinput id="FB7_I27" signal="U3_U5_EncReg3_SPECSIG"/><fbinput id="FB7_I28" signal="U3_U5_EncReg4_SPECSIG"/><fbinput id="FB7_I29" signal="U3_U5_EncReg5_SPECSIG"/><fbinput id="FB7_I30" signal="U3_U5_EncReg6_SPECSIG"/><fbinput id="FB7_I31" signal="U3_U5_EncReg7_SPECSIG"/><fbinput id="FB7_I32" signal="U3_U5_EncReg8_SPECSIG"/><PAL><pterm id="FB7_0"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R1enable" negated="ON"/><signal id="U3_U3_EncReg7_SPECSIG"/></pterm><pterm id="FB7_1"><signal id="U3_U3_EncReg8_SPECSIG"/><signal id="N_PZ_579"/></pterm><pterm id="FB7_2"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="R2data"/></pterm><pterm id="FB7_3"><signal id="U3_U4_EncReg0_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB7_4"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg0_SPECSIG"/></pterm><pterm id="FB7_5"><signal id="U3_U4_EncReg1_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB7_6"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg1_SPECSIG"/></pterm><pterm id="FB7_7"><signal id="U3_U4_EncReg2_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB7_8"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg2_SPECSIG"/></pterm><pterm id="FB7_9"><signal id="U3_U4_EncReg3_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB7_10"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R2enable" negated="ON"/><signal id="U3_U4_EncReg7_SPECSIG"/></pterm><pterm id="FB7_11"><signal id="U3_U4_EncReg8_SPECSIG"/><signal id="N_PZ_580"/></pterm><pterm id="FB7_12"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="R3data"/></pterm><pterm id="FB7_13"><signal id="U3_U5_EncReg0_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_14"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg0_SPECSIG"/></pterm><pterm id="FB7_15"><signal id="U3_U5_EncReg1_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_16"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg1_SPECSIG"/></pterm><pterm id="FB7_17"><signal id="U3_U5_EncReg2_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_18"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg2_SPECSIG"/></pterm><pterm id="FB7_19"><signal id="U3_U5_EncReg3_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_20"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg3_SPECSIG"/></pterm><pterm id="FB7_21"><signal id="U3_U5_EncReg4_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_22"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg4_SPECSIG"/></pterm><pterm id="FB7_23"><signal id="U3_U5_EncReg5_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_24"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg5_SPECSIG"/></pterm><pterm id="FB7_25"><signal id="U3_U5_EncReg6_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_26"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg6_SPECSIG"/></pterm><pterm id="FB7_27"><signal id="U3_U5_EncReg7_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_28"><signal id="BUSReset"/><signal id="U3_NET282"/><signal id="R3enable" negated="ON"/><signal id="U3_U5_EncReg7_SPECSIG"/></pterm><pterm id="FB7_29"><signal id="U3_U5_EncReg8_SPECSIG"/><signal id="N_PZ_581"/></pterm><pterm id="FB7_30"><signal id="BUSReset" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG"/></pterm><pterm id="FB7_31"><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg7_SPECSIG"/><signal id="AD7PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB7_32"><signal id="BUSReset"/><signal id="AS" negated="ON"/><signal id="U1_ASedge"/><signal id="N_PZ_582"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/><signal id="AD7PIN_SPECSIG"/></pterm></PAL><equation id="U3_U3_EncReg8_SPECSIG"><d2><eq_pterm ptindx="FB7_1"/><eq_pterm ptindx="FB7_0"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U1_ADDR_reg7_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB7_30"/><eq_pterm ptindx="FB7_31"/><eq_pterm ptindx="FB7_32"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg8_SPECSIG"><d2><eq_pterm ptindx="FB7_29"/><eq_pterm ptindx="FB7_28"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg0_SPECSIG"><d2><eq_pterm ptindx="FB7_3"/><eq_pterm ptindx="FB7_2"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg7_SPECSIG"><d2><eq_pterm ptindx="FB7_27"/><eq_pterm ptindx="FB7_26"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg6_SPECSIG"><d2><eq_pterm ptindx="FB7_25"/><eq_pterm ptindx="FB7_24"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg5_SPECSIG"><d2><eq_pterm ptindx="FB7_23"/><eq_pterm ptindx="FB7_22"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg4_SPECSIG"><d2><eq_pterm ptindx="FB7_21"/><eq_pterm ptindx="FB7_20"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg3_SPECSIG"><d2><eq_pterm ptindx="FB7_19"/><eq_pterm ptindx="FB7_18"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg2_SPECSIG"><d2><eq_pterm ptindx="FB7_17"/><eq_pterm ptindx="FB7_16"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg1_SPECSIG"><d2><eq_pterm ptindx="FB7_15"/><eq_pterm ptindx="FB7_14"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U5_EncReg0_SPECSIG"><d2><eq_pterm ptindx="FB7_13"/><eq_pterm ptindx="FB7_12"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg8_SPECSIG"><d2><eq_pterm ptindx="FB7_11"/><eq_pterm ptindx="FB7_10"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg3_SPECSIG"><d2><eq_pterm ptindx="FB7_9"/><eq_pterm ptindx="FB7_8"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg1_SPECSIG"><d2><eq_pterm ptindx="FB7_5"/><eq_pterm ptindx="FB7_4"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="U3_U4_EncReg2_SPECSIG"><d2><eq_pterm ptindx="FB7_7"/><eq_pterm ptindx="FB7_6"/></d2><clk><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB8" pinUse="3"><macrocell id="FB8_MC1" sigUse="2" signal="N_PZ_582"><eq_pterm ptindx="FB8_8"/></macrocell><macrocell id="FB8_MC2" pin="FB8_MC2_PIN71" sigUse="4" signal="R0enable"><eq_pterm ptindx="FB8_1"/><eq_pterm ptindx="FB8_2"/></macrocell><macrocell id="FB8_MC3" pin="FB8_MC3_PIN72" sigUse="4" signal="R1enable"><eq_pterm ptindx="FB8_3"/><eq_pterm ptindx="FB8_4"/></macrocell><macrocell id="FB8_MC4"/><macrocell id="FB8_MC5"/><macrocell id="FB8_MC6"/><macrocell id="FB8_MC7"/><macrocell id="FB8_MC8" sigUse="10" signal="DRVVALV1w"><eq_pterm ptindx="FB8_22"/></macrocell><macrocell id="FB8_MC9" sigUse="10" signal="DRVVALV0w"><eq_pterm ptindx="FB8_24"/></macrocell><macrocell id="FB8_MC10" sigUse="10" signal="DRVSTATr"><eq_pterm ptindx="FB8_26"/></macrocell><macrocell id="FB8_MC11" sigUse="10" signal="DRVMTRCTLw"><eq_pterm ptindx="FB8_28"/></macrocell><macrocell id="FB8_MC12" sigUse="10" signal="DRVCTLw"><eq_pterm ptindx="FB8_30"/></macrocell><macrocell id="FB8_MC13" sigUse="10" signal="DRV3LOWr"><eq_pterm ptindx="FB8_32"/></macrocell><macrocell id="FB8_MC14" sigUse="8" signal="U1_Enable_AD"><eq_pterm ptindx="FB8_7"/><eq_pterm ptindx="FB8_9"/></macrocell><macrocell id="FB8_MC15" sigUse="5" signal="N_PZ_629"><eq_pterm ptindx="FB8_5"/><eq_pterm ptindx="FB8_6"/></macrocell><macrocell id="FB8_MC16" pin="FB8_MC16_PIN74" sigUse="1" signal="BusINT"/><fbinput id="FB8_I1" fbk="PIN" signal="AD4PIN_SPECSIG"/><fbinput id="FB8_I2" fbk="PIN" signal="AD5PIN_SPECSIG"/><fbinput id="FB8_I3" signal="AS"/><fbinput id="FB8_I4" signal="BUSReset"/><fbinput id="FB8_I5" signal="DRVCTLw"/><fbinput id="FB8_I6" signal="N_PZ_1049"/><fbinput id="FB8_I7" signal="R0enable"/><fbinput id="FB8_I8" signal="R1enable"/><fbinput id="FB8_I9" signal="RD"/><fbinput id="FB8_I10" signal="U1_ADDR_reg0_SPECSIG"/><fbinput id="FB8_I11" signal="U1_ADDR_reg1_SPECSIG"/><fbinput id="FB8_I12" signal="U1_ADDR_reg2_SPECSIG"/><fbinput id="FB8_I13" signal="U1_ADDR_reg3_SPECSIG"/><fbinput id="FB8_I14" signal="U1_ADDR_reg4_SPECSIG"/><fbinput id="FB8_I15" signal="U1_ADDR_reg5_SPECSIG"/><fbinput id="FB8_I16" signal="U1_ADDR_reg6_SPECSIG"/><fbinput id="FB8_I17" signal="U1_ADDR_reg7_SPECSIG"/><fbinput id="FB8_I18" signal="U1_ASedge"/><fbinput id="FB8_I19" signal="U1_WRRDedge"/><fbinput id="FB8_I20" signal="WR"/><PAL><pterm id="FB8_0"><signal id="N_PZ_1049"/></pterm><pterm id="FB8_1"><signal id="BUSReset"/><signal id="DRVCTLw"/><signal id="AD4PIN_SPECSIG"/></pterm><pterm id="FB8_2"><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/><signal id="R0enable" negated="ON"/></pterm><pterm id="FB8_3"><signal id="BUSReset"/><signal id="DRVCTLw"/><signal id="AD5PIN_SPECSIG"/></pterm><pterm id="FB8_4"><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/><signal id="R1enable" negated="ON"/></pterm><pterm id="FB8_5"><signal id="RD"/><signal id="WR"/><signal id="AS"/><signal id="U1_WRRDedge" negated="ON"/></pterm><pterm id="FB8_6"><signal id="RD"/><signal id="WR"/><signal id="U1_ASedge" negated="ON"/><signal id="U1_WRRDedge" negated="ON"/></pterm><pterm id="FB8_7"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB8_8"><signal id="RD"/><signal id="WR"/></pterm><pterm id="FB8_9"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB8_22"><signal id="RD"/><signal id="WR" negated="ON"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB8_24"><signal id="RD"/><signal id="WR" negated="ON"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB8_26"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB8_28"><signal id="RD"/><signal id="WR" negated="ON"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB8_30"><signal id="RD"/><signal id="WR" negated="ON"/><signal id="U1_ADDR_reg0_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg2_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm><pterm id="FB8_32"><signal id="RD" negated="ON"/><signal id="WR"/><signal id="U1_ADDR_reg0_SPECSIG"/><signal id="U1_ADDR_reg2_SPECSIG"/><signal id="U1_ADDR_reg3_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg4_SPECSIG"/><signal id="U1_ADDR_reg5_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg6_SPECSIG" negated="ON"/><signal id="U1_ADDR_reg1_SPECSIG"/><signal id="U1_ADDR_reg7_SPECSIG" negated="ON"/></pterm></PAL><equation id="N_PZ_582"><d1><eq_pterm ptindx="FB8_8"/></d1></equation><equation id="R0enable" negated="ON"><d2><eq_pterm ptindx="FB8_1"/><eq_pterm ptindx="FB8_2"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><set><eq_pterm ptindx="FB4_7"/></set><prld ptindx="VCC"/></equation><equation id="R1enable" negated="ON"><d2><eq_pterm ptindx="FB8_3"/><eq_pterm ptindx="FB8_4"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><set><eq_pterm ptindx="FB4_7"/></set><prld ptindx="VCC"/></equation><equation id="DRVVALV1w"><d1><eq_pterm ptindx="FB8_22"/></d1></equation><equation id="DRVVALV0w"><d1><eq_pterm ptindx="FB8_24"/></d1></equation><equation id="DRVSTATr"><d1><eq_pterm ptindx="FB8_26"/></d1></equation><equation id="DRVMTRCTLw"><d1><eq_pterm ptindx="FB8_28"/></d1></equation><equation id="DRVCTLw"><d1><eq_pterm ptindx="FB8_30"/></d1></equation><equation id="DRV3LOWr"><d1><eq_pterm ptindx="FB8_32"/></d1></equation><equation id="U1_Enable_AD"><d2><eq_pterm ptindx="FB8_7"/><eq_pterm ptindx="FB8_9"/></d2></equation><equation id="N_PZ_629"><d2><eq_pterm ptindx="FB8_5"/><eq_pterm ptindx="FB8_6"/></d2></equation><equation id="BusINT"><d2><eq_pterm ptindx="GND"/></d2><oe><eq_pterm ptindx="FB8_0"/></oe></equation></fblock><fblock id="FB9" pinUse="1"><macrocell id="FB9_MC1" pin="FB9_MC1_PIN122"/><macrocell id="FB9_MC2"/><macrocell id="FB9_MC3" pin="FB9_MC3_PIN121"/><macrocell id="FB9_MC4"/><macrocell id="FB9_MC5" pin="FB9_MC5_PIN120" sigUse="3" signal="Motor3_Phase_A_HIN"><eq_pterm ptindx="FB9_16"/></macrocell><macrocell id="FB9_MC6"/><macrocell id="FB9_MC7"/><macrocell id="FB9_MC8"/><macrocell id="FB9_MC9"/><macrocell id="FB9_MC10"/><macrocell id="FB9_MC11"/><macrocell id="FB9_MC12"/><macrocell id="FB9_MC13"/><macrocell id="FB9_MC14"/><macrocell id="FB9_MC15"/><macrocell id="FB9_MC16"/><fbinput id="FB9_I1" signal="GPIO8"/><fbinput id="FB9_I2" signal="U4M20_SPECSIG"/><fbinput id="FB9_I3" signal="U4M21_SPECSIG"/><PAL><pterm id="FB9_16"><signal id="GPIO8"/><signal id="U4M20_SPECSIG"/><signal id="U4M21_SPECSIG" negated="ON"/></pterm></PAL><equation id="Motor3_Phase_A_HIN"><d1><eq_pterm ptindx="FB9_16"/></d1></equation></fblock><fblock id="FB10" pinUse="3"><macrocell id="FB10_MC1"/><macrocell id="FB10_MC2"/><macrocell id="FB10_MC3" pin="FB10_MC3_PIN131"/><macrocell id="FB10_MC4" pin="FB10_MC4_PIN132" sigUse="3" signal="Motor2_Phase_B_LIN"><eq_pterm ptindx="FB10_2"/><eq_pterm ptindx="FB10_3"/></macrocell><macrocell id="FB10_MC5"/><macrocell id="FB10_MC6"/><macrocell id="FB10_MC7"/><macrocell id="FB10_MC8"/><macrocell id="FB10_MC9"/><macrocell id="FB10_MC10"/><macrocell id="FB10_MC11"/><macrocell id="FB10_MC12"/><macrocell id="FB10_MC13"/><macrocell id="FB10_MC14"/><macrocell id="FB10_MC15" pin="FB10_MC15_PIN133" sigUse="3" signal="Motor2_Phase_B_HIN"><eq_pterm ptindx="FB10_36"/></macrocell><macrocell id="FB10_MC16" pin="FB10_MC16_PIN134" sigUse="3" signal="Motor2_Phase_A_LIN"><eq_pterm ptindx="FB10_1"/><eq_pterm ptindx="FB10_0"/></macrocell><fbinput id="FB10_I1" signal="GPIO8"/><fbinput id="FB10_I2" signal="U4M10_SPECSIG"/><fbinput id="FB10_I3" signal="U4M11_SPECSIG"/><PAL><pterm id="FB10_0"><signal id="GPIO8" negated="ON"/><signal id="U4M10_SPECSIG"/></pterm><pterm id="FB10_1"><signal id="GPIO8"/><signal id="U4M11_SPECSIG"/></pterm><pterm id="FB10_2"><signal id="GPIO8"/><signal id="U4M10_SPECSIG"/></pterm><pterm id="FB10_3"><signal id="GPIO8" negated="ON"/><signal id="U4M11_SPECSIG"/></pterm><pterm id="FB10_36"><signal id="GPIO8"/><signal id="U4M10_SPECSIG" negated="ON"/><signal id="U4M11_SPECSIG"/></pterm></PAL><equation id="Motor2_Phase_B_LIN" negated="ON"><d2><eq_pterm ptindx="FB10_2"/><eq_pterm ptindx="FB10_3"/></d2></equation><equation id="Motor2_Phase_B_HIN"><d1><eq_pterm ptindx="FB10_36"/></d1></equation><equation id="Motor2_Phase_A_LIN" negated="ON"><d2><eq_pterm ptindx="FB10_1"/><eq_pterm ptindx="FB10_0"/></d2></equation></fblock><fblock id="FB11" pinUse="3"><macrocell id="FB11_MC1"/><macrocell id="FB11_MC2"/><macrocell id="FB11_MC3"/><macrocell id="FB11_MC4"/><macrocell id="FB11_MC5" pin="FB11_MC5_PIN117" sigUse="3" signal="Motor3_Phase_B_LIN"><eq_pterm ptindx="FB11_2"/><eq_pterm ptindx="FB11_3"/></macrocell><macrocell id="FB11_MC6"/><macrocell id="FB11_MC7"/><macrocell id="FB11_MC8"/><macrocell id="FB11_MC9"/><macrocell id="FB11_MC10"/><macrocell id="FB11_MC11"/><macrocell id="FB11_MC12"/><macrocell id="FB11_MC13"/><macrocell id="FB11_MC14"/><macrocell id="FB11_MC15" pin="FB11_MC15_PIN118" sigUse="3" signal="Motor3_Phase_B_HIN"><eq_pterm ptindx="FB11_36"/></macrocell><macrocell id="FB11_MC16" pin="FB11_MC16_PIN119" sigUse="3" signal="Motor3_Phase_A_LIN"><eq_pterm ptindx="FB11_1"/><eq_pterm ptindx="FB11_0"/></macrocell><fbinput id="FB11_I1" signal="GPIO8"/><fbinput id="FB11_I2" signal="U4M20_SPECSIG"/><fbinput id="FB11_I3" signal="U4M21_SPECSIG"/><PAL><pterm id="FB11_0"><signal id="GPIO8" negated="ON"/><signal id="U4M20_SPECSIG"/></pterm><pterm id="FB11_1"><signal id="GPIO8"/><signal id="U4M21_SPECSIG"/></pterm><pterm id="FB11_2"><signal id="GPIO8"/><signal id="U4M20_SPECSIG"/></pterm><pterm id="FB11_3"><signal id="GPIO8" negated="ON"/><signal id="U4M21_SPECSIG"/></pterm><pterm id="FB11_36"><signal id="GPIO8"/><signal id="U4M20_SPECSIG" negated="ON"/><signal id="U4M21_SPECSIG"/></pterm></PAL><equation id="Motor3_Phase_B_LIN" negated="ON"><d2><eq_pterm ptindx="FB11_2"/><eq_pterm ptindx="FB11_3"/></d2></equation><equation id="Motor3_Phase_B_HIN"><d1><eq_pterm ptindx="FB11_36"/></d1></equation><equation id="Motor3_Phase_A_LIN" negated="ON"><d2><eq_pterm ptindx="FB11_1"/><eq_pterm ptindx="FB11_0"/></d2></equation></fblock><fblock id="FB12" pinUse="4"><macrocell id="FB12_MC1" pin="FB12_MC1_PIN139" sigUse="3" signal="Motor1_Phase_A_LIN"><eq_pterm ptindx="FB12_1"/><eq_pterm ptindx="FB12_0"/></macrocell><macrocell id="FB12_MC2"/><macrocell id="FB12_MC3" pin="FB12_MC3_PIN138" sigUse="3" signal="Motor1_Phase_B_HIN"><eq_pterm ptindx="FB12_12"/></macrocell><macrocell id="FB12_MC4" pin="FB12_MC4_PIN137" sigUse="3" signal="Motor1_Phase_B_LIN"><eq_pterm ptindx="FB12_2"/><eq_pterm ptindx="FB12_3"/></macrocell><macrocell id="FB12_MC5"/><macrocell id="FB12_MC6"/><macrocell id="FB12_MC7"/><macrocell id="FB12_MC8"/><macrocell id="FB12_MC9"/><macrocell id="FB12_MC10"/><macrocell id="FB12_MC11"/><macrocell id="FB12_MC12"/><macrocell id="FB12_MC13" pin="FB12_MC13_PIN136" sigUse="3" signal="Motor2_Phase_A_HIN"><eq_pterm ptindx="FB12_32"/></macrocell><macrocell id="FB12_MC14"/><macrocell id="FB12_MC15"/><macrocell id="FB12_MC16"/><fbinput id="FB12_I1" signal="GPIO8"/><fbinput id="FB12_I2" signal="U4M00_SPECSIG"/><fbinput id="FB12_I3" signal="U4M01_SPECSIG"/><fbinput id="FB12_I4" signal="U4M10_SPECSIG"/><fbinput id="FB12_I5" signal="U4M11_SPECSIG"/><PAL><pterm id="FB12_0"><signal id="GPIO8" negated="ON"/><signal id="U4M00_SPECSIG"/></pterm><pterm id="FB12_1"><signal id="GPIO8"/><signal id="U4M01_SPECSIG"/></pterm><pterm id="FB12_2"><signal id="GPIO8"/><signal id="U4M00_SPECSIG"/></pterm><pterm id="FB12_3"><signal id="GPIO8" negated="ON"/><signal id="U4M01_SPECSIG"/></pterm><pterm id="FB12_12"><signal id="GPIO8"/><signal id="U4M00_SPECSIG" negated="ON"/><signal id="U4M01_SPECSIG"/></pterm><pterm id="FB12_32"><signal id="GPIO8"/><signal id="U4M10_SPECSIG"/><signal id="U4M11_SPECSIG" negated="ON"/></pterm></PAL><equation id="Motor1_Phase_A_LIN" negated="ON"><d2><eq_pterm ptindx="FB12_1"/><eq_pterm ptindx="FB12_0"/></d2></equation><equation id="Motor1_Phase_B_HIN"><d1><eq_pterm ptindx="FB12_12"/></d1></equation><equation id="Motor1_Phase_B_LIN" negated="ON"><d2><eq_pterm ptindx="FB12_2"/><eq_pterm ptindx="FB12_3"/></d2></equation><equation id="Motor2_Phase_A_HIN"><d1><eq_pterm ptindx="FB12_32"/></d1></equation></fblock><fblock id="FB13" pinUse="4"><macrocell id="FB13_MC1" pin="FB13_MC1_PIN61"/><macrocell id="FB13_MC2"/><macrocell id="FB13_MC3" pin="FB13_MC3_PIN62"/><macrocell id="FB13_MC4"/><macrocell id="FB13_MC5"/><macrocell id="FB13_MC6"/><macrocell id="FB13_MC7"/><macrocell id="FB13_MC8"/><macrocell id="FB13_MC9"/><macrocell id="FB13_MC10"/><macrocell id="FB13_MC11"/><macrocell id="FB13_MC12"/><macrocell id="FB13_MC13"/><macrocell id="FB13_MC14" pin="FB13_MC14_PIN65"/><macrocell id="FB13_MC15"/><macrocell id="FB13_MC16" pin="FB13_MC16_PIN66"/><PAL/></fblock><fblock id="FB14" pinUse="4"><macrocell id="FB14_MC1"/><macrocell id="FB14_MC2" pin="FB14_MC2_PIN47" sigUse="0" signal="AS0"/><macrocell id="FB14_MC3" pin="FB14_MC3_PIN46" sigUse="0" signal="Current_enable"/><macrocell id="FB14_MC4"/><macrocell id="FB14_MC5"/><macrocell id="FB14_MC6"/><macrocell id="FB14_MC7"/><macrocell id="FB14_MC8"/><macrocell id="FB14_MC9"/><macrocell id="FB14_MC10"/><macrocell id="FB14_MC11"/><macrocell id="FB14_MC12"/><macrocell id="FB14_MC13"/><macrocell id="FB14_MC14" pin="FB14_MC14_PIN44" sigUse="4" signal="R3enable"><eq_pterm ptindx="FB14_2"/><eq_pterm ptindx="FB14_3"/></macrocell><macrocell id="FB14_MC15"/><macrocell id="FB14_MC16" pin="FB14_MC16_PIN43" sigUse="4" signal="R2enable"><eq_pterm ptindx="FB14_0"/><eq_pterm ptindx="FB14_1"/></macrocell><fbinput id="FB14_I1" fbk="PIN" signal="AD6PIN_SPECSIG"/><fbinput id="FB14_I2" fbk="PIN" signal="AD7PIN_SPECSIG"/><fbinput id="FB14_I3" signal="BUSReset"/><fbinput id="FB14_I4" signal="DRVCTLw"/><fbinput id="FB14_I5" signal="R2enable"/><fbinput id="FB14_I6" signal="R3enable"/><PAL><pterm id="FB14_0"><signal id="BUSReset"/><signal id="DRVCTLw"/><signal id="AD6PIN_SPECSIG"/></pterm><pterm id="FB14_1"><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/><signal id="R2enable" negated="ON"/></pterm><pterm id="FB14_2"><signal id="BUSReset"/><signal id="DRVCTLw"/><signal id="AD7PIN_SPECSIG"/></pterm><pterm id="FB14_3"><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/><signal id="R3enable" negated="ON"/></pterm></PAL><equation id="AS0"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="Current_enable"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="R3enable" negated="ON"><d2><eq_pterm ptindx="FB14_2"/><eq_pterm ptindx="FB14_3"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><set><eq_pterm ptindx="FB4_7"/></set><prld ptindx="VCC"/></equation><equation id="R2enable" negated="ON"><d2><eq_pterm ptindx="FB14_0"/><eq_pterm ptindx="FB14_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><set><eq_pterm ptindx="FB4_7"/></set><prld ptindx="VCC"/></equation></fblock><fblock id="FB15" pinUse="1"><macrocell id="FB15_MC1"/><macrocell id="FB15_MC2"/><macrocell id="FB15_MC3" pin="FB15_MC3_PIN60" sigUse="2" signal="R0clk"><eq_pterm ptindx="FB15_12"/></macrocell><macrocell id="FB15_MC4"/><macrocell id="FB15_MC5" pin="FB15_MC5_PIN56"/><macrocell id="FB15_MC6"/><macrocell id="FB15_MC7"/><macrocell id="FB15_MC8"/><macrocell id="FB15_MC9"/><macrocell id="FB15_MC10"/><macrocell id="FB15_MC11"/><macrocell id="FB15_MC12"/><macrocell id="FB15_MC13"/><macrocell id="FB15_MC14"/><macrocell id="FB15_MC15"/><macrocell id="FB15_MC16"/><fbinput id="FB15_I1" signal="R0enable"/><fbinput id="FB15_I2" signal="R3clk"/><PAL><pterm id="FB15_0"><signal id="R0enable"/></pterm><pterm id="FB15_12"><signal id="R3clk"/></pterm></PAL><equation id="R0clk"><d1><eq_pterm ptindx="FB15_12"/></d1><oe><eq_pterm ptindx="FB15_0"/></oe></equation></fblock><fblock id="FB16" pinUse="2"><macrocell id="FB16_MC1"/><macrocell id="FB16_MC2" pin="FB16_MC2_PIN48" sigUse="0" signal="AS1"/><macrocell id="FB16_MC3"/><macrocell id="FB16_MC4" pin="FB16_MC4_PIN49" sigUse="0" signal="AS2"/><macrocell id="FB16_MC5"/><macrocell id="FB16_MC6"/><macrocell id="FB16_MC7"/><macrocell id="FB16_MC8"/><macrocell id="FB16_MC9"/><macrocell id="FB16_MC10"/><macrocell id="FB16_MC11"/><macrocell id="FB16_MC12"/><macrocell id="FB16_MC13"/><macrocell id="FB16_MC14"/><macrocell id="FB16_MC15"/><macrocell id="FB16_MC16"/><PAL/><equation id="AS1"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="AS2"><d2><eq_pterm ptindx="GND"/></d2></equation></fblock><fblock id="FB17" pinUse="5"><macrocell id="FB17_MC1"/><macrocell id="FB17_MC2"/><macrocell id="FB17_MC3" pin="FB17_MC3_PIN6" sigUse="7" signal="PhaseB_High_7"><eq_pterm ptindx="FB17_8"/><eq_pterm ptindx="FB17_11"/><eq_pterm ptindx="FB17_9"/><eq_pterm ptindx="FB17_10"/></macrocell><macrocell id="FB17_MC4" pin="FB17_MC4_PIN5" sigUse="7" signal="PhaseB_Low_7"><eq_pterm ptindx="FB17_13"/><eq_pterm ptindx="FB17_16"/><eq_pterm ptindx="FB17_15"/><eq_pterm ptindx="FB17_14"/></macrocell><macrocell id="FB17_MC5" pin="FB17_MC5_PIN4" sigUse="8" signal="PhaseA_High_8"><eq_pterm ptindx="FB17_0"/><eq_pterm ptindx="FB17_3"/><eq_pterm ptindx="FB17_2"/><eq_pterm ptindx="FB17_1"/></macrocell><macrocell id="FB17_MC6"/><macrocell id="FB17_MC7"/><macrocell id="FB17_MC8"/><macrocell id="FB17_MC9"/><macrocell id="FB17_MC10"/><macrocell id="FB17_MC11"/><macrocell id="FB17_MC12"/><macrocell id="FB17_MC13"/><macrocell id="FB17_MC14"/><macrocell id="FB17_MC15" pin="FB17_MC15_PIN2" sigUse="8" signal="PhaseA_Low_8"><eq_pterm ptindx="FB17_4"/><eq_pterm ptindx="FB17_7"/><eq_pterm ptindx="FB17_5"/><eq_pterm ptindx="FB17_6"/></macrocell><macrocell id="FB17_MC16" pin="FB17_MC16_PIN1" sigUse="7" signal="PhaseB_High_8"><eq_pterm ptindx="FB17_12"/><eq_pterm ptindx="FB17_7"/><eq_pterm ptindx="FB17_5"/><eq_pterm ptindx="FB17_6"/></macrocell><fbinput id="FB17_I1" fbk="PIN" signal="AD4PIN_SPECSIG"/><fbinput id="FB17_I2" fbk="PIN" signal="AD5PIN_SPECSIG"/><fbinput id="FB17_I3" fbk="PIN" signal="AD6PIN_SPECSIG"/><fbinput id="FB17_I4" fbk="PIN" signal="AD7PIN_SPECSIG"/><fbinput id="FB17_I5" signal="BUSReset"/><fbinput id="FB17_I6" signal="DRVVALV0w"/><fbinput id="FB17_I7" signal="DRVVALV1w"/><fbinput id="FB17_I8" signal="PhaseA_High_8"/><fbinput id="FB17_I9" signal="PhaseA_Low_8"/><fbinput id="FB17_I10" signal="PhaseB_High_7"/><fbinput id="FB17_I11" signal="PhaseB_High_8"/><fbinput id="FB17_I12" signal="PhaseB_Low_7"/><fbinput id="FB17_I13" signal="PhaseB_Low_8"/><PAL><pterm id="FB17_0"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_High_8"/></pterm><pterm id="FB17_1"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG" negated="ON"/><signal id="AD7PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_8" negated="ON"/><signal id="PhaseB_Low_8"/></pterm><pterm id="FB17_2"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG"/><signal id="AD7PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_High_8" negated="ON"/></pterm><pterm id="FB17_3"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_8"/></pterm><pterm id="FB17_4"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_Low_8"/></pterm><pterm id="FB17_5"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG"/><signal id="AD7PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_8"/><signal id="PhaseB_Low_8" negated="ON"/></pterm><pterm id="FB17_6"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG" negated="ON"/><signal id="AD7PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_Low_8" negated="ON"/></pterm><pterm id="FB17_7"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_8"/></pterm><pterm id="FB17_8"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_7"/></pterm><pterm id="FB17_9"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_7"/><signal id="PhaseB_Low_7" negated="ON"/></pterm><pterm id="FB17_10"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_Low_7" negated="ON"/></pterm><pterm id="FB17_11"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_7"/></pterm><pterm id="FB17_12"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_8"/></pterm><pterm id="FB17_13"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_Low_7"/></pterm><pterm id="FB17_14"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_7" negated="ON"/><signal id="PhaseB_Low_7"/></pterm><pterm id="FB17_15"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_High_7" negated="ON"/></pterm><pterm id="FB17_16"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_7"/></pterm></PAL><equation id="PhaseB_High_7"><d2><eq_pterm ptindx="FB17_8"/><eq_pterm ptindx="FB17_11"/><eq_pterm ptindx="FB17_9"/><eq_pterm ptindx="FB17_10"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_Low_7"><d2><eq_pterm ptindx="FB17_13"/><eq_pterm ptindx="FB17_16"/><eq_pterm ptindx="FB17_15"/><eq_pterm ptindx="FB17_14"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_8"><d2><eq_pterm ptindx="FB17_0"/><eq_pterm ptindx="FB17_3"/><eq_pterm ptindx="FB17_2"/><eq_pterm ptindx="FB17_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_Low_8"><d2><eq_pterm ptindx="FB17_4"/><eq_pterm ptindx="FB17_7"/><eq_pterm ptindx="FB17_5"/><eq_pterm ptindx="FB17_6"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_High_8"><d2><eq_pterm ptindx="FB17_12"/><eq_pterm ptindx="FB17_7"/><eq_pterm ptindx="FB17_5"/><eq_pterm ptindx="FB17_6"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB18" pinUse="6"><macrocell id="FB18_MC1" pin="FB18_MC1_PIN7" sigUse="8" signal="PhaseA_Low_7"><eq_pterm ptindx="FB18_12"/><eq_pterm ptindx="FB18_15"/><eq_pterm ptindx="FB18_13"/><eq_pterm ptindx="FB18_14"/></macrocell><macrocell id="FB18_MC2" pin="FB18_MC2_PIN8" sigUse="8" signal="PhaseA_High_7"><eq_pterm ptindx="FB18_4"/><eq_pterm ptindx="FB18_7"/><eq_pterm ptindx="FB18_6"/><eq_pterm ptindx="FB18_5"/></macrocell><macrocell id="FB18_MC3" pin="FB18_MC3_PIN9" sigUse="7" signal="PhaseB_Low_6"><eq_pterm ptindx="FB18_17"/><eq_pterm ptindx="FB18_3"/><eq_pterm ptindx="FB18_2"/><eq_pterm ptindx="FB18_1"/></macrocell><macrocell id="FB18_MC4" pin="FB18_MC4_PIN10" sigUse="7" signal="PhaseB_High_6"><eq_pterm ptindx="FB18_16"/><eq_pterm ptindx="FB18_11"/><eq_pterm ptindx="FB18_9"/><eq_pterm ptindx="FB18_10"/></macrocell><macrocell id="FB18_MC5"/><macrocell id="FB18_MC6"/><macrocell id="FB18_MC7"/><macrocell id="FB18_MC8"/><macrocell id="FB18_MC9"/><macrocell id="FB18_MC10"/><macrocell id="FB18_MC11"/><macrocell id="FB18_MC12"/><macrocell id="FB18_MC13"/><macrocell id="FB18_MC14"/><macrocell id="FB18_MC15" pin="FB18_MC15_PIN11" sigUse="8" signal="PhaseA_Low_6"><eq_pterm ptindx="FB18_8"/><eq_pterm ptindx="FB18_11"/><eq_pterm ptindx="FB18_9"/><eq_pterm ptindx="FB18_10"/></macrocell><macrocell id="FB18_MC16" pin="FB18_MC16_PIN12" sigUse="8" signal="PhaseA_High_6"><eq_pterm ptindx="FB18_0"/><eq_pterm ptindx="FB18_3"/><eq_pterm ptindx="FB18_2"/><eq_pterm ptindx="FB18_1"/></macrocell><fbinput id="FB18_I1" fbk="PIN" signal="AD2PIN_SPECSIG"/><fbinput id="FB18_I2" fbk="PIN" signal="AD3PIN_SPECSIG"/><fbinput id="FB18_I3" fbk="PIN" signal="AD4PIN_SPECSIG"/><fbinput id="FB18_I4" fbk="PIN" signal="AD5PIN_SPECSIG"/><fbinput id="FB18_I5" signal="BUSReset"/><fbinput id="FB18_I6" signal="DRVVALV0w"/><fbinput id="FB18_I7" signal="DRVVALV1w"/><fbinput id="FB18_I8" signal="PhaseA_High_6"/><fbinput id="FB18_I9" signal="PhaseA_High_7"/><fbinput id="FB18_I10" signal="PhaseA_Low_6"/><fbinput id="FB18_I11" signal="PhaseA_Low_7"/><fbinput id="FB18_I12" signal="PhaseB_High_6"/><fbinput id="FB18_I13" signal="PhaseB_High_7"/><fbinput id="FB18_I14" signal="PhaseB_Low_6"/><fbinput id="FB18_I15" signal="PhaseB_Low_7"/><PAL><pterm id="FB18_0"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_High_6"/></pterm><pterm id="FB18_1"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG" negated="ON"/><signal id="AD3PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_6" negated="ON"/><signal id="PhaseB_Low_6"/></pterm><pterm id="FB18_2"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG"/><signal id="AD3PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_High_6" negated="ON"/></pterm><pterm id="FB18_3"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_6"/></pterm><pterm id="FB18_4"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_High_7"/></pterm><pterm id="FB18_5"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_7" negated="ON"/><signal id="PhaseB_Low_7"/></pterm><pterm id="FB18_6"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_High_7" negated="ON"/></pterm><pterm id="FB18_7"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_7"/></pterm><pterm id="FB18_8"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_Low_6"/></pterm><pterm id="FB18_9"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG"/><signal id="AD3PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_6"/><signal id="PhaseB_Low_6" negated="ON"/></pterm><pterm id="FB18_10"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG" negated="ON"/><signal id="AD3PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_Low_6" negated="ON"/></pterm><pterm id="FB18_11"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_6"/></pterm><pterm id="FB18_12"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_Low_7"/></pterm><pterm id="FB18_13"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_7"/><signal id="PhaseB_Low_7" negated="ON"/></pterm><pterm id="FB18_14"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_Low_7" negated="ON"/></pterm><pterm id="FB18_15"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_7"/></pterm><pterm id="FB18_16"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_6"/></pterm><pterm id="FB18_17"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_Low_6"/></pterm></PAL><equation id="PhaseA_Low_7"><d2><eq_pterm ptindx="FB18_12"/><eq_pterm ptindx="FB18_15"/><eq_pterm ptindx="FB18_13"/><eq_pterm ptindx="FB18_14"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_7"><d2><eq_pterm ptindx="FB18_4"/><eq_pterm ptindx="FB18_7"/><eq_pterm ptindx="FB18_6"/><eq_pterm ptindx="FB18_5"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_Low_6"><d2><eq_pterm ptindx="FB18_17"/><eq_pterm ptindx="FB18_3"/><eq_pterm ptindx="FB18_2"/><eq_pterm ptindx="FB18_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_High_6"><d2><eq_pterm ptindx="FB18_16"/><eq_pterm ptindx="FB18_11"/><eq_pterm ptindx="FB18_9"/><eq_pterm ptindx="FB18_10"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_Low_6"><d2><eq_pterm ptindx="FB18_8"/><eq_pterm ptindx="FB18_11"/><eq_pterm ptindx="FB18_9"/><eq_pterm ptindx="FB18_10"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_6"><d2><eq_pterm ptindx="FB18_0"/><eq_pterm ptindx="FB18_3"/><eq_pterm ptindx="FB18_2"/><eq_pterm ptindx="FB18_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB19" pinUse="3"><macrocell id="FB19_MC1"/><macrocell id="FB19_MC2" pin="FB19_MC2_PIN143" sigUse="7" signal="PhaseB_Low_8"><eq_pterm ptindx="FB19_0"/><eq_pterm ptindx="FB19_3"/><eq_pterm ptindx="FB19_2"/><eq_pterm ptindx="FB19_1"/></macrocell><macrocell id="FB19_MC3"/><macrocell id="FB19_MC4" pin="FB19_MC4_PIN142" sigUse="1" signal="Heater_Control"><eq_pterm ptindx="FB19_14"/></macrocell><macrocell id="FB19_MC5"/><macrocell id="FB19_MC6"/><macrocell id="FB19_MC7"/><macrocell id="FB19_MC8"/><macrocell id="FB19_MC9"/><macrocell id="FB19_MC10"/><macrocell id="FB19_MC11"/><macrocell id="FB19_MC12"/><macrocell id="FB19_MC13"/><macrocell id="FB19_MC14"/><macrocell id="FB19_MC15" pin="FB19_MC15_PIN140" sigUse="3" signal="Motor1_Phase_A_HIN"><eq_pterm ptindx="FB19_36"/></macrocell><macrocell id="FB19_MC16"/><fbinput id="FB19_I1" fbk="PIN" signal="AD6PIN_SPECSIG"/><fbinput id="FB19_I2" fbk="PIN" signal="AD7PIN_SPECSIG"/><fbinput id="FB19_I3" signal="BUSReset"/><fbinput id="FB19_I4" signal="DRVVALV0w"/><fbinput id="FB19_I5" signal="DRVVALV1w"/><fbinput id="FB19_I6" signal="GPIO8"/><fbinput id="FB19_I7" signal="GPIO9"/><fbinput id="FB19_I8" signal="PhaseB_High_8"/><fbinput id="FB19_I9" signal="PhaseB_Low_8"/><fbinput id="FB19_I10" signal="U4M00_SPECSIG"/><fbinput id="FB19_I11" signal="U4M01_SPECSIG"/><PAL><pterm id="FB19_0"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_Low_8"/></pterm><pterm id="FB19_1"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG" negated="ON"/><signal id="AD7PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_8" negated="ON"/><signal id="PhaseB_Low_8"/></pterm><pterm id="FB19_2"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG"/><signal id="AD7PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_High_8" negated="ON"/></pterm><pterm id="FB19_3"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_8"/></pterm><pterm id="FB19_14"><signal id="GPIO9"/></pterm><pterm id="FB19_36"><signal id="GPIO8"/><signal id="U4M00_SPECSIG"/><signal id="U4M01_SPECSIG" negated="ON"/></pterm></PAL><equation id="PhaseB_Low_8"><d2><eq_pterm ptindx="FB19_0"/><eq_pterm ptindx="FB19_3"/><eq_pterm ptindx="FB19_2"/><eq_pterm ptindx="FB19_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="Heater_Control"><d1><eq_pterm ptindx="FB19_14"/></d1></equation><equation id="Motor1_Phase_A_HIN"><d1><eq_pterm ptindx="FB19_36"/></d1></equation></fblock><fblock id="FB20" pinUse="4"><macrocell id="FB20_MC1" pin="FB20_MC1_PIN14" sigUse="7" signal="PhaseB_Low_5"><eq_pterm ptindx="FB20_9"/><eq_pterm ptindx="FB20_3"/><eq_pterm ptindx="FB20_2"/><eq_pterm ptindx="FB20_1"/></macrocell><macrocell id="FB20_MC2"/><macrocell id="FB20_MC3"/><macrocell id="FB20_MC4" pin="FB20_MC4_PIN15" sigUse="7" signal="PhaseB_High_5"><eq_pterm ptindx="FB20_8"/><eq_pterm ptindx="FB20_7"/><eq_pterm ptindx="FB20_5"/><eq_pterm ptindx="FB20_6"/></macrocell><macrocell id="FB20_MC5"/><macrocell id="FB20_MC6"/><macrocell id="FB20_MC7"/><macrocell id="FB20_MC8"/><macrocell id="FB20_MC9"/><macrocell id="FB20_MC10"/><macrocell id="FB20_MC11"/><macrocell id="FB20_MC12"/><macrocell id="FB20_MC13"/><macrocell id="FB20_MC14" pin="FB20_MC14_PIN16" sigUse="8" signal="PhaseA_Low_5"><eq_pterm ptindx="FB20_4"/><eq_pterm ptindx="FB20_7"/><eq_pterm ptindx="FB20_5"/><eq_pterm ptindx="FB20_6"/></macrocell><macrocell id="FB20_MC15"/><macrocell id="FB20_MC16" pin="FB20_MC16_PIN18" sigUse="8" signal="PhaseA_High_5"><eq_pterm ptindx="FB20_0"/><eq_pterm ptindx="FB20_3"/><eq_pterm ptindx="FB20_2"/><eq_pterm ptindx="FB20_1"/></macrocell><fbinput id="FB20_I1" fbk="PIN" signal="AD0PIN_SPECSIG"/><fbinput id="FB20_I2" fbk="PIN" signal="AD1PIN_SPECSIG"/><fbinput id="FB20_I3" signal="BUSReset"/><fbinput id="FB20_I4" signal="DRVVALV0w"/><fbinput id="FB20_I5" signal="DRVVALV1w"/><fbinput id="FB20_I6" signal="PhaseA_High_5"/><fbinput id="FB20_I7" signal="PhaseA_Low_5"/><fbinput id="FB20_I8" signal="PhaseB_High_5"/><fbinput id="FB20_I9" signal="PhaseB_Low_5"/><PAL><pterm id="FB20_0"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_High_5"/></pterm><pterm id="FB20_1"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG" negated="ON"/><signal id="AD1PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_5" negated="ON"/><signal id="PhaseB_Low_5"/></pterm><pterm id="FB20_2"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="AD1PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_High_5" negated="ON"/></pterm><pterm id="FB20_3"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_5"/></pterm><pterm id="FB20_4"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseA_Low_5"/></pterm><pterm id="FB20_5"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="AD1PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_5"/><signal id="PhaseB_Low_5" negated="ON"/></pterm><pterm id="FB20_6"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG" negated="ON"/><signal id="AD1PIN_SPECSIG"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseB_Low_5" negated="ON"/></pterm><pterm id="FB20_7"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_5"/></pterm><pterm id="FB20_8"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_5"/></pterm><pterm id="FB20_9"><signal id="BUSReset"/><signal id="DRVVALV0w"/><signal id="PhaseB_Low_5"/></pterm></PAL><equation id="PhaseB_Low_5"><d2><eq_pterm ptindx="FB20_9"/><eq_pterm ptindx="FB20_3"/><eq_pterm ptindx="FB20_2"/><eq_pterm ptindx="FB20_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_High_5"><d2><eq_pterm ptindx="FB20_8"/><eq_pterm ptindx="FB20_7"/><eq_pterm ptindx="FB20_5"/><eq_pterm ptindx="FB20_6"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_Low_5"><d2><eq_pterm ptindx="FB20_4"/><eq_pterm ptindx="FB20_7"/><eq_pterm ptindx="FB20_5"/><eq_pterm ptindx="FB20_6"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_5"><d2><eq_pterm ptindx="FB20_0"/><eq_pterm ptindx="FB20_3"/><eq_pterm ptindx="FB20_2"/><eq_pterm ptindx="FB20_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB21" pinUse="2"><macrocell id="FB21_MC1"/><macrocell id="FB21_MC2"/><macrocell id="FB21_MC3"/><macrocell id="FB21_MC4"/><macrocell id="FB21_MC5"/><macrocell id="FB21_MC6"/><macrocell id="FB21_MC7"/><macrocell id="FB21_MC8"/><macrocell id="FB21_MC9"/><macrocell id="FB21_MC10"/><macrocell id="FB21_MC11"/><macrocell id="FB21_MC12"/><macrocell id="FB21_MC13" pin="FB21_MC13_PIN40" sigUse="4" signal="Motor_Power"><eq_pterm ptindx="FB21_4"/><eq_pterm ptindx="FB21_5"/></macrocell><macrocell id="FB21_MC14"/><macrocell id="FB21_MC15"/><macrocell id="FB21_MC16" pin="FB21_MC16_PIN37" sigUse="8" signal="PhaseA_High_1"><eq_pterm ptindx="FB21_3"/><eq_pterm ptindx="FB21_2"/><eq_pterm ptindx="FB21_0"/><eq_pterm ptindx="FB21_1"/></macrocell><fbinput id="FB21_I1" fbk="PIN" signal="AD0PIN_SPECSIG"/><fbinput id="FB21_I2" fbk="PIN" signal="AD1PIN_SPECSIG"/><fbinput id="FB21_I3" fbk="PIN" signal="AD2PIN_SPECSIG"/><fbinput id="FB21_I4" signal="BUSReset"/><fbinput id="FB21_I5" signal="DRVCTLw"/><fbinput id="FB21_I6" signal="DRVVALV0w"/><fbinput id="FB21_I7" signal="DRVVALV1w"/><fbinput id="FB21_I8" signal="Motor_Power"/><fbinput id="FB21_I9" signal="PhaseA_High_1"/><fbinput id="FB21_I10" signal="PhaseB_High_1"/><fbinput id="FB21_I11" signal="PhaseB_Low_1"/><PAL><pterm id="FB21_0"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="AD1PIN_SPECSIG" negated="ON"/><signal id="PhaseB_High_1" negated="ON"/><signal id="DRVVALV0w"/></pterm><pterm id="FB21_1"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG" negated="ON"/><signal id="AD1PIN_SPECSIG"/><signal id="PhaseB_High_1" negated="ON"/><signal id="PhaseB_Low_1"/><signal id="DRVVALV0w"/></pterm><pterm id="FB21_2"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseA_High_1"/><signal id="DRVVALV1w"/></pterm><pterm id="FB21_3"><signal id="BUSReset"/><signal id="PhaseB_Low_1"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/></pterm><pterm id="FB21_4"><signal id="BUSReset"/><signal id="DRVCTLw"/><signal id="AD2PIN_SPECSIG"/></pterm><pterm id="FB21_5"><signal id="BUSReset"/><signal id="DRVCTLw" negated="ON"/><signal id="Motor_Power"/></pterm></PAL><equation id="Motor_Power"><d2><eq_pterm ptindx="FB21_4"/><eq_pterm ptindx="FB21_5"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_1"><d2><eq_pterm ptindx="FB21_3"/><eq_pterm ptindx="FB21_2"/><eq_pterm ptindx="FB21_0"/><eq_pterm ptindx="FB21_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB22" pinUse="5"><macrocell id="FB22_MC1" pin="FB22_MC1_PIN19" sigUse="6" signal="PhaseB_Low_4"><eq_pterm ptindx="FB22_14"/><eq_pterm ptindx="FB22_0"/><eq_pterm ptindx="FB22_13"/></macrocell><macrocell id="FB22_MC2"/><macrocell id="FB22_MC3" pin="FB22_MC3_PIN20" sigUse="6" signal="PhaseB_High_4"><eq_pterm ptindx="FB22_9"/><eq_pterm ptindx="FB22_8"/><eq_pterm ptindx="FB22_5"/></macrocell><macrocell id="FB22_MC4" pin="FB22_MC4_PIN21" sigUse="8" signal="PhaseA_Low_4"><eq_pterm ptindx="FB22_6"/><eq_pterm ptindx="FB22_7"/><eq_pterm ptindx="FB22_5"/><eq_pterm ptindx="FB22_4"/></macrocell><macrocell id="FB22_MC5" pin="FB22_MC5_PIN22"/><macrocell id="FB22_MC6"/><macrocell id="FB22_MC7"/><macrocell id="FB22_MC8"/><macrocell id="FB22_MC9"/><macrocell id="FB22_MC10"/><macrocell id="FB22_MC11"/><macrocell id="FB22_MC12"/><macrocell id="FB22_MC13" pin="FB22_MC13_PIN23" sigUse="8" signal="PhaseA_High_4"><eq_pterm ptindx="FB22_2"/><eq_pterm ptindx="FB22_3"/><eq_pterm ptindx="FB22_0"/><eq_pterm ptindx="FB22_1"/></macrocell><macrocell id="FB22_MC14"/><macrocell id="FB22_MC15"/><macrocell id="FB22_MC16" pin="FB22_MC16_PIN25" sigUse="6" signal="PhaseB_Low_3"><eq_pterm ptindx="FB22_12"/><eq_pterm ptindx="FB22_11"/><eq_pterm ptindx="FB22_10"/></macrocell><fbinput id="FB22_I1" fbk="PIN" signal="AD4PIN_SPECSIG"/><fbinput id="FB22_I2" fbk="PIN" signal="AD5PIN_SPECSIG"/><fbinput id="FB22_I3" fbk="PIN" signal="AD6PIN_SPECSIG"/><fbinput id="FB22_I4" fbk="PIN" signal="AD7PIN_SPECSIG"/><fbinput id="FB22_I5" signal="BUSReset"/><fbinput id="FB22_I6" signal="DRVVALV0w"/><fbinput id="FB22_I7" signal="DRVVALV1w"/><fbinput id="FB22_I8" signal="PhaseA_High_4"/><fbinput id="FB22_I9" signal="PhaseA_Low_4"/><fbinput id="FB22_I10" signal="PhaseB_High_3"/><fbinput id="FB22_I11" signal="PhaseB_High_4"/><fbinput id="FB22_I12" signal="PhaseB_Low_3"/><fbinput id="FB22_I13" signal="PhaseB_Low_4"/><PAL><pterm id="FB22_0"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG"/><signal id="AD7PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_4" negated="ON"/></pterm><pterm id="FB22_1"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG" negated="ON"/><signal id="AD7PIN_SPECSIG"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_4" negated="ON"/><signal id="PhaseB_Low_4"/></pterm><pterm id="FB22_2"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseA_High_4"/></pterm><pterm id="FB22_3"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_4"/></pterm><pterm id="FB22_4"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG"/><signal id="AD7PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_4"/><signal id="PhaseB_Low_4" negated="ON"/></pterm><pterm id="FB22_5"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG" negated="ON"/><signal id="AD7PIN_SPECSIG"/><signal id="DRVVALV0w"/><signal id="PhaseB_Low_4" negated="ON"/></pterm><pterm id="FB22_6"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseA_Low_4"/></pterm><pterm id="FB22_7"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_4"/></pterm><pterm id="FB22_8"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG"/><signal id="AD7PIN_SPECSIG" negated="ON"/><signal id="PhaseB_High_4"/><signal id="PhaseB_Low_4" negated="ON"/></pterm><pterm id="FB22_9"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_4"/></pterm><pterm id="FB22_10"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/><signal id="PhaseB_High_3" negated="ON"/><signal id="PhaseB_Low_3"/></pterm><pterm id="FB22_11"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_3" negated="ON"/></pterm><pterm id="FB22_12"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_Low_3"/></pterm><pterm id="FB22_13"><signal id="BUSReset"/><signal id="AD6PIN_SPECSIG" negated="ON"/><signal id="AD7PIN_SPECSIG"/><signal id="PhaseB_High_4" negated="ON"/><signal id="PhaseB_Low_4"/></pterm><pterm id="FB22_14"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_Low_4"/></pterm></PAL><equation id="PhaseB_Low_4"><d2><eq_pterm ptindx="FB22_14"/><eq_pterm ptindx="FB22_0"/><eq_pterm ptindx="FB22_13"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_High_4"><d2><eq_pterm ptindx="FB22_9"/><eq_pterm ptindx="FB22_8"/><eq_pterm ptindx="FB22_5"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_Low_4"><d2><eq_pterm ptindx="FB22_6"/><eq_pterm ptindx="FB22_7"/><eq_pterm ptindx="FB22_5"/><eq_pterm ptindx="FB22_4"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_4"><d2><eq_pterm ptindx="FB22_2"/><eq_pterm ptindx="FB22_3"/><eq_pterm ptindx="FB22_0"/><eq_pterm ptindx="FB22_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_Low_3"><d2><eq_pterm ptindx="FB22_12"/><eq_pterm ptindx="FB22_11"/><eq_pterm ptindx="FB22_10"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB23" pinUse="2"><macrocell id="FB23_MC1" pin="FB23_MC1_PIN36" sigUse="8" signal="PhaseA_Low_1"><eq_pterm ptindx="FB23_3"/><eq_pterm ptindx="FB23_2"/><eq_pterm ptindx="FB23_1"/><eq_pterm ptindx="FB23_0"/></macrocell><macrocell id="FB23_MC2"/><macrocell id="FB23_MC3"/><macrocell id="FB23_MC4"/><macrocell id="FB23_MC5"/><macrocell id="FB23_MC6"/><macrocell id="FB23_MC7"/><macrocell id="FB23_MC8"/><macrocell id="FB23_MC9"/><macrocell id="FB23_MC10"/><macrocell id="FB23_MC11"/><macrocell id="FB23_MC12"/><macrocell id="FB23_MC13"/><macrocell id="FB23_MC14" pin="FB23_MC14_PIN35" sigUse="6" signal="PhaseB_High_1"><eq_pterm ptindx="FB23_5"/><eq_pterm ptindx="FB23_4"/><eq_pterm ptindx="FB23_1"/></macrocell><macrocell id="FB23_MC15"/><macrocell id="FB23_MC16"/><fbinput id="FB23_I1" fbk="PIN" signal="AD0PIN_SPECSIG"/><fbinput id="FB23_I2" fbk="PIN" signal="AD1PIN_SPECSIG"/><fbinput id="FB23_I3" signal="BUSReset"/><fbinput id="FB23_I4" signal="DRVVALV0w"/><fbinput id="FB23_I5" signal="DRVVALV1w"/><fbinput id="FB23_I6" signal="PhaseA_Low_1"/><fbinput id="FB23_I7" signal="PhaseB_High_1"/><fbinput id="FB23_I8" signal="PhaseB_Low_1"/><PAL><pterm id="FB23_0"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="AD1PIN_SPECSIG" negated="ON"/><signal id="PhaseB_High_1"/><signal id="PhaseB_Low_1" negated="ON"/><signal id="DRVVALV0w"/></pterm><pterm id="FB23_1"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG" negated="ON"/><signal id="AD1PIN_SPECSIG"/><signal id="PhaseB_Low_1" negated="ON"/><signal id="DRVVALV0w"/></pterm><pterm id="FB23_2"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseA_Low_1"/></pterm><pterm id="FB23_3"><signal id="BUSReset"/><signal id="PhaseB_High_1"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/></pterm><pterm id="FB23_4"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="AD1PIN_SPECSIG" negated="ON"/><signal id="PhaseB_High_1"/><signal id="PhaseB_Low_1" negated="ON"/></pterm><pterm id="FB23_5"><signal id="BUSReset"/><signal id="PhaseB_High_1"/><signal id="DRVVALV0w" negated="ON"/></pterm></PAL><equation id="PhaseA_Low_1"><d2><eq_pterm ptindx="FB23_3"/><eq_pterm ptindx="FB23_2"/><eq_pterm ptindx="FB23_1"/><eq_pterm ptindx="FB23_0"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_High_1"><d2><eq_pterm ptindx="FB23_5"/><eq_pterm ptindx="FB23_4"/><eq_pterm ptindx="FB23_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB24" pinUse="8"><macrocell id="FB24_MC1" pin="FB24_MC1_PIN26" sigUse="6" signal="PhaseB_High_3"><eq_pterm ptindx="FB24_19"/><eq_pterm ptindx="FB24_18"/><eq_pterm ptindx="FB24_13"/></macrocell><macrocell id="FB24_MC2" pin="FB24_MC2_PIN27" sigUse="8" signal="PhaseA_Low_3"><eq_pterm ptindx="FB24_14"/><eq_pterm ptindx="FB24_15"/><eq_pterm ptindx="FB24_13"/><eq_pterm ptindx="FB24_12"/></macrocell><macrocell id="FB24_MC3" pin="FB24_MC3_PIN28" sigUse="8" signal="PhaseA_High_3"><eq_pterm ptindx="FB24_6"/><eq_pterm ptindx="FB24_7"/><eq_pterm ptindx="FB24_4"/><eq_pterm ptindx="FB24_5"/></macrocell><macrocell id="FB24_MC4" pin="FB24_MC4_PIN29" sigUse="6" signal="PhaseB_Low_2"><eq_pterm ptindx="FB24_24"/><eq_pterm ptindx="FB24_0"/><eq_pterm ptindx="FB24_23"/></macrocell><macrocell id="FB24_MC5" pin="FB24_MC5_PIN30" sigUse="6" signal="PhaseB_High_2"><eq_pterm ptindx="FB24_17"/><eq_pterm ptindx="FB24_16"/><eq_pterm ptindx="FB24_8"/></macrocell><macrocell id="FB24_MC6"/><macrocell id="FB24_MC7"/><macrocell id="FB24_MC8"/><macrocell id="FB24_MC9"/><macrocell id="FB24_MC10"/><macrocell id="FB24_MC11"/><macrocell id="FB24_MC12"/><macrocell id="FB24_MC13" pin="FB24_MC13_PIN31" sigUse="8" signal="PhaseA_Low_2"><eq_pterm ptindx="FB24_10"/><eq_pterm ptindx="FB24_11"/><eq_pterm ptindx="FB24_8"/><eq_pterm ptindx="FB24_9"/></macrocell><macrocell id="FB24_MC14" pin="FB24_MC14_PIN32" sigUse="8" signal="PhaseA_High_2"><eq_pterm ptindx="FB24_2"/><eq_pterm ptindx="FB24_3"/><eq_pterm ptindx="FB24_0"/><eq_pterm ptindx="FB24_1"/></macrocell><macrocell id="FB24_MC15"/><macrocell id="FB24_MC16" pin="FB24_MC16_PIN34" sigUse="6" signal="PhaseB_Low_1"><eq_pterm ptindx="FB24_22"/><eq_pterm ptindx="FB24_21"/><eq_pterm ptindx="FB24_20"/></macrocell><fbinput id="FB24_I1" fbk="PIN" signal="AD0PIN_SPECSIG"/><fbinput id="FB24_I2" fbk="PIN" signal="AD1PIN_SPECSIG"/><fbinput id="FB24_I3" fbk="PIN" signal="AD2PIN_SPECSIG"/><fbinput id="FB24_I4" fbk="PIN" signal="AD3PIN_SPECSIG"/><fbinput id="FB24_I5" fbk="PIN" signal="AD4PIN_SPECSIG"/><fbinput id="FB24_I6" fbk="PIN" signal="AD5PIN_SPECSIG"/><fbinput id="FB24_I7" signal="BUSReset"/><fbinput id="FB24_I8" signal="DRVVALV0w"/><fbinput id="FB24_I9" signal="DRVVALV1w"/><fbinput id="FB24_I10" signal="PhaseA_High_2"/><fbinput id="FB24_I11" signal="PhaseA_High_3"/><fbinput id="FB24_I12" signal="PhaseA_Low_2"/><fbinput id="FB24_I13" signal="PhaseA_Low_3"/><fbinput id="FB24_I14" signal="PhaseB_High_1"/><fbinput id="FB24_I15" signal="PhaseB_High_2"/><fbinput id="FB24_I16" signal="PhaseB_High_3"/><fbinput id="FB24_I17" signal="PhaseB_Low_1"/><fbinput id="FB24_I18" signal="PhaseB_Low_2"/><fbinput id="FB24_I19" signal="PhaseB_Low_3"/><PAL><pterm id="FB24_0"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG"/><signal id="AD3PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_2" negated="ON"/></pterm><pterm id="FB24_1"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG" negated="ON"/><signal id="AD3PIN_SPECSIG"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_2" negated="ON"/><signal id="PhaseB_Low_2"/></pterm><pterm id="FB24_2"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseA_High_2"/></pterm><pterm id="FB24_3"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_2"/></pterm><pterm id="FB24_4"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_3" negated="ON"/></pterm><pterm id="FB24_5"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_3" negated="ON"/><signal id="PhaseB_Low_3"/></pterm><pterm id="FB24_6"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseA_High_3"/></pterm><pterm id="FB24_7"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_Low_3"/></pterm><pterm id="FB24_8"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG" negated="ON"/><signal id="AD3PIN_SPECSIG"/><signal id="DRVVALV0w"/><signal id="PhaseB_Low_2" negated="ON"/></pterm><pterm id="FB24_9"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG"/><signal id="AD3PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_2"/><signal id="PhaseB_Low_2" negated="ON"/></pterm><pterm id="FB24_10"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseA_Low_2"/></pterm><pterm id="FB24_11"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_2"/></pterm><pterm id="FB24_12"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="DRVVALV0w"/><signal id="PhaseB_High_3"/><signal id="PhaseB_Low_3" negated="ON"/></pterm><pterm id="FB24_13"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG" negated="ON"/><signal id="AD5PIN_SPECSIG"/><signal id="DRVVALV0w"/><signal id="PhaseB_Low_3" negated="ON"/></pterm><pterm id="FB24_14"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w"/><signal id="PhaseA_Low_3"/></pterm><pterm id="FB24_15"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="DRVVALV1w" negated="ON"/><signal id="PhaseB_High_3"/></pterm><pterm id="FB24_16"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG"/><signal id="AD3PIN_SPECSIG" negated="ON"/><signal id="PhaseB_High_2"/><signal id="PhaseB_Low_2" negated="ON"/></pterm><pterm id="FB24_17"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_2"/></pterm><pterm id="FB24_18"><signal id="BUSReset"/><signal id="AD4PIN_SPECSIG"/><signal id="AD5PIN_SPECSIG" negated="ON"/><signal id="PhaseB_High_3"/><signal id="PhaseB_Low_3" negated="ON"/></pterm><pterm id="FB24_19"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_High_3"/></pterm><pterm id="FB24_20"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG" negated="ON"/><signal id="AD1PIN_SPECSIG"/><signal id="PhaseB_High_1" negated="ON"/><signal id="PhaseB_Low_1"/></pterm><pterm id="FB24_21"><signal id="BUSReset"/><signal id="AD0PIN_SPECSIG"/><signal id="AD1PIN_SPECSIG" negated="ON"/><signal id="PhaseB_High_1" negated="ON"/><signal id="DRVVALV0w"/></pterm><pterm id="FB24_22"><signal id="BUSReset"/><signal id="PhaseB_Low_1"/><signal id="DRVVALV0w" negated="ON"/></pterm><pterm id="FB24_23"><signal id="BUSReset"/><signal id="AD2PIN_SPECSIG" negated="ON"/><signal id="AD3PIN_SPECSIG"/><signal id="PhaseB_High_2" negated="ON"/><signal id="PhaseB_Low_2"/></pterm><pterm id="FB24_24"><signal id="BUSReset"/><signal id="DRVVALV0w" negated="ON"/><signal id="PhaseB_Low_2"/></pterm></PAL><equation id="PhaseB_High_3"><d2><eq_pterm ptindx="FB24_19"/><eq_pterm ptindx="FB24_18"/><eq_pterm ptindx="FB24_13"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_Low_3"><d2><eq_pterm ptindx="FB24_14"/><eq_pterm ptindx="FB24_15"/><eq_pterm ptindx="FB24_13"/><eq_pterm ptindx="FB24_12"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_3"><d2><eq_pterm ptindx="FB24_6"/><eq_pterm ptindx="FB24_7"/><eq_pterm ptindx="FB24_4"/><eq_pterm ptindx="FB24_5"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_Low_2"><d2><eq_pterm ptindx="FB24_24"/><eq_pterm ptindx="FB24_0"/><eq_pterm ptindx="FB24_23"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_High_2"><d2><eq_pterm ptindx="FB24_17"/><eq_pterm ptindx="FB24_16"/><eq_pterm ptindx="FB24_8"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_Low_2"><d2><eq_pterm ptindx="FB24_10"/><eq_pterm ptindx="FB24_11"/><eq_pterm ptindx="FB24_8"/><eq_pterm ptindx="FB24_9"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseA_High_2"><d2><eq_pterm ptindx="FB24_2"/><eq_pterm ptindx="FB24_3"/><eq_pterm ptindx="FB24_0"/><eq_pterm ptindx="FB24_1"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation><equation id="PhaseB_Low_1"><d2><eq_pterm ptindx="FB24_22"/><eq_pterm ptindx="FB24_21"/><eq_pterm ptindx="FB24_20"/></d2><clk negated="ON"><fastsig signal="Mclk"/></clk><prld ptindx="GND"/></equation></fblock><vcc/><gnd/><messages><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;7&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;6&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;5&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;4&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;0&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;1&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;2&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;3&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;1&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;2&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;3&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;4&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;5&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;6&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;7&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;1&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;2&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;3&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;4&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;5&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;6&gt;\$WA1' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;7&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;1&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;2&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;3&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;4&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;5&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;6&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;7&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;1&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;2&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;3&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;4&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;5&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;6&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;7&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;0&gt;\$WA4' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;0&gt;\$WA0' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;0&gt;\$WA3' is detected.    The logic is being translated to a mux implementation.</warning><warning>Cpld:987 - An internal tristate buffer 'outDATA&lt;0&gt;\$WA2' is detected.    The logic is being translated to a mux implementation.</warning></messages><compOpts isp="ON" loc="ON" part="XCR3384XL-10-TQ144" prld="LOW" slew="SLOW" inreg="ON" mlopt="ON" nouct="OFF" fbnand="OFF" inputs="32" keepio="OFF" pterms="28" unused="PULLUP" exhaust="OFF" wysiwyg="OFF" blkfanin="38" ignorets="OFF" optimize="SPEED" terminate="FLOAT"/><specSig value="AD&lt;0&gt;.PIN" signal="AD0PIN_SPECSIG"/><specSig value="AD&lt;2&gt;.PIN" signal="AD2PIN_SPECSIG"/><specSig value="AD&lt;3&gt;.PIN" signal="AD3PIN_SPECSIG"/><specSig value="AD&lt;4&gt;.PIN" signal="AD4PIN_SPECSIG"/><specSig value="AD&lt;5&gt;.PIN" signal="AD5PIN_SPECSIG"/><specSig value="AD&lt;6&gt;.PIN" signal="AD6PIN_SPECSIG"/><specSig value="AD&lt;1&gt;.PIN" signal="AD1PIN_SPECSIG"/><specSig value="AD&lt;7&gt;.PIN" signal="AD7PIN_SPECSIG"/><specSig value="I/O" signal="IO_SPECSIG"/><specSig value="AD&lt;3&gt;" signal="AD3_SPECSIG"/><specSig value="AD&lt;2&gt;" signal="AD2_SPECSIG"/><specSig value="AD&lt;1&gt;" signal="AD1_SPECSIG"/><specSig value="AD&lt;0&gt;" signal="AD0_SPECSIG"/><specSig value="AD&lt;4&gt;" signal="AD4_SPECSIG"/><specSig value="AD&lt;5&gt;" signal="AD5_SPECSIG"/><specSig value="AD&lt;6&gt;" signal="AD6_SPECSIG"/><specSig value="AD&lt;7&gt;" signal="AD7_SPECSIG"/><specSig value="(b)" signal="b_SPECSIG"/><specSig value="U3_U2_EncReg&lt;5&gt;" signal="U3_U2_EncReg5_SPECSIG"/><specSig value="U3_U2_EncReg&lt;4&gt;" signal="U3_U2_EncReg4_SPECSIG"/><specSig value="U3_U2_EncReg&lt;0&gt;" signal="U3_U2_EncReg0_SPECSIG"/><specSig value="U3_U2_EncReg&lt;3&gt;" signal="U3_U2_EncReg3_SPECSIG"/><specSig value="U3_U2_EncReg&lt;2&gt;" signal="U3_U2_EncReg2_SPECSIG"/><specSig value="U3_U2_EncReg&lt;1&gt;" signal="U3_U2_EncReg1_SPECSIG"/><specSig value="U3_U1/DAVr" signal="U3_U1DAVr_SPECSIG"/><specSig value="U3_U2_EncReg&lt;8&gt;" signal="U3_U2_EncReg8_SPECSIG"/><specSig value="U3_U3_EncReg&lt;0&gt;" signal="U3_U3_EncReg0_SPECSIG"/><specSig value="U3_U3_EncReg&lt;1&gt;" signal="U3_U3_EncReg1_SPECSIG"/><specSig value="U3_U3_EncReg&lt;2&gt;" signal="U3_U3_EncReg2_SPECSIG"/><specSig value="U3_U3_EncReg&lt;3&gt;" signal="U3_U3_EncReg3_SPECSIG"/><specSig value="U3_U3_EncReg&lt;8&gt;" signal="U3_U3_EncReg8_SPECSIG"/><specSig value="U3_U4_EncReg&lt;0&gt;" signal="U3_U4_EncReg0_SPECSIG"/><specSig value="U3_U4_EncReg&lt;1&gt;" signal="U3_U4_EncReg1_SPECSIG"/><specSig value="U3_U4_EncReg&lt;2&gt;" signal="U3_U4_EncReg2_SPECSIG"/><specSig value="U3_U4_EncReg&lt;3&gt;" signal="U3_U4_EncReg3_SPECSIG"/><specSig value="U3_U4_EncReg&lt;8&gt;" signal="U3_U4_EncReg8_SPECSIG"/><specSig value="U3_U5_EncReg&lt;0&gt;" signal="U3_U5_EncReg0_SPECSIG"/><specSig value="U3_U5_EncReg&lt;1&gt;" signal="U3_U5_EncReg1_SPECSIG"/><specSig value="U3_U5_EncReg&lt;2&gt;" signal="U3_U5_EncReg2_SPECSIG"/><specSig value="U3_U5_EncReg&lt;3&gt;" signal="U3_U5_EncReg3_SPECSIG"/><specSig value="U3_U5_EncReg&lt;8&gt;" signal="U3_U5_EncReg8_SPECSIG"/><specSig value="U3_U4_EncReg&lt;4&gt;" signal="U3_U4_EncReg4_SPECSIG"/><specSig value="U3_U4_EncReg&lt;7&gt;" signal="U3_U4_EncReg7_SPECSIG"/><specSig value="U3_U4_EncReg&lt;6&gt;" signal="U3_U4_EncReg6_SPECSIG"/><specSig value="U3_U4_EncReg&lt;5&gt;" signal="U3_U4_EncReg5_SPECSIG"/><specSig value="U3_U1/CEr" signal="U3_U1CEr_SPECSIG"/><specSig value="U3_U1/SS" signal="U3_U1SS_SPECSIG"/><specSig value="U3_U2_EncReg&lt;6&gt;" signal="U3_U2_EncReg6_SPECSIG"/><specSig value="U3_U2_EncReg&lt;7&gt;" signal="U3_U2_EncReg7_SPECSIG"/><specSig value="U3_U3_EncReg&lt;4&gt;" signal="U3_U3_EncReg4_SPECSIG"/><specSig value="U3_U3_EncReg&lt;5&gt;" signal="U3_U3_EncReg5_SPECSIG"/><specSig value="U3_U3_EncReg&lt;6&gt;" signal="U3_U3_EncReg6_SPECSIG"/><specSig value="U3_U3_EncReg&lt;7&gt;" signal="U3_U3_EncReg7_SPECSIG"/><specSig value="U3_U5_EncReg&lt;4&gt;" signal="U3_U5_EncReg4_SPECSIG"/><specSig value="U3_U5_EncReg&lt;5&gt;" signal="U3_U5_EncReg5_SPECSIG"/><specSig value="U3_U5_EncReg&lt;6&gt;" signal="U3_U5_EncReg6_SPECSIG"/><specSig value="U3_U5_EncReg&lt;7&gt;" signal="U3_U5_EncReg7_SPECSIG"/><specSig value="U1_ADDR_reg&lt;4&gt;" signal="U1_ADDR_reg4_SPECSIG"/><specSig value="U1_ADDR_reg&lt;3&gt;" signal="U1_ADDR_reg3_SPECSIG"/><specSig value="U1_ADDR_reg&lt;1&gt;" signal="U1_ADDR_reg1_SPECSIG"/><specSig value="U1_ADDR_reg&lt;2&gt;" signal="U1_ADDR_reg2_SPECSIG"/><specSig value="U1_ADDR_reg&lt;0&gt;" signal="U1_ADDR_reg0_SPECSIG"/><specSig value="U1_ADDR_reg&lt;5&gt;" signal="U1_ADDR_reg5_SPECSIG"/><specSig value="U1_ADDR_reg&lt;6&gt;" signal="U1_ADDR_reg6_SPECSIG"/><specSig value="U1_ADDR_reg&lt;7&gt;" signal="U1_ADDR_reg7_SPECSIG"/><specSig value="U3_U1/BitCounter&lt;0&gt;" signal="U3_U1BitCounter0_SPECSIG"/><specSig value="U3_U1/BitCounter&lt;1&gt;" signal="U3_U1BitCounter1_SPECSIG"/><specSig value="U3_U1/BitCounter&lt;2&gt;" signal="U3_U1BitCounter2_SPECSIG"/><specSig value="U3_U1/BitCounter&lt;3&gt;" signal="U3_U1BitCounter3_SPECSIG"/><specSig value="U4/M30" signal="U4M30_SPECSIG"/><specSig value="U4/M31" signal="U4M31_SPECSIG"/><specSig value="U4/M21" signal="U4M21_SPECSIG"/><specSig value="U4/M20" signal="U4M20_SPECSIG"/><specSig value="U4/M11" signal="U4M11_SPECSIG"/><specSig value="U4/M10" signal="U4M10_SPECSIG"/><specSig value="U4/M00" signal="U4M00_SPECSIG"/><specSig value="U4/M01" signal="U4M01_SPECSIG"/><specSig value="U3_U1/divider&lt;3&gt;" signal="U3_U1divider3_SPECSIG"/><specSig value="U3_U1/divider&lt;1&gt;" signal="U3_U1divider1_SPECSIG"/><specSig value="U3_U1/divider&lt;0&gt;" signal="U3_U1divider0_SPECSIG"/><specSig value="U3_U1/divider&lt;2&gt;" signal="U3_U1divider2_SPECSIG"/></document>
