//--------------------------------------------------------------------------------------------------
//
// Title       : AnalogSel
// Design      : U4
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Rvavle\Rvalve\U4\src\AnalogSel.v
// Generated   : Tue May  4 11:15:49 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {AnalogSel}}
module AnalogSel ( ACE ,inDATA ,DRVCURSELw ,Reset ,AS0 ,AS1 ,AS2 ,Mclk );

input [7:0] inDATA ;
wire [7:0] inDATA ;
input DRVCURSELw ;
wire DRVCURSELw ;
input Reset ;
wire Reset ;
input Mclk ;
wire Mclk ;

output ACE ;
wire ACE ;
output AS0 ;
wire AS0 ;
output AS1 ;
wire AS1 ;
output AS2 ;
wire AS2 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [3:0] analogr;

always @ (negedge Mclk)
	begin
		if (Reset) analogr <= 4'b0;
		else if (DRVCURSELw) analogr <= inDATA[3:0];
		else analogr <= analogr;
	end
endmodule