111000000000 //AS RD WR BusDrive 8-Data 111000000000 //waiting for channel1 decoder to count a few 111000000000 //Reset through here 111000000000 111000000000 111000000000 011100010000 110111110001 //set up address to start read of encoders 111000000000 111000000000 111000000000 111000000000 111000000000 //power up and start conversion 111000000000 111000000000 111000000000 111000000000 011100011010 //write to valve bank 0 110101010101 111000000000 111000000000 111000000000 011100011001 //while that is running look at PWM translator 111000000000 110101010101 //set all pwm's to fwd 111000000000 111000000000 011100011011 //write to bank 1 110101010101 111000000000 111000000000 111000000000 111000000000 011100011010 //write bank 0 110110101010 011100011011 //write bank 1 110110101010 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 011100011001 111000000000 110110101010 111000000000 111000000000 111000000000 111111110001 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 011100011001 110111111111 111100010000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111100001111 111100001111 111100001111 111101010101 //now read the holding register, which should latch the entire 24 bits of 111101010101 //channel1 111101010101 111000000000 111000000000 //AS RD WR BusDrive 8-Data 111000000000 //waiting for channel1 decoder to count a few 111000000000 //Reset through here 111000000000 111000000000 111000000000 111100010000 111100010000 111100010000 111000010000 111000000000 111000000000 111100010000 111000000000 011100010001 //Read the encoders 001000000000 011000000000 001000000000 011000000000 001000000000 011000000000 001000000000 011000000000 001000000000 011000000000 001000000000 011000000000 001000000000 011000000000 001000000000 111000000000 111000000000 111000000000 111100001111 111100001111 111100001111 111101010101 //now read the holding register, which should latch the entire 24 bits of 111101010101 //channel1 111101010101 111000000000 111000000000 //AS RD WR BusDrive 8-Data 111000000000 //waiting for channel1 decoder to count a few 111000000000 //Reset through here 111000000000 111000000000 111000000000 111000010000 111000010000 111000010000 111000010000 111000000000 111000000000 111011110001 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111000000000 111100001111 111100001111 111100001111 111101010101 //now read the holding register, which should latch the entire 24 bits of 111101010101 //channel1 111101010101