// Xilinx Verilog produced by program ngc2hdl G.26
// Command: -ofmt verilog -intstyle silent -w U4.ngc U4.v 
// Input file: U4.ngc
// Output file: U4.v
// Design name: U4
// Xilinx: C:/Xilinx

// The output of ngc2hdl is a simulation model. This file cannot be synthesized,
// or used in any other manner other than simulation. This netlist uses simulation
// primitives which may not represent the true implementation of the device, however
// the netlist is functionally correct. Do not modify this file.

`timescale 1 ns/10 ps

module LPM_XOR2_1 (
  Data_0_, Data_1_, Result
);
  input Data_0_;
  input Data_1_;
  output Result;
  XOR2 Xo_0_1 (
    .I0(Data_0_),
    .I1(Data_1_),
    .O(Result)
  );
endmodule

module EncoderControl (
  DRVCTLw, Start, DRVSTATr, Reset, Mclk, Shift, Eclk, DAV
);
  input DRVCTLw;
  input Start;
  input DRVSTATr;
  input Reset;
  input Mclk;
  output Shift;
  output Eclk;
  output DAV;
  wire NlwRenamedSig_OI_Shift;
  wire NlwRenamedSig_OI_Eclk;
  wire BitCounter_0_;
  wire CEr;
  wire Madd__n0011__n0006_0_;
  wire DAVr;
  wire BitCounter_3_;
  wire BitCounter_Madd__n0000__n0004_0_;
  wire _n0000;
  wire _n0001;
  wire _n0002;
  wire BitCounter_2_;
  wire BitCounter_0_1__n0000;
  wire _n0005;
  wire BitCounter_1_;
  wire _n0012;
  wire BitCounter_0_2__n0000;
  wire BitCounter__n0000_1_;
  wire BitCounter_0__n0000;
  wire BitCounter__n0000_2_;
  wire _n0004_0_;
  wire _n0015;
  wire BitCounter_0_0__n0000;
  wire _n0004_3_;
  wire _n0004_2_;
  wire _n0004_1_;
  wire SS;
  wire divider_3_;
  wire divider_2_;
  wire divider_1_;
  wire divider_0_;
  wire _n0011_3_;
  wire _n0011_2_;
  wire _n0011_1_;
  wire BitCounter_Madd__n0000__n0006_0_;
  wire N6164;
  wire Eclkr__n0001;
  wire Eclkr__n0000;
  wire Shiftr__n0002;
  wire Shiftr__n0000;
  wire BitCounter_0_1__n0001;
  wire CEr__n0000;
  wire DAVr__n0000;
  wire BitCounter_0_3__n0000;
  wire DAVr__n0002;
  wire SS__n0000;
  wire BitCounter__n0000_3_;
  wire SS__n0002;
  wire Madd__n0011__n0004_0_;
  wire _n00121;
  wire _n00122;
  wire _n00123;
  wire _n00124;
  wire _n00125;
  wire _n00126;
  wire _n00011;
  wire _n00012;
  wire _n00013;
  wire _n00014;
  wire _n00015;
  wire _n00016;
  wire _n00151;
  wire _n00152;
  wire _n00153;
  wire DAVr__n00021;
  wire DAVr__n00022;
  wire DAVr__n00023;
  wire DAVr__n00024;
  wire DAVr__n00025;
  wire _n0004_0_1;
  wire _n0004_0_2;
  wire _n0004_0_3;
  wire _n00051;
  wire _n00021;
  wire _n00001;
  wire _n00002;
  wire _n00003;
  wire _n00004;
  wire _n00005;
  wire BitCounter_0_1__n00011;
  wire BitCounter_0_1__n00012;
  wire SS__n00021;
  wire Eclkr__n00011;
  wire Eclkr__n00012;
  wire Eclkr__n00001;
  wire Shiftr__n00001;
  assign
    Shift = NlwRenamedSig_OI_Shift,
    Eclk = NlwRenamedSig_OI_Eclk;
  AND2 _n00127 (
    .I0(_n00124),
    .I1(_n00126),
    .O(_n0012)
  );
  LPM_XOR2_1 Madd__n0011_Mxor_Result_1_ (
    .Data_0_(divider_0_),
    .Data_1_(divider_1_),
    .Result(_n0011_1_)
  );
  OR2 _n00017 (
    .I0(Reset),
    .I1(_n00016),
    .O(_n0001)
  );
  FDCE BitCounter_3 (
    .D(BitCounter_0_3__n0000),
    .CE(BitCounter_0_1__n0001),
    .CLR(N6164),
    .C(Mclk),
    .Q(BitCounter_3_)
  );
  INV BitCounter_0__n00001 (
    .I(BitCounter_0_),
    .O(BitCounter_0__n0000)
  );
  INV _n00154 (
    .I(_n00153),
    .O(_n0015)
  );
  LPM_XOR2_1 BitCounter_Madd__n0000_Mxor_Result_2_ (
    .Data_0_(BitCounter_Madd__n0000__n0004_0_),
    .Data_1_(BitCounter_2_),
    .Result(BitCounter__n0000_2_)
  );
  OR2 DAVr__n00026 (
    .I0(_n0002),
    .I1(DAVr__n00025),
    .O(DAVr__n0002)
  );
  AND4 _n0004_0_4 (
    .I0(SS),
    .I1(_n0004_0_1),
    .I2(_n0004_0_2),
    .I3(_n0004_0_3),
    .O(_n0004_0_)
  );
  AND2 _n0004_1_1 (
    .I0(_n0012),
    .I1(_n0011_1_),
    .O(_n0004_1_)
  );
  AND2 _n0004_2_1 (
    .I0(_n0012),
    .I1(_n0011_2_),
    .O(_n0004_2_)
  );
  AND2 _n0004_3_1 (
    .I0(_n0012),
    .I1(_n0011_3_),
    .O(_n0004_3_)
  );
  AND2 _n00052 (
    .I0(SS),
    .I1(_n00051),
    .O(_n0005)
  );
  OR2 _n00022 (
    .I0(Reset),
    .I1(_n00021),
    .O(_n0002)
  );
  AND2 BitCounter_Madd__n0000__n00001 (
    .I0(BitCounter_1_),
    .I1(BitCounter_0_),
    .O(BitCounter_Madd__n0000__n0004_0_)
  );
  OR2 _n00006 (
    .I0(Reset),
    .I1(_n00005),
    .O(_n0000)
  );
  FDCE SS_77 (
    .D(SS__n0000),
    .CE(SS__n0002),
    .CLR(N6164),
    .C(Shiftr__n0002),
    .Q(SS)
  );
  FD CEr_78 (
    .D(CEr__n0000),
    .C(Shiftr__n0002),
    .Q(CEr)
  );
  FD Shiftr (
    .D(Shiftr__n0000),
    .C(Shiftr__n0002),
    .Q(NlwRenamedSig_OI_Shift)
  );
  FDCE DAVr_79 (
    .D(DAVr__n0000),
    .CE(DAVr__n0002),
    .CLR(N6164),
    .C(Shiftr__n0002),
    .Q(DAVr)
  );
  FDCE divider_1 (
    .D(_n0004_1_),
    .CE(_n0015),
    .CLR(N6164),
    .C(Mclk),
    .Q(divider_1_)
  );
  FDCE Eclkr (
    .D(Eclkr__n0000),
    .CE(Eclkr__n0001),
    .CLR(N6164),
    .C(Mclk),
    .Q(NlwRenamedSig_OI_Eclk)
  );
  AND2 BitCounter_1__n00001 (
    .I0(_n0005),
    .I1(BitCounter__n0000_1_),
    .O(BitCounter_0_1__n0000)
  );
  BUFE I7_0 (
    .E(DRVSTATr),
    .I(DAVr),
    .O(DAV)
  );
  INV BitCounter_0_1__n00013 (
    .I(BitCounter_0_1__n00012),
    .O(BitCounter_0_1__n0001)
  );
  OR2 SS__n00022 (
    .I0(_n0000),
    .I1(SS__n00021),
    .O(SS__n0002)
  );
  AND2 BitCounter_Madd__n0000__n00011 (
    .I0(BitCounter_2_),
    .I1(BitCounter_Madd__n0000__n0004_0_),
    .O(BitCounter_Madd__n0000__n0006_0_)
  );
  INV Eclkr__n00013 (
    .I(Eclkr__n00012),
    .O(Eclkr__n0001)
  );
  INV Eclkr__n00002 (
    .I(Eclkr__n00001),
    .O(Eclkr__n0000)
  );
  GND XST_GND (
    .G(N6164)
  );
  INV Shiftr__n00021 (
    .I(Mclk),
    .O(Shiftr__n0002)
  );
  AND2 Shiftr__n00002 (
    .I0(NlwRenamedSig_OI_Eclk),
    .I1(Shiftr__n00001),
    .O(Shiftr__n0000)
  );
  FDCE BitCounter_0 (
    .D(BitCounter_0_0__n0000),
    .CE(BitCounter_0_1__n0001),
    .CLR(N6164),
    .C(Mclk),
    .Q(BitCounter_0_)
  );
  INV CEr__n00001 (
    .I(_n0001),
    .O(CEr__n0000)
  );
  FDCE BitCounter_1 (
    .D(BitCounter_0_1__n0000),
    .CE(BitCounter_0_1__n0001),
    .CLR(N6164),
    .C(Mclk),
    .Q(BitCounter_1_)
  );
  AND2 BitCounter_3__n00001 (
    .I0(_n0005),
    .I1(BitCounter__n0000_3_),
    .O(BitCounter_0_3__n0000)
  );
  INV DAVr__n00001 (
    .I(_n0002),
    .O(DAVr__n0000)
  );
  FDCE BitCounter_2 (
    .D(BitCounter_0_2__n0000),
    .CE(BitCounter_0_1__n0001),
    .CLR(N6164),
    .C(Mclk),
    .Q(BitCounter_2_)
  );
  LPM_XOR2_1 BitCounter_Madd__n0000_Mxor_Result_3_ (
    .Data_0_(BitCounter_Madd__n0000__n0006_0_),
    .Data_1_(BitCounter_3_),
    .Result(BitCounter__n0000_3_)
  );
  INV SS__n00001 (
    .I(_n0000),
    .O(SS__n0000)
  );
  AND2 BitCounter_2__n00001 (
    .I0(_n0005),
    .I1(BitCounter__n0000_2_),
    .O(BitCounter_0_2__n0000)
  );
  AND2 Madd__n0011__n00011 (
    .I0(divider_2_),
    .I1(Madd__n0011__n0004_0_),
    .O(Madd__n0011__n0006_0_)
  );
  AND2 Madd__n0011__n00001 (
    .I0(divider_1_),
    .I1(divider_0_),
    .O(Madd__n0011__n0004_0_)
  );
  LPM_XOR2_1 Madd__n0011_Mxor_Result_3_ (
    .Data_0_(Madd__n0011__n0006_0_),
    .Data_1_(divider_3_),
    .Result(_n0011_3_)
  );
  LPM_XOR2_1 Madd__n0011_Mxor_Result_2_ (
    .Data_0_(Madd__n0011__n0004_0_),
    .Data_1_(divider_2_),
    .Result(_n0011_2_)
  );
  FDCE divider_3 (
    .D(_n0004_3_),
    .CE(_n0015),
    .CLR(N6164),
    .C(Mclk),
    .Q(divider_3_)
  );
  FDCE divider_2 (
    .D(_n0004_2_),
    .CE(_n0015),
    .CLR(N6164),
    .C(Mclk),
    .Q(divider_2_)
  );
  FDCE divider_0 (
    .D(_n0004_0_),
    .CE(_n0015),
    .CLR(N6164),
    .C(Mclk),
    .Q(divider_0_)
  );
  AND2 BitCounter_0__n00002 (
    .I0(_n0005),
    .I1(BitCounter_0__n0000),
    .O(BitCounter_0_0__n0000)
  );
  LPM_XOR2_1 BitCounter_Madd__n0000_Mxor_Result_1_ (
    .Data_0_(BitCounter_0_),
    .Data_1_(BitCounter_1_),
    .Result(BitCounter__n0000_1_)
  );
  INV _n00121_80 (
    .I(divider_3_),
    .O(_n00121)
  );
  INV _n00122_81 (
    .I(divider_2_),
    .O(_n00122)
  );
  AND2 _n00123_82 (
    .I0(divider_1_),
    .I1(divider_0_),
    .O(_n00123)
  );
  AND2 _n00124_83 (
    .I0(SS),
    .I1(_n00121),
    .O(_n00124)
  );
  INV _n00125_84 (
    .I(_n00123),
    .O(_n00125)
  );
  AND2 _n00126_85 (
    .I0(_n00122),
    .I1(_n00125),
    .O(_n00126)
  );
  INV _n00011_86 (
    .I(divider_2_),
    .O(_n00011)
  );
  INV _n00012_87 (
    .I(divider_3_),
    .O(_n00012)
  );
  AND2 _n00013_88 (
    .I0(divider_1_),
    .I1(divider_0_),
    .O(_n00013)
  );
  AND2 _n00014_89 (
    .I0(_n00011),
    .I1(_n00012),
    .O(_n00014)
  );
  INV _n00015_90 (
    .I(_n00013),
    .O(_n00015)
  );
  AND2 _n00016_91 (
    .I0(_n00014),
    .I1(_n00015),
    .O(_n00016)
  );
  INV _n00151_92 (
    .I(SS),
    .O(_n00151)
  );
  INV _n00152_93 (
    .I(Reset),
    .O(_n00152)
  );
  AND2 _n00153_94 (
    .I0(_n00151),
    .I1(_n00152),
    .O(_n00153)
  );
  AND2 DAVr__n00021_95 (
    .I0(BitCounter_1_),
    .I1(NlwRenamedSig_OI_Eclk),
    .O(DAVr__n00021)
  );
  INV DAVr__n00022_96 (
    .I(BitCounter_0_),
    .O(DAVr__n00022)
  );
  INV DAVr__n00023_97 (
    .I(BitCounter_2_),
    .O(DAVr__n00023)
  );
  AND2 DAVr__n00024_98 (
    .I0(BitCounter_3_),
    .I1(DAVr__n00022),
    .O(DAVr__n00024)
  );
  AND3 DAVr__n00025_99 (
    .I0(DAVr__n00024),
    .I1(DAVr__n00021),
    .I2(DAVr__n00023),
    .O(DAVr__n00025)
  );
  INV _n0004_0_1_100 (
    .I(divider_3_),
    .O(_n0004_0_1)
  );
  INV _n0004_0_2_101 (
    .I(divider_2_),
    .O(_n0004_0_2)
  );
  INV _n0004_0_3_102 (
    .I(divider_0_),
    .O(_n0004_0_3)
  );
  INV _n00051_103 (
    .I(Reset),
    .O(_n00051)
  );
  AND2 _n00021_104 (
    .I0(Start),
    .I1(DRVCTLw),
    .O(_n00021)
  );
  AND2 _n00001_105 (
    .I0(BitCounter_1_),
    .I1(NlwRenamedSig_OI_Eclk),
    .O(_n00001)
  );
  INV _n00002_106 (
    .I(BitCounter_0_),
    .O(_n00002)
  );
  INV _n00003_107 (
    .I(BitCounter_2_),
    .O(_n00003)
  );
  AND2 _n00004_108 (
    .I0(BitCounter_3_),
    .I1(_n00002),
    .O(_n00004)
  );
  AND3 _n00005_109 (
    .I0(_n00004),
    .I1(_n00001),
    .I2(_n00003),
    .O(_n00005)
  );
  INV BitCounter_0_1__n00011_110 (
    .I(NlwRenamedSig_OI_Shift),
    .O(BitCounter_0_1__n00011)
  );
  AND2 BitCounter_0_1__n00012_111 (
    .I0(_n0005),
    .I1(BitCounter_0_1__n00011),
    .O(BitCounter_0_1__n00012)
  );
  AND2 SS__n00021_112 (
    .I0(Start),
    .I1(DRVCTLw),
    .O(SS__n00021)
  );
  INV Eclkr__n00011_113 (
    .I(CEr),
    .O(Eclkr__n00011)
  );
  AND2 Eclkr__n00012_114 (
    .I0(_n0005),
    .I1(Eclkr__n00011),
    .O(Eclkr__n00012)
  );
  AND2 Eclkr__n00001_115 (
    .I0(_n0005),
    .I1(NlwRenamedSig_OI_Eclk),
    .O(Eclkr__n00001)
  );
  INV Shiftr__n00001_116 (
    .I(_n0001),
    .O(Shiftr__n00001)
  );
endmodule

module PWMTranslator (
  DRVMTRCTLw, DRVCTLw, Reset, PWMsource, Mclk, Motor1_Phase_B_LIN, Motor2_Phase_A_LIN, MTRPWR_n, Motor3_Phase_B_HIN, Motor0_Phase_B_HIN, 
Motor1_Phase_A_HIN, Motor2_Phase_B_LIN, Motor3_Phase_A_LIN, Motor0_Phase_A_LIN, Motor1_Phase_B_HIN, Motor2_Phase_A_HIN, Motor3_Phase_B_LIN, 
Motor0_Phase_B_LIN, Motor1_Phase_A_LIN, Motor2_Phase_B_HIN, MTRPWR, Motor3_Phase_A_HIN, Motor0_Phase_A_HIN, inDATA
);
  input DRVMTRCTLw;
  input DRVCTLw;
  input Reset;
  input PWMsource;
  input Mclk;
  output Motor1_Phase_B_LIN;
  output Motor2_Phase_A_LIN;
  output MTRPWR_n;
  output Motor3_Phase_B_HIN;
  output Motor0_Phase_B_HIN;
  output Motor1_Phase_A_HIN;
  output Motor2_Phase_B_LIN;
  output Motor3_Phase_A_LIN;
  output Motor0_Phase_A_LIN;
  output Motor1_Phase_B_HIN;
  output Motor2_Phase_A_HIN;
  output Motor3_Phase_B_LIN;
  output Motor0_Phase_B_LIN;
  output Motor1_Phase_A_LIN;
  output Motor2_Phase_B_HIN;
  output MTRPWR;
  output Motor3_Phase_A_HIN;
  output Motor0_Phase_A_HIN;
  input [7 : 0] inDATA;
  wire M10;
  wire NlwRenamedSig_OI_MTRPWR;
  wire M20__n0000;
  wire M10__n0000;
  wire M30__n0000;
  wire N6524;
  wire M31__n0000;
  wire M30;
  wire MTRPWRr__n0002;
  wire MTRPWRr__n0000;
  wire M01__n0000;
  wire M31;
  wire M21__n0000;
  wire M11;
  wire M00__n0000;
  wire M11__n0000;
  wire M20;
  wire M31__n0002;
  wire M00;
  wire M01;
  wire M21;
  wire M10__n00001;
  wire M10__n00002;
  wire M10__n00003;
  wire M10__n00004;
  wire M10__n00005;
  wire M20__n00001;
  wire M20__n00002;
  wire M20__n00003;
  wire M20__n00004;
  wire M20__n00005;
  wire A_LIN_1_A_LIN;
  wire A_LIN_1_A_LIN1;
  wire A_LIN_1_A_LIN2;
  wire A_LIN_1_A_LIN3;
  wire A_LIN_1_A_LIN4;
  wire B_LIN_2_B_LIN;
  wire B_LIN_2_B_LIN1;
  wire B_LIN_2_B_LIN2;
  wire B_LIN_2_B_LIN3;
  wire B_LIN_2_B_LIN4;
  wire B_HIN_1_B_HIN;
  wire B_HIN_1_B_HIN1;
  wire A_LIN_3_A_LIN;
  wire A_LIN_3_A_LIN1;
  wire A_LIN_3_A_LIN2;
  wire A_LIN_3_A_LIN3;
  wire A_LIN_3_A_LIN4;
  wire B_LIN_3_B_LIN;
  wire B_LIN_3_B_LIN1;
  wire B_LIN_3_B_LIN2;
  wire B_LIN_3_B_LIN3;
  wire B_LIN_3_B_LIN4;
  wire B_HIN_3_B_HIN;
  wire B_HIN_3_B_HIN1;
  wire B_LIN_1_B_LIN;
  wire B_LIN_1_B_LIN1;
  wire B_LIN_1_B_LIN2;
  wire B_LIN_1_B_LIN3;
  wire B_LIN_1_B_LIN4;
  wire MTRPWRr__n00001;
  wire M11__n00001;
  wire M11__n00002;
  wire M11__n00003;
  wire M11__n00004;
  wire M11__n00005;
  wire M21__n00001;
  wire M21__n00002;
  wire M21__n00003;
  wire M21__n00004;
  wire M21__n00005;
  wire M00__n00001;
  wire M00__n00002;
  wire M00__n00003;
  wire M00__n00004;
  wire M00__n00005;
  wire M30__n00001;
  wire M30__n00002;
  wire M30__n00003;
  wire M30__n00004;
  wire M30__n00005;
  wire M01__n00001;
  wire M01__n00002;
  wire M01__n00003;
  wire M01__n00004;
  wire M01__n00005;
  wire M31__n00001;
  wire M31__n00002;
  wire M31__n00003;
  wire M31__n00004;
  wire M31__n00005;
  wire A_HIN_4_A_HIN;
  wire A_HIN_4_A_HIN1;
  wire A_LIN_2_A_LIN;
  wire A_LIN_2_A_LIN1;
  wire A_LIN_2_A_LIN2;
  wire A_LIN_2_A_LIN3;
  wire A_LIN_2_A_LIN4;
  wire A_HIN_2_A_HIN;
  wire A_HIN_2_A_HIN1;
  wire B_HIN_4_B_HIN;
  wire B_HIN_4_B_HIN1;
  wire A_LIN_4_A_LIN;
  wire A_LIN_4_A_LIN1;
  wire A_LIN_4_A_LIN2;
  wire A_LIN_4_A_LIN3;
  wire A_LIN_4_A_LIN4;
  wire B_HIN_2_B_HIN;
  wire B_HIN_2_B_HIN1;
  wire A_HIN_3_A_HIN;
  wire A_HIN_3_A_HIN1;
  wire B_LIN_4_B_LIN;
  wire B_LIN_4_B_LIN1;
  wire B_LIN_4_B_LIN2;
  wire B_LIN_4_B_LIN3;
  wire B_LIN_4_B_LIN4;
  wire A_HIN_1_A_HIN;
  wire A_HIN_1_A_HIN1;
  assign
    MTRPWR = NlwRenamedSig_OI_MTRPWR;
  AND2 M10__n00006 (
    .I0(M10__n00005),
    .I1(M10__n00003),
    .O(M10__n0000)
  );
  AND2 M20__n00006 (
    .I0(M20__n00005),
    .I1(M20__n00003),
    .O(M20__n0000)
  );
  OR2 A_LIN_1_A_LIN6 (
    .I0(A_LIN_1_A_LIN3),
    .I1(A_LIN_1_A_LIN4),
    .O(Motor3_Phase_A_LIN)
  );
  OR2 B_LIN_2_B_LIN6 (
    .I0(B_LIN_2_B_LIN3),
    .I1(B_LIN_2_B_LIN4),
    .O(Motor2_Phase_B_LIN)
  );
  AND2 B_HIN_1_B_HIN3 (
    .I0(B_HIN_1_B_HIN),
    .I1(B_HIN_1_B_HIN1),
    .O(Motor3_Phase_B_HIN)
  );
  INV MTRPWR_n1 (
    .I(NlwRenamedSig_OI_MTRPWR),
    .O(MTRPWR_n)
  );
  OR2 A_LIN_3_A_LIN6 (
    .I0(A_LIN_3_A_LIN3),
    .I1(A_LIN_3_A_LIN4),
    .O(Motor1_Phase_A_LIN)
  );
  OR2 B_LIN_3_B_LIN6 (
    .I0(B_LIN_3_B_LIN3),
    .I1(B_LIN_3_B_LIN4),
    .O(Motor1_Phase_B_LIN)
  );
  AND2 B_HIN_3_B_HIN3 (
    .I0(B_HIN_3_B_HIN),
    .I1(B_HIN_3_B_HIN1),
    .O(Motor1_Phase_B_HIN)
  );
  OR2 MTRPWRr__n00021 (
    .I0(Reset),
    .I1(DRVCTLw),
    .O(MTRPWRr__n0002)
  );
  OR2 B_LIN_1_B_LIN6 (
    .I0(B_LIN_1_B_LIN3),
    .I1(B_LIN_1_B_LIN4),
    .O(Motor3_Phase_B_LIN)
  );
  AND2 MTRPWRr__n00002 (
    .I0(inDATA[2]),
    .I1(MTRPWRr__n00001),
    .O(MTRPWRr__n0000)
  );
  AND2 M11__n00006 (
    .I0(M11__n00005),
    .I1(M11__n00003),
    .O(M11__n0000)
  );
  AND2 M21__n00006 (
    .I0(M21__n00005),
    .I1(M21__n00003),
    .O(M21__n0000)
  );
  GND XST_GND (
    .G(N6524)
  );
  AND2 M00__n00006 (
    .I0(M00__n00005),
    .I1(M00__n00003),
    .O(M00__n0000)
  );
  AND2 M30__n00006 (
    .I0(M30__n00005),
    .I1(M30__n00003),
    .O(M30__n0000)
  );
  AND2 M01__n00006 (
    .I0(M01__n00005),
    .I1(M01__n00003),
    .O(M01__n0000)
  );
  AND2 M31__n00006 (
    .I0(M31__n00005),
    .I1(M31__n00003),
    .O(M31__n0000)
  );
  FDCE MTRPWRr (
    .D(MTRPWRr__n0000),
    .CE(MTRPWRr__n0002),
    .CLR(N6524),
    .C(M31__n0002),
    .Q(NlwRenamedSig_OI_MTRPWR)
  );
  INV M31__n00021 (
    .I(Mclk),
    .O(M31__n0002)
  );
  FD M31_246 (
    .D(M31__n0000),
    .C(M31__n0002),
    .Q(M31)
  );
  AND2 A_HIN_4_A_HIN3 (
    .I0(A_HIN_4_A_HIN),
    .I1(A_HIN_4_A_HIN1),
    .O(Motor0_Phase_A_HIN)
  );
  FD M30_247 (
    .D(M30__n0000),
    .C(M31__n0002),
    .Q(M30)
  );
  OR2 A_LIN_2_A_LIN6 (
    .I0(A_LIN_2_A_LIN3),
    .I1(A_LIN_2_A_LIN4),
    .O(Motor2_Phase_A_LIN)
  );
  FD M21_248 (
    .D(M21__n0000),
    .C(M31__n0002),
    .Q(M21)
  );
  AND2 A_HIN_2_A_HIN3 (
    .I0(A_HIN_2_A_HIN),
    .I1(A_HIN_2_A_HIN1),
    .O(Motor2_Phase_A_HIN)
  );
  FD M20_249 (
    .D(M20__n0000),
    .C(M31__n0002),
    .Q(M20)
  );
  AND2 B_HIN_4_B_HIN3 (
    .I0(B_HIN_4_B_HIN),
    .I1(B_HIN_4_B_HIN1),
    .O(Motor0_Phase_B_HIN)
  );
  FD M11_250 (
    .D(M11__n0000),
    .C(M31__n0002),
    .Q(M11)
  );
  OR2 A_LIN_4_A_LIN6 (
    .I0(A_LIN_4_A_LIN3),
    .I1(A_LIN_4_A_LIN4),
    .O(Motor0_Phase_A_LIN)
  );
  FD M10_251 (
    .D(M10__n0000),
    .C(M31__n0002),
    .Q(M10)
  );
  AND2 B_HIN_2_B_HIN3 (
    .I0(B_HIN_2_B_HIN),
    .I1(B_HIN_2_B_HIN1),
    .O(Motor2_Phase_B_HIN)
  );
  FD M01_252 (
    .D(M01__n0000),
    .C(M31__n0002),
    .Q(M01)
  );
  AND2 A_HIN_3_A_HIN3 (
    .I0(A_HIN_3_A_HIN),
    .I1(A_HIN_3_A_HIN1),
    .O(Motor1_Phase_A_HIN)
  );
  FD M00_253 (
    .D(M00__n0000),
    .C(M31__n0002),
    .Q(M00)
  );
  OR2 B_LIN_4_B_LIN6 (
    .I0(B_LIN_4_B_LIN3),
    .I1(B_LIN_4_B_LIN4),
    .O(Motor0_Phase_B_LIN)
  );
  AND2 A_HIN_1_A_HIN3 (
    .I0(A_HIN_1_A_HIN),
    .I1(A_HIN_1_A_HIN1),
    .O(Motor3_Phase_A_HIN)
  );
  AND2 M10__n00001_254 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[2]),
    .O(M10__n00001)
  );
  INV M10__n00002_255 (
    .I(DRVMTRCTLw),
    .O(M10__n00002)
  );
  INV M10__n00003_256 (
    .I(Reset),
    .O(M10__n00003)
  );
  AND2 M10__n00004_257 (
    .I0(M10),
    .I1(M10__n00002),
    .O(M10__n00004)
  );
  OR2 M10__n00005_258 (
    .I0(M10__n00001),
    .I1(M10__n00004),
    .O(M10__n00005)
  );
  AND2 M20__n00001_259 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[4]),
    .O(M20__n00001)
  );
  INV M20__n00002_260 (
    .I(DRVMTRCTLw),
    .O(M20__n00002)
  );
  INV M20__n00003_261 (
    .I(Reset),
    .O(M20__n00003)
  );
  AND2 M20__n00004_262 (
    .I0(M20),
    .I1(M20__n00002),
    .O(M20__n00004)
  );
  OR2 M20__n00005_263 (
    .I0(M20__n00001),
    .I1(M20__n00004),
    .O(M20__n00005)
  );
  INV A_LIN_1_A_LIN1_264 (
    .I(M31),
    .O(A_LIN_1_A_LIN)
  );
  INV A_LIN_1_A_LIN2_265 (
    .I(PWMsource),
    .O(A_LIN_1_A_LIN1)
  );
  INV A_LIN_1_A_LIN3_266 (
    .I(M30),
    .O(A_LIN_1_A_LIN2)
  );
  AND2 A_LIN_1_A_LIN4_267 (
    .I0(PWMsource),
    .I1(A_LIN_1_A_LIN),
    .O(A_LIN_1_A_LIN3)
  );
  AND2 A_LIN_1_A_LIN5 (
    .I0(A_LIN_1_A_LIN1),
    .I1(A_LIN_1_A_LIN2),
    .O(A_LIN_1_A_LIN4)
  );
  INV B_LIN_2_B_LIN1_268 (
    .I(M20),
    .O(B_LIN_2_B_LIN)
  );
  INV B_LIN_2_B_LIN2_269 (
    .I(PWMsource),
    .O(B_LIN_2_B_LIN1)
  );
  INV B_LIN_2_B_LIN3_270 (
    .I(M21),
    .O(B_LIN_2_B_LIN2)
  );
  AND2 B_LIN_2_B_LIN4_271 (
    .I0(PWMsource),
    .I1(B_LIN_2_B_LIN),
    .O(B_LIN_2_B_LIN3)
  );
  AND2 B_LIN_2_B_LIN5 (
    .I0(B_LIN_2_B_LIN1),
    .I1(B_LIN_2_B_LIN2),
    .O(B_LIN_2_B_LIN4)
  );
  AND2 B_HIN_1_B_HIN1_272 (
    .I0(M31),
    .I1(PWMsource),
    .O(B_HIN_1_B_HIN)
  );
  INV B_HIN_1_B_HIN2 (
    .I(M30),
    .O(B_HIN_1_B_HIN1)
  );
  INV A_LIN_3_A_LIN1_273 (
    .I(M11),
    .O(A_LIN_3_A_LIN)
  );
  INV A_LIN_3_A_LIN2_274 (
    .I(PWMsource),
    .O(A_LIN_3_A_LIN1)
  );
  INV A_LIN_3_A_LIN3_275 (
    .I(M10),
    .O(A_LIN_3_A_LIN2)
  );
  AND2 A_LIN_3_A_LIN4_276 (
    .I0(PWMsource),
    .I1(A_LIN_3_A_LIN),
    .O(A_LIN_3_A_LIN3)
  );
  AND2 A_LIN_3_A_LIN5 (
    .I0(A_LIN_3_A_LIN1),
    .I1(A_LIN_3_A_LIN2),
    .O(A_LIN_3_A_LIN4)
  );
  INV B_LIN_3_B_LIN1_277 (
    .I(M10),
    .O(B_LIN_3_B_LIN)
  );
  INV B_LIN_3_B_LIN2_278 (
    .I(PWMsource),
    .O(B_LIN_3_B_LIN1)
  );
  INV B_LIN_3_B_LIN3_279 (
    .I(M11),
    .O(B_LIN_3_B_LIN2)
  );
  AND2 B_LIN_3_B_LIN4_280 (
    .I0(PWMsource),
    .I1(B_LIN_3_B_LIN),
    .O(B_LIN_3_B_LIN3)
  );
  AND2 B_LIN_3_B_LIN5 (
    .I0(B_LIN_3_B_LIN1),
    .I1(B_LIN_3_B_LIN2),
    .O(B_LIN_3_B_LIN4)
  );
  AND2 B_HIN_3_B_HIN1_281 (
    .I0(M11),
    .I1(PWMsource),
    .O(B_HIN_3_B_HIN)
  );
  INV B_HIN_3_B_HIN2 (
    .I(M10),
    .O(B_HIN_3_B_HIN1)
  );
  INV B_LIN_1_B_LIN1_282 (
    .I(M30),
    .O(B_LIN_1_B_LIN)
  );
  INV B_LIN_1_B_LIN2_283 (
    .I(PWMsource),
    .O(B_LIN_1_B_LIN1)
  );
  INV B_LIN_1_B_LIN3_284 (
    .I(M31),
    .O(B_LIN_1_B_LIN2)
  );
  AND2 B_LIN_1_B_LIN4_285 (
    .I0(PWMsource),
    .I1(B_LIN_1_B_LIN),
    .O(B_LIN_1_B_LIN3)
  );
  AND2 B_LIN_1_B_LIN5 (
    .I0(B_LIN_1_B_LIN1),
    .I1(B_LIN_1_B_LIN2),
    .O(B_LIN_1_B_LIN4)
  );
  INV MTRPWRr__n00001_286 (
    .I(Reset),
    .O(MTRPWRr__n00001)
  );
  AND2 M11__n00001_287 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[3]),
    .O(M11__n00001)
  );
  INV M11__n00002_288 (
    .I(DRVMTRCTLw),
    .O(M11__n00002)
  );
  INV M11__n00003_289 (
    .I(Reset),
    .O(M11__n00003)
  );
  AND2 M11__n00004_290 (
    .I0(M11),
    .I1(M11__n00002),
    .O(M11__n00004)
  );
  OR2 M11__n00005_291 (
    .I0(M11__n00001),
    .I1(M11__n00004),
    .O(M11__n00005)
  );
  AND2 M21__n00001_292 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[5]),
    .O(M21__n00001)
  );
  INV M21__n00002_293 (
    .I(DRVMTRCTLw),
    .O(M21__n00002)
  );
  INV M21__n00003_294 (
    .I(Reset),
    .O(M21__n00003)
  );
  AND2 M21__n00004_295 (
    .I0(M21),
    .I1(M21__n00002),
    .O(M21__n00004)
  );
  OR2 M21__n00005_296 (
    .I0(M21__n00001),
    .I1(M21__n00004),
    .O(M21__n00005)
  );
  AND2 M00__n00001_297 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[0]),
    .O(M00__n00001)
  );
  INV M00__n00002_298 (
    .I(DRVMTRCTLw),
    .O(M00__n00002)
  );
  INV M00__n00003_299 (
    .I(Reset),
    .O(M00__n00003)
  );
  AND2 M00__n00004_300 (
    .I0(M00),
    .I1(M00__n00002),
    .O(M00__n00004)
  );
  OR2 M00__n00005_301 (
    .I0(M00__n00001),
    .I1(M00__n00004),
    .O(M00__n00005)
  );
  AND2 M30__n00001_302 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[6]),
    .O(M30__n00001)
  );
  INV M30__n00002_303 (
    .I(DRVMTRCTLw),
    .O(M30__n00002)
  );
  INV M30__n00003_304 (
    .I(Reset),
    .O(M30__n00003)
  );
  AND2 M30__n00004_305 (
    .I0(M30),
    .I1(M30__n00002),
    .O(M30__n00004)
  );
  OR2 M30__n00005_306 (
    .I0(M30__n00001),
    .I1(M30__n00004),
    .O(M30__n00005)
  );
  AND2 M01__n00001_307 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[1]),
    .O(M01__n00001)
  );
  INV M01__n00002_308 (
    .I(DRVMTRCTLw),
    .O(M01__n00002)
  );
  INV M01__n00003_309 (
    .I(Reset),
    .O(M01__n00003)
  );
  AND2 M01__n00004_310 (
    .I0(M01),
    .I1(M01__n00002),
    .O(M01__n00004)
  );
  OR2 M01__n00005_311 (
    .I0(M01__n00001),
    .I1(M01__n00004),
    .O(M01__n00005)
  );
  AND2 M31__n00001_312 (
    .I0(DRVMTRCTLw),
    .I1(inDATA[7]),
    .O(M31__n00001)
  );
  INV M31__n00002_313 (
    .I(DRVMTRCTLw),
    .O(M31__n00002)
  );
  INV M31__n00003_314 (
    .I(Reset),
    .O(M31__n00003)
  );
  AND2 M31__n00004_315 (
    .I0(M31),
    .I1(M31__n00002),
    .O(M31__n00004)
  );
  OR2 M31__n00005_316 (
    .I0(M31__n00001),
    .I1(M31__n00004),
    .O(M31__n00005)
  );
  AND2 A_HIN_4_A_HIN1_317 (
    .I0(M00),
    .I1(PWMsource),
    .O(A_HIN_4_A_HIN)
  );
  INV A_HIN_4_A_HIN2 (
    .I(M01),
    .O(A_HIN_4_A_HIN1)
  );
  INV A_LIN_2_A_LIN1_318 (
    .I(M21),
    .O(A_LIN_2_A_LIN)
  );
  INV A_LIN_2_A_LIN2_319 (
    .I(PWMsource),
    .O(A_LIN_2_A_LIN1)
  );
  INV A_LIN_2_A_LIN3_320 (
    .I(M20),
    .O(A_LIN_2_A_LIN2)
  );
  AND2 A_LIN_2_A_LIN4_321 (
    .I0(PWMsource),
    .I1(A_LIN_2_A_LIN),
    .O(A_LIN_2_A_LIN3)
  );
  AND2 A_LIN_2_A_LIN5 (
    .I0(A_LIN_2_A_LIN1),
    .I1(A_LIN_2_A_LIN2),
    .O(A_LIN_2_A_LIN4)
  );
  AND2 A_HIN_2_A_HIN1_322 (
    .I0(M20),
    .I1(PWMsource),
    .O(A_HIN_2_A_HIN)
  );
  INV A_HIN_2_A_HIN2 (
    .I(M21),
    .O(A_HIN_2_A_HIN1)
  );
  AND2 B_HIN_4_B_HIN1_323 (
    .I0(M01),
    .I1(PWMsource),
    .O(B_HIN_4_B_HIN)
  );
  INV B_HIN_4_B_HIN2 (
    .I(M00),
    .O(B_HIN_4_B_HIN1)
  );
  INV A_LIN_4_A_LIN1_324 (
    .I(M01),
    .O(A_LIN_4_A_LIN)
  );
  INV A_LIN_4_A_LIN2_325 (
    .I(PWMsource),
    .O(A_LIN_4_A_LIN1)
  );
  INV A_LIN_4_A_LIN3_326 (
    .I(M00),
    .O(A_LIN_4_A_LIN2)
  );
  AND2 A_LIN_4_A_LIN4_327 (
    .I0(PWMsource),
    .I1(A_LIN_4_A_LIN),
    .O(A_LIN_4_A_LIN3)
  );
  AND2 A_LIN_4_A_LIN5 (
    .I0(A_LIN_4_A_LIN1),
    .I1(A_LIN_4_A_LIN2),
    .O(A_LIN_4_A_LIN4)
  );
  AND2 B_HIN_2_B_HIN1_328 (
    .I0(M21),
    .I1(PWMsource),
    .O(B_HIN_2_B_HIN)
  );
  INV B_HIN_2_B_HIN2 (
    .I(M20),
    .O(B_HIN_2_B_HIN1)
  );
  AND2 A_HIN_3_A_HIN1_329 (
    .I0(M10),
    .I1(PWMsource),
    .O(A_HIN_3_A_HIN)
  );
  INV A_HIN_3_A_HIN2 (
    .I(M11),
    .O(A_HIN_3_A_HIN1)
  );
  INV B_LIN_4_B_LIN1_330 (
    .I(M00),
    .O(B_LIN_4_B_LIN)
  );
  INV B_LIN_4_B_LIN2_331 (
    .I(PWMsource),
    .O(B_LIN_4_B_LIN1)
  );
  INV B_LIN_4_B_LIN3_332 (
    .I(M01),
    .O(B_LIN_4_B_LIN2)
  );
  AND2 B_LIN_4_B_LIN4_333 (
    .I0(PWMsource),
    .I1(B_LIN_4_B_LIN),
    .O(B_LIN_4_B_LIN3)
  );
  AND2 B_LIN_4_B_LIN5 (
    .I0(B_LIN_4_B_LIN1),
    .I1(B_LIN_4_B_LIN2),
    .O(B_LIN_4_B_LIN4)
  );
  AND2 A_HIN_1_A_HIN1_334 (
    .I0(M30),
    .I1(PWMsource),
    .O(A_HIN_1_A_HIN)
  );
  INV A_HIN_1_A_HIN2 (
    .I(M31),
    .O(A_HIN_1_A_HIN1)
  );
endmodule

module AddressDecode (
  RD, WR, DRVVALV0w, DRVMTRCTLw, DRVVALV1w, DRV2LOWr, DRVCURSELw, DRVCTLw, DRV0HIGHr, DRVSTATr, DRV3LOWr, DRV1HIGHr, DRV2HIGHr, DRV0LOWr, DRV3HIGHr, 
DRV1LOWr, ADDR
);
  input RD;
  input WR;
  output DRVVALV0w;
  output DRVMTRCTLw;
  output DRVVALV1w;
  output DRV2LOWr;
  output DRVCURSELw;
  output DRVCTLw;
  output DRV0HIGHr;
  output DRVSTATr;
  output DRV3LOWr;
  output DRV1HIGHr;
  output DRV2HIGHr;
  output DRV0LOWr;
  output DRV3HIGHr;
  output DRV1LOWr;
  input [7 : 0] ADDR;
  wire SF9621;
  wire SF9617;
  wire SF9596;
  wire SF9610;
  wire SF9593;
  wire SF9606;
  wire SF9591;
  wire SF9600;
  wire Select_9_Select;
  wire Select_9_Select1;
  wire Select_9_Select2;
  wire Select_12_Select;
  wire Select_12_Select1;
  wire Select_12_Select2;
  wire Select_12_Select3;
  wire Select_14_Select;
  wire Select_14_Select1;
  wire Select_14_Select2;
  wire Select_14_Select3;
  wire Select_4_Select;
  wire Select_4_Select1;
  wire Select_4_Select2;
  wire Select_7_Select;
  wire Select_7_Select1;
  wire Select_7_Select2;
  wire SF96171;
  wire SF96172;
  wire SF96173;
  wire SF96174;
  wire SF96175;
  wire Select_13_Select;
  wire Select_13_Select1;
  wire Select_13_Select2;
  wire Select_13_Select3;
  wire Select_8_Select;
  wire Select_8_Select1;
  wire Select_8_Select2;
  wire Select_8_Select3;
  wire SF96101;
  wire SF96102;
  wire SF96103;
  wire SF96104;
  wire SF96105;
  wire Select_5_Select;
  wire Select_5_Select1;
  wire Select_5_Select2;
  wire Select_1_Select;
  wire Select_1_Select1;
  wire Select_1_Select2;
  wire Select_1_Select3;
  wire Select_1_Select4;
  wire Select_6_Select;
  wire Select_6_Select1;
  wire Select_6_Select2;
  wire Select_6_Select3;
  wire SF95931;
  wire SF95932;
  wire SF95933;
  wire SF95934;
  wire Select_10_Select;
  wire Select_10_Select1;
  wire Select_10_Select2;
  wire Select_10_Select3;
  wire Select_2_Select;
  wire Select_2_Select1;
  wire Select_2_Select2;
  wire SF96061;
  wire SF96062;
  wire SF96063;
  wire SF96064;
  wire SF95911;
  wire SF95912;
  wire Select_11_Select;
  wire Select_11_Select1;
  wire Select_11_Select2;
  wire SF95961;
  wire SF95962;
  wire SF95963;
  wire SF96211;
  wire SF96212;
  wire SF96213;
  wire SF96214;
  wire Select_3_Select;
  wire Select_3_Select1;
  wire Select_3_Select2;
  wire Select_3_Select3;
  wire SF96001;
  wire SF96002;
  wire SF96003;
  wire SF96004;
  AND2 Select_9_Select4 (
    .I0(Select_9_Select),
    .I1(Select_9_Select2),
    .O(DRV1LOWr)
  );
  AND2 Select_12_Select5 (
    .I0(Select_12_Select),
    .I1(Select_12_Select3),
    .O(DRV0HIGHr)
  );
  AND2 Select_14_Select5 (
    .I0(Select_14_Select),
    .I1(Select_14_Select3),
    .O(DRVSTATr)
  );
  AND2 Select_4_Select4 (
    .I0(Select_4_Select),
    .I1(Select_4_Select2),
    .O(DRVMTRCTLw)
  );
  AND2 Select_7_Select4 (
    .I0(Select_7_Select),
    .I1(Select_7_Select2),
    .O(DRV2LOWr)
  );
  AND3 SF96176 (
    .I0(SF96175),
    .I1(SF96171),
    .I2(SF96174),
    .O(SF9617)
  );
  AND2 Select_13_Select5 (
    .I0(Select_13_Select),
    .I1(Select_13_Select3),
    .O(DRVCTLw)
  );
  AND2 Select_8_Select5 (
    .I0(Select_8_Select),
    .I1(Select_8_Select3),
    .O(DRV2HIGHr)
  );
  AND3 SF96106 (
    .I0(SF96105),
    .I1(SF96101),
    .I2(SF96104),
    .O(SF9610)
  );
  AND2 Select_5_Select4 (
    .I0(Select_5_Select),
    .I1(Select_5_Select2),
    .O(DRV3LOWr)
  );
  AND2 Select_1_Select6 (
    .I0(Select_1_Select),
    .I1(Select_1_Select4),
    .O(DRVCURSELw)
  );
  AND2 Select_6_Select5 (
    .I0(Select_6_Select),
    .I1(Select_6_Select3),
    .O(DRV3HIGHr)
  );
  AND3 SF95935 (
    .I0(SF95934),
    .I1(SF95931),
    .I2(SF95933),
    .O(SF9593)
  );
  AND2 Select_10_Select5 (
    .I0(Select_10_Select),
    .I1(Select_10_Select3),
    .O(DRV1HIGHr)
  );
  AND2 Select_2_Select4 (
    .I0(Select_2_Select),
    .I1(Select_2_Select2),
    .O(DRVVALV1w)
  );
  AND3 SF96065 (
    .I0(SF96064),
    .I1(SF96061),
    .I2(SF96063),
    .O(SF9606)
  );
  AND3 SF95913 (
    .I0(SF95911),
    .I1(ADDR[1]),
    .I2(SF95912),
    .O(SF9591)
  );
  AND2 Select_11_Select4 (
    .I0(Select_11_Select),
    .I1(Select_11_Select2),
    .O(DRV0LOWr)
  );
  AND3 SF95964 (
    .I0(SF95962),
    .I1(SF95961),
    .I2(SF95963),
    .O(SF9596)
  );
  AND3 SF96215 (
    .I0(SF96214),
    .I1(SF96211),
    .I2(SF96213),
    .O(SF9621)
  );
  AND2 Select_3_Select5 (
    .I0(Select_3_Select),
    .I1(Select_3_Select3),
    .O(DRVVALV0w)
  );
  AND3 SF96005 (
    .I0(SF96004),
    .I1(SF96001),
    .I2(SF96003),
    .O(SF9600)
  );
  AND2 Select_9_Select1_435 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_9_Select)
  );
  INV Select_9_Select2_436 (
    .I(RD),
    .O(Select_9_Select1)
  );
  AND2 Select_9_Select3 (
    .I0(SF9617),
    .I1(Select_9_Select1),
    .O(Select_9_Select2)
  );
  AND2 Select_12_Select1_437 (
    .I0(WR),
    .I1(SF9617),
    .O(Select_12_Select)
  );
  INV Select_12_Select2_438 (
    .I(RD),
    .O(Select_12_Select1)
  );
  INV Select_12_Select3_439 (
    .I(ADDR[0]),
    .O(Select_12_Select2)
  );
  AND2 Select_12_Select4 (
    .I0(Select_12_Select1),
    .I1(Select_12_Select2),
    .O(Select_12_Select3)
  );
  AND2 Select_14_Select1_440 (
    .I0(WR),
    .I1(SF9610),
    .O(Select_14_Select)
  );
  INV Select_14_Select2_441 (
    .I(RD),
    .O(Select_14_Select1)
  );
  INV Select_14_Select3_442 (
    .I(ADDR[0]),
    .O(Select_14_Select2)
  );
  AND2 Select_14_Select4 (
    .I0(Select_14_Select1),
    .I1(Select_14_Select2),
    .O(Select_14_Select3)
  );
  AND2 Select_4_Select1_443 (
    .I0(RD),
    .I1(ADDR[0]),
    .O(Select_4_Select)
  );
  INV Select_4_Select2_444 (
    .I(WR),
    .O(Select_4_Select1)
  );
  AND2 Select_4_Select3 (
    .I0(SF9600),
    .I1(Select_4_Select1),
    .O(Select_4_Select2)
  );
  AND2 Select_7_Select1_445 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_7_Select)
  );
  INV Select_7_Select2_446 (
    .I(RD),
    .O(Select_7_Select1)
  );
  AND2 Select_7_Select3 (
    .I0(SF9606),
    .I1(Select_7_Select1),
    .O(Select_7_Select2)
  );
  AND2 SF96171_447 (
    .I0(ADDR[4]),
    .I1(SF9591),
    .O(SF96171)
  );
  INV SF96172_448 (
    .I(ADDR[5]),
    .O(SF96172)
  );
  INV SF96173_449 (
    .I(ADDR[2]),
    .O(SF96173)
  );
  INV SF96174_450 (
    .I(ADDR[3]),
    .O(SF96174)
  );
  AND2 SF96175_451 (
    .I0(SF96172),
    .I1(SF96173),
    .O(SF96175)
  );
  AND2 Select_13_Select1_452 (
    .I0(RD),
    .I1(SF9610),
    .O(Select_13_Select)
  );
  INV Select_13_Select2_453 (
    .I(WR),
    .O(Select_13_Select1)
  );
  INV Select_13_Select3_454 (
    .I(ADDR[0]),
    .O(Select_13_Select2)
  );
  AND2 Select_13_Select4 (
    .I0(Select_13_Select1),
    .I1(Select_13_Select2),
    .O(Select_13_Select3)
  );
  AND2 Select_8_Select1_455 (
    .I0(WR),
    .I1(SF9621),
    .O(Select_8_Select)
  );
  INV Select_8_Select2_456 (
    .I(RD),
    .O(Select_8_Select1)
  );
  INV Select_8_Select3_457 (
    .I(ADDR[0]),
    .O(Select_8_Select2)
  );
  AND2 Select_8_Select4 (
    .I0(Select_8_Select1),
    .I1(Select_8_Select2),
    .O(Select_8_Select3)
  );
  AND2 SF96101_458 (
    .I0(ADDR[4]),
    .I1(SF9596),
    .O(SF96101)
  );
  INV SF96102_459 (
    .I(ADDR[5]),
    .O(SF96102)
  );
  INV SF96103_460 (
    .I(ADDR[2]),
    .O(SF96103)
  );
  INV SF96104_461 (
    .I(ADDR[3]),
    .O(SF96104)
  );
  AND2 SF96105_462 (
    .I0(SF96102),
    .I1(SF96103),
    .O(SF96105)
  );
  AND2 Select_5_Select1_463 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_5_Select)
  );
  INV Select_5_Select2_464 (
    .I(RD),
    .O(Select_5_Select1)
  );
  AND2 Select_5_Select3 (
    .I0(SF9621),
    .I1(Select_5_Select1),
    .O(Select_5_Select2)
  );
  AND4 Select_1_Select1_465 (
    .I0(RD),
    .I1(ADDR[4]),
    .I2(ADDR[2]),
    .I3(ADDR[3]),
    .O(Select_1_Select)
  );
  INV Select_1_Select2_466 (
    .I(WR),
    .O(Select_1_Select1)
  );
  INV Select_1_Select3_467 (
    .I(ADDR[0]),
    .O(Select_1_Select2)
  );
  INV Select_1_Select4_468 (
    .I(ADDR[5]),
    .O(Select_1_Select3)
  );
  AND4 Select_1_Select5 (
    .I0(SF9596),
    .I1(Select_1_Select1),
    .I2(Select_1_Select2),
    .I3(Select_1_Select3),
    .O(Select_1_Select4)
  );
  AND2 Select_6_Select1_469 (
    .I0(WR),
    .I1(SF9600),
    .O(Select_6_Select)
  );
  INV Select_6_Select2_470 (
    .I(RD),
    .O(Select_6_Select1)
  );
  INV Select_6_Select3_471 (
    .I(ADDR[0]),
    .O(Select_6_Select2)
  );
  AND2 Select_6_Select4 (
    .I0(Select_6_Select1),
    .I1(Select_6_Select2),
    .O(Select_6_Select3)
  );
  AND2 SF95931_472 (
    .I0(ADDR[4]),
    .I1(ADDR[3]),
    .O(SF95931)
  );
  INV SF95932_473 (
    .I(ADDR[5]),
    .O(SF95932)
  );
  INV SF95933_474 (
    .I(ADDR[2]),
    .O(SF95933)
  );
  AND2 SF95934_475 (
    .I0(SF9591),
    .I1(SF95932),
    .O(SF95934)
  );
  AND2 Select_10_Select1_476 (
    .I0(WR),
    .I1(SF9606),
    .O(Select_10_Select)
  );
  INV Select_10_Select2_477 (
    .I(RD),
    .O(Select_10_Select1)
  );
  INV Select_10_Select3_478 (
    .I(ADDR[0]),
    .O(Select_10_Select2)
  );
  AND2 Select_10_Select4 (
    .I0(Select_10_Select1),
    .I1(Select_10_Select2),
    .O(Select_10_Select3)
  );
  AND2 Select_2_Select1_479 (
    .I0(RD),
    .I1(ADDR[0]),
    .O(Select_2_Select)
  );
  INV Select_2_Select2_480 (
    .I(WR),
    .O(Select_2_Select1)
  );
  AND2 Select_2_Select3 (
    .I0(SF9593),
    .I1(Select_2_Select1),
    .O(Select_2_Select2)
  );
  AND2 SF96061_481 (
    .I0(ADDR[4]),
    .I1(ADDR[2]),
    .O(SF96061)
  );
  INV SF96062_482 (
    .I(ADDR[5]),
    .O(SF96062)
  );
  INV SF96063_483 (
    .I(ADDR[3]),
    .O(SF96063)
  );
  AND2 SF96064_484 (
    .I0(SF9596),
    .I1(SF96062),
    .O(SF96064)
  );
  INV SF95911_485 (
    .I(ADDR[7]),
    .O(SF95911)
  );
  INV SF95912_486 (
    .I(ADDR[6]),
    .O(SF95912)
  );
  AND2 Select_11_Select1_487 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_11_Select)
  );
  INV Select_11_Select2_488 (
    .I(RD),
    .O(Select_11_Select1)
  );
  AND2 Select_11_Select3 (
    .I0(SF9610),
    .I1(Select_11_Select1),
    .O(Select_11_Select2)
  );
  INV SF95961_489 (
    .I(ADDR[7]),
    .O(SF95961)
  );
  INV SF95962_490 (
    .I(ADDR[6]),
    .O(SF95962)
  );
  INV SF95963_491 (
    .I(ADDR[1]),
    .O(SF95963)
  );
  AND2 SF96211_492 (
    .I0(ADDR[4]),
    .I1(ADDR[2]),
    .O(SF96211)
  );
  INV SF96212_493 (
    .I(ADDR[5]),
    .O(SF96212)
  );
  INV SF96213_494 (
    .I(ADDR[3]),
    .O(SF96213)
  );
  AND2 SF96214_495 (
    .I0(SF9591),
    .I1(SF96212),
    .O(SF96214)
  );
  AND2 Select_3_Select1_496 (
    .I0(RD),
    .I1(SF9593),
    .O(Select_3_Select)
  );
  INV Select_3_Select2_497 (
    .I(WR),
    .O(Select_3_Select1)
  );
  INV Select_3_Select3_498 (
    .I(ADDR[0]),
    .O(Select_3_Select2)
  );
  AND2 Select_3_Select4 (
    .I0(Select_3_Select1),
    .I1(Select_3_Select2),
    .O(Select_3_Select3)
  );
  AND2 SF96001_499 (
    .I0(ADDR[4]),
    .I1(ADDR[3]),
    .O(SF96001)
  );
  INV SF96002_500 (
    .I(ADDR[5]),
    .O(SF96002)
  );
  INV SF96003_501 (
    .I(ADDR[2]),
    .O(SF96003)
  );
  AND2 SF96004_502 (
    .I0(SF9596),
    .I1(SF96002),
    .O(SF96004)
  );
endmodule

module ValveTranslator (
  DRVVALV0w, DRVVALV1w, Reset, Mclk, VAH0, VAH1, VAH2, VAH3, VAH4, VAH5, VAH6, VAH7, VAL0, VAL1, VAL2, VAL3, VAL4, VAL5, VBH0, VAL6, VBH1, VAL7, VBH2
, VBH3, VBH4, VBH5, VBH6, VBH7, VBL0, VBL1, VBL2, VBL3, VBL4, VBL5, VBL6, VBL7, inDATA
);
  input DRVVALV0w;
  input DRVVALV1w;
  input Reset;
  input Mclk;
  output VAH0;
  output VAH1;
  output VAH2;
  output VAH3;
  output VAH4;
  output VAH5;
  output VAH6;
  output VAH7;
  output VAL0;
  output VAL1;
  output VAL2;
  output VAL3;
  output VAL4;
  output VAL5;
  output VBH0;
  output VAL6;
  output VBH1;
  output VAL7;
  output VBH2;
  output VBH3;
  output VBH4;
  output VBH5;
  output VBH6;
  output VBH7;
  output VBL0;
  output VBL1;
  output VBL2;
  output VBL3;
  output VBL4;
  output VBL5;
  output VBL6;
  output VBL7;
  input [7 : 0] inDATA;
  wire NlwRenamedSig_OI_VBL0;
  wire NlwRenamedSig_OI_VBL1;
  wire NlwRenamedSig_OI_VBL2;
  wire NlwRenamedSig_OI_VBL3;
  wire NlwRenamedSig_OI_VBL4;
  wire NlwRenamedSig_OI_VBL5;
  wire NlwRenamedSig_OI_VBL6;
  wire NlwRenamedSig_OI_VBL7;
  wire V3_1__n0000;
  wire V4_0__n0000;
  wire V3_0__n0000;
  wire V7_1__n0000;
  wire V6_1__n0000;
  wire V0_1__n0000;
  wire NlwRenamedSig_OI_VBH0;
  wire V2_1__n0000;
  wire NlwRenamedSig_OI_VBH1;
  wire V0_0__n0000;
  wire NlwRenamedSig_OI_VBH2;
  wire NlwRenamedSig_OI_VBH3;
  wire NlwRenamedSig_OI_VBH4;
  wire NlwRenamedSig_OI_VBH5;
  wire NlwRenamedSig_OI_VBH6;
  wire NlwRenamedSig_OI_VBH7;
  wire V1_0__n0000;
  wire V4_1__n0000;
  wire V7_0__n0003;
  wire V7_0__n0002;
  wire V5_0__n0000;
  wire V1_1__n0000;
  wire V5_1__n0000;
  wire V7_0__n0000;
  wire N6076;
  wire V2_0__n0000;
  wire V6_0__n0000;
  wire V3_0__n0002;
  wire V3_0__n00021;
  wire V3_0__n00022;
  wire V3_0__n00023;
  wire V7_1__n00001;
  wire V7_1__n00002;
  wire V7_1__n00003;
  wire V7_1__n00004;
  wire V7_1__n00005;
  wire V7_1__n00006;
  wire V7_1__n00007;
  wire V7_1__n00008;
  wire V7_1__n00009;
  wire V7_1__n000010;
  wire V7_1__n000011;
  wire V7_1__n000012;
  wire V7_1__n000013;
  wire V7_0__n00001;
  wire V7_0__n00002;
  wire V7_0__n00003;
  wire V7_0__n00004;
  wire V7_0__n00005;
  wire V7_0__n00006;
  wire V7_0__n00007;
  wire V7_0__n00008;
  wire V7_0__n00009;
  wire V7_0__n000010;
  wire V7_0__n000011;
  wire V7_0__n000012;
  wire V7_0__n000013;
  wire V6_1__n00001;
  wire V6_1__n00002;
  wire V6_1__n00003;
  wire V6_1__n00004;
  wire V6_1__n00005;
  wire V6_1__n00006;
  wire V6_1__n00007;
  wire V6_1__n00008;
  wire V6_1__n00009;
  wire V6_1__n000010;
  wire V6_1__n000011;
  wire V6_1__n000012;
  wire V6_1__n000013;
  wire V6_0__n00001;
  wire V6_0__n00002;
  wire V6_0__n00003;
  wire V6_0__n00004;
  wire V6_0__n00005;
  wire V6_0__n00006;
  wire V6_0__n00007;
  wire V6_0__n00008;
  wire V6_0__n00009;
  wire V6_0__n000010;
  wire V6_0__n000011;
  wire V6_0__n000012;
  wire V6_0__n000013;
  wire V5_1__n00001;
  wire V5_1__n00002;
  wire V5_1__n00003;
  wire V5_1__n00004;
  wire V5_1__n00005;
  wire V5_1__n00006;
  wire V5_1__n00007;
  wire V5_1__n00008;
  wire V5_1__n00009;
  wire V5_1__n000010;
  wire V5_1__n000011;
  wire V5_1__n000012;
  wire V5_1__n000013;
  wire V5_0__n00001;
  wire V5_0__n00002;
  wire V5_0__n00003;
  wire V5_0__n00004;
  wire V5_0__n00005;
  wire V5_0__n00006;
  wire V5_0__n00007;
  wire V5_0__n00008;
  wire V5_0__n00009;
  wire V5_0__n000010;
  wire V5_0__n000011;
  wire V5_0__n000012;
  wire V5_0__n000013;
  wire V4_1__n00001;
  wire V4_1__n00002;
  wire V4_1__n00003;
  wire V4_1__n00004;
  wire V4_1__n00005;
  wire V4_1__n00006;
  wire V4_1__n00007;
  wire V4_1__n00008;
  wire V4_1__n00009;
  wire V4_1__n000010;
  wire V4_1__n000011;
  wire V4_1__n000012;
  wire V4_1__n000013;
  wire V7_0__n00021;
  wire V7_0__n00022;
  wire V4_0__n00001;
  wire V4_0__n00002;
  wire V4_0__n00003;
  wire V4_0__n00004;
  wire V4_0__n00005;
  wire V4_0__n00006;
  wire V4_0__n00007;
  wire V4_0__n00008;
  wire V4_0__n00009;
  wire V4_0__n000010;
  wire V4_0__n000011;
  wire V4_0__n000012;
  wire V4_0__n000013;
  wire V3_1__n00001;
  wire V3_1__n00002;
  wire V3_1__n00003;
  wire V3_1__n00004;
  wire V3_1__n00005;
  wire V3_1__n00006;
  wire V3_1__n00007;
  wire V3_1__n00008;
  wire V3_1__n00009;
  wire V3_1__n000010;
  wire V3_1__n000011;
  wire V3_1__n000012;
  wire V3_1__n000013;
  wire V3_0__n00001;
  wire V3_0__n00002;
  wire V3_0__n00003;
  wire V3_0__n00004;
  wire V3_0__n00005;
  wire V3_0__n00006;
  wire V3_0__n00007;
  wire V3_0__n00008;
  wire V3_0__n00009;
  wire V3_0__n000010;
  wire V3_0__n000011;
  wire V3_0__n000012;
  wire V3_0__n000013;
  wire V2_1__n00001;
  wire V2_1__n00002;
  wire V2_1__n00003;
  wire V2_1__n00004;
  wire V2_1__n00005;
  wire V2_1__n00006;
  wire V2_1__n00007;
  wire V2_1__n00008;
  wire V2_1__n00009;
  wire V2_1__n000010;
  wire V2_1__n000011;
  wire V2_1__n000012;
  wire V2_1__n000013;
  wire V2_0__n00001;
  wire V2_0__n00002;
  wire V2_0__n00003;
  wire V2_0__n00004;
  wire V2_0__n00005;
  wire V2_0__n00006;
  wire V2_0__n00007;
  wire V2_0__n00008;
  wire V2_0__n00009;
  wire V2_0__n000010;
  wire V2_0__n000011;
  wire V2_0__n000012;
  wire V2_0__n000013;
  wire V1_1__n00001;
  wire V1_1__n00002;
  wire V1_1__n00003;
  wire V1_1__n00004;
  wire V1_1__n00005;
  wire V1_1__n00006;
  wire V1_1__n00007;
  wire V1_1__n00008;
  wire V1_1__n00009;
  wire V1_1__n000010;
  wire V1_1__n000011;
  wire V1_1__n000012;
  wire V1_1__n000013;
  wire V1_0__n00001;
  wire V1_0__n00002;
  wire V1_0__n00003;
  wire V1_0__n00004;
  wire V1_0__n00005;
  wire V1_0__n00006;
  wire V1_0__n00007;
  wire V1_0__n00008;
  wire V1_0__n00009;
  wire V1_0__n000010;
  wire V1_0__n000011;
  wire V1_0__n000012;
  wire V1_0__n000013;
  wire V0_1__n00001;
  wire V0_1__n00002;
  wire V0_1__n00003;
  wire V0_1__n00004;
  wire V0_1__n00005;
  wire V0_1__n00006;
  wire V0_1__n00007;
  wire V0_1__n00008;
  wire V0_1__n00009;
  wire V0_1__n000010;
  wire V0_1__n000011;
  wire V0_1__n000012;
  wire V0_1__n000013;
  wire V0_0__n00001;
  wire V0_0__n00002;
  wire V0_0__n00003;
  wire V0_0__n00004;
  wire V0_0__n00005;
  wire V0_0__n00006;
  wire V0_0__n00007;
  wire V0_0__n00008;
  wire V0_0__n00009;
  wire V0_0__n000010;
  wire V0_0__n000011;
  wire V0_0__n000012;
  wire V0_0__n000013;
  assign
    VAH0 = NlwRenamedSig_OI_VBL0,
    VAH1 = NlwRenamedSig_OI_VBL1,
    VAH2 = NlwRenamedSig_OI_VBL2,
    VAH3 = NlwRenamedSig_OI_VBL3,
    VAH4 = NlwRenamedSig_OI_VBL4,
    VAH5 = NlwRenamedSig_OI_VBL5,
    VAH6 = NlwRenamedSig_OI_VBL6,
    VAH7 = NlwRenamedSig_OI_VBL7,
    VAL0 = NlwRenamedSig_OI_VBH0,
    VAL1 = NlwRenamedSig_OI_VBH1,
    VAL2 = NlwRenamedSig_OI_VBH2,
    VAL3 = NlwRenamedSig_OI_VBH3,
    VAL4 = NlwRenamedSig_OI_VBH4,
    VAL5 = NlwRenamedSig_OI_VBH5,
    VBH0 = NlwRenamedSig_OI_VBH0,
    VAL6 = NlwRenamedSig_OI_VBH6,
    VBH1 = NlwRenamedSig_OI_VBH1,
    VAL7 = NlwRenamedSig_OI_VBH7,
    VBH2 = NlwRenamedSig_OI_VBH2,
    VBH3 = NlwRenamedSig_OI_VBH3,
    VBH4 = NlwRenamedSig_OI_VBH4,
    VBH5 = NlwRenamedSig_OI_VBH5,
    VBH6 = NlwRenamedSig_OI_VBH6,
    VBH7 = NlwRenamedSig_OI_VBH7,
    VBL0 = NlwRenamedSig_OI_VBL0,
    VBL1 = NlwRenamedSig_OI_VBL1,
    VBL2 = NlwRenamedSig_OI_VBL2,
    VBL3 = NlwRenamedSig_OI_VBL3,
    VBL4 = NlwRenamedSig_OI_VBL4,
    VBL5 = NlwRenamedSig_OI_VBL5,
    VBL6 = NlwRenamedSig_OI_VBL6,
    VBL7 = NlwRenamedSig_OI_VBL7;
  FDCE V7_0 (
    .D(V7_0__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL7)
  );
  INV V3_0__n00024 (
    .I(V3_0__n00023),
    .O(V3_0__n0002)
  );
  AND2 V7_1__n000014 (
    .I0(V7_1__n000013),
    .I1(V7_1__n00007),
    .O(V7_1__n0000)
  );
  FDCE V7_1 (
    .D(V7_1__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH7)
  );
  AND2 V7_0__n000014 (
    .I0(V7_0__n000013),
    .I1(V7_0__n00007),
    .O(V7_0__n0000)
  );
  FDCE V6_1 (
    .D(V6_1__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH6)
  );
  AND2 V6_1__n000014 (
    .I0(V6_1__n000013),
    .I1(V6_1__n00007),
    .O(V6_1__n0000)
  );
  FDCE V5_1 (
    .D(V5_1__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH5)
  );
  AND2 V6_0__n000014 (
    .I0(V6_0__n000013),
    .I1(V6_0__n00007),
    .O(V6_0__n0000)
  );
  FDCE V4_1 (
    .D(V4_1__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH4)
  );
  AND2 V5_1__n000014 (
    .I0(V5_1__n000013),
    .I1(V5_1__n00007),
    .O(V5_1__n0000)
  );
  FDCE V2_1 (
    .D(V2_1__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH2)
  );
  AND2 V5_0__n000014 (
    .I0(V5_0__n000013),
    .I1(V5_0__n00007),
    .O(V5_0__n0000)
  );
  FDCE V3_1 (
    .D(V3_1__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH3)
  );
  AND2 V4_1__n000014 (
    .I0(V4_1__n000013),
    .I1(V4_1__n00007),
    .O(V4_1__n0000)
  );
  INV V7_0__n00023 (
    .I(V7_0__n00022),
    .O(V7_0__n0002)
  );
  AND2 V4_0__n000014 (
    .I0(V4_0__n000013),
    .I1(V4_0__n00007),
    .O(V4_0__n0000)
  );
  FDCE V1_1 (
    .D(V1_1__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH1)
  );
  AND2 V3_1__n000014 (
    .I0(V3_1__n000013),
    .I1(V3_1__n00007),
    .O(V3_1__n0000)
  );
  INV V7_0__n00031 (
    .I(Mclk),
    .O(V7_0__n0003)
  );
  AND2 V3_0__n000014 (
    .I0(V3_0__n000013),
    .I1(V3_0__n00007),
    .O(V3_0__n0000)
  );
  FDCE V0_0 (
    .D(V0_0__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL0)
  );
  AND2 V2_1__n000014 (
    .I0(V2_1__n000013),
    .I1(V2_1__n00007),
    .O(V2_1__n0000)
  );
  FDCE V0_1 (
    .D(V0_1__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBH0)
  );
  AND2 V2_0__n000014 (
    .I0(V2_0__n000013),
    .I1(V2_0__n00007),
    .O(V2_0__n0000)
  );
  FDCE V2_0 (
    .D(V2_0__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL2)
  );
  AND2 V1_1__n000014 (
    .I0(V1_1__n000013),
    .I1(V1_1__n00007),
    .O(V1_1__n0000)
  );
  FDCE V3_0 (
    .D(V3_0__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL3)
  );
  AND2 V1_0__n000014 (
    .I0(V1_0__n000013),
    .I1(V1_0__n00007),
    .O(V1_0__n0000)
  );
  FDCE V1_0 (
    .D(V1_0__n0000),
    .CE(V3_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL1)
  );
  AND2 V0_1__n000014 (
    .I0(V0_1__n000013),
    .I1(V0_1__n00007),
    .O(V0_1__n0000)
  );
  FDCE V4_0 (
    .D(V4_0__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL4)
  );
  AND2 V0_0__n000014 (
    .I0(V0_0__n000013),
    .I1(V0_0__n00007),
    .O(V0_0__n0000)
  );
  FDCE V5_0 (
    .D(V5_0__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL5)
  );
  GND XST_GND (
    .G(N6076)
  );
  FDCE V6_0 (
    .D(V6_0__n0000),
    .CE(V7_0__n0002),
    .CLR(N6076),
    .C(V7_0__n0003),
    .Q(NlwRenamedSig_OI_VBL6)
  );
  INV V3_0__n00021_746 (
    .I(DRVVALV0w),
    .O(V3_0__n00021)
  );
  INV V3_0__n00022_747 (
    .I(Reset),
    .O(V3_0__n00022)
  );
  AND3 V3_0__n00023_748 (
    .I0(V3_0__n00021),
    .I1(DRVVALV1w),
    .I2(V3_0__n00022),
    .O(V3_0__n00023)
  );
  INV V7_1__n00001_749 (
    .I(inDATA[7]),
    .O(V7_1__n00001)
  );
  INV V7_1__n00002_750 (
    .I(NlwRenamedSig_OI_VBL7),
    .O(V7_1__n00002)
  );
  INV V7_1__n00003_751 (
    .I(DRVVALV1w),
    .O(V7_1__n00003)
  );
  AND2 V7_1__n00004_752 (
    .I0(inDATA[7]),
    .I1(DRVVALV1w),
    .O(V7_1__n00004)
  );
  INV V7_1__n00005_753 (
    .I(inDATA[6]),
    .O(V7_1__n00005)
  );
  INV V7_1__n00006_754 (
    .I(NlwRenamedSig_OI_VBL7),
    .O(V7_1__n00006)
  );
  INV V7_1__n00007_755 (
    .I(Reset),
    .O(V7_1__n00007)
  );
  AND3 V7_1__n00008_756 (
    .I0(V7_1__n00001),
    .I1(inDATA[6]),
    .I2(V7_1__n00002),
    .O(V7_1__n00008)
  );
  AND2 V7_1__n00009_757 (
    .I0(V7_1__n00005),
    .I1(V7_1__n00006),
    .O(V7_1__n00009)
  );
  OR2 V7_1__n000010_758 (
    .I0(V7_1__n00008),
    .I1(V7_1__n00003),
    .O(V7_1__n000010)
  );
  AND2 V7_1__n000011_759 (
    .I0(V7_1__n00004),
    .I1(V7_1__n00009),
    .O(V7_1__n000011)
  );
  AND2 V7_1__n000012_760 (
    .I0(NlwRenamedSig_OI_VBH7),
    .I1(V7_1__n000010),
    .O(V7_1__n000012)
  );
  OR2 V7_1__n000013_761 (
    .I0(V7_1__n000012),
    .I1(V7_1__n000011),
    .O(V7_1__n000013)
  );
  INV V7_0__n00001_762 (
    .I(inDATA[6]),
    .O(V7_0__n00001)
  );
  INV V7_0__n00002_763 (
    .I(NlwRenamedSig_OI_VBH7),
    .O(V7_0__n00002)
  );
  INV V7_0__n00003_764 (
    .I(DRVVALV1w),
    .O(V7_0__n00003)
  );
  AND2 V7_0__n00004_765 (
    .I0(inDATA[6]),
    .I1(DRVVALV1w),
    .O(V7_0__n00004)
  );
  INV V7_0__n00005_766 (
    .I(inDATA[7]),
    .O(V7_0__n00005)
  );
  INV V7_0__n00006_767 (
    .I(NlwRenamedSig_OI_VBH7),
    .O(V7_0__n00006)
  );
  INV V7_0__n00007_768 (
    .I(Reset),
    .O(V7_0__n00007)
  );
  AND3 V7_0__n00008_769 (
    .I0(V7_0__n00001),
    .I1(inDATA[7]),
    .I2(V7_0__n00002),
    .O(V7_0__n00008)
  );
  AND2 V7_0__n00009_770 (
    .I0(V7_0__n00005),
    .I1(V7_0__n00006),
    .O(V7_0__n00009)
  );
  OR2 V7_0__n000010_771 (
    .I0(V7_0__n00008),
    .I1(V7_0__n00003),
    .O(V7_0__n000010)
  );
  AND2 V7_0__n000011_772 (
    .I0(V7_0__n00004),
    .I1(V7_0__n00009),
    .O(V7_0__n000011)
  );
  AND2 V7_0__n000012_773 (
    .I0(NlwRenamedSig_OI_VBL7),
    .I1(V7_0__n000010),
    .O(V7_0__n000012)
  );
  OR2 V7_0__n000013_774 (
    .I0(V7_0__n000012),
    .I1(V7_0__n000011),
    .O(V7_0__n000013)
  );
  INV V6_1__n00001_775 (
    .I(inDATA[5]),
    .O(V6_1__n00001)
  );
  INV V6_1__n00002_776 (
    .I(NlwRenamedSig_OI_VBL6),
    .O(V6_1__n00002)
  );
  INV V6_1__n00003_777 (
    .I(DRVVALV1w),
    .O(V6_1__n00003)
  );
  AND2 V6_1__n00004_778 (
    .I0(inDATA[5]),
    .I1(DRVVALV1w),
    .O(V6_1__n00004)
  );
  INV V6_1__n00005_779 (
    .I(inDATA[4]),
    .O(V6_1__n00005)
  );
  INV V6_1__n00006_780 (
    .I(NlwRenamedSig_OI_VBL6),
    .O(V6_1__n00006)
  );
  INV V6_1__n00007_781 (
    .I(Reset),
    .O(V6_1__n00007)
  );
  AND3 V6_1__n00008_782 (
    .I0(V6_1__n00001),
    .I1(inDATA[4]),
    .I2(V6_1__n00002),
    .O(V6_1__n00008)
  );
  AND2 V6_1__n00009_783 (
    .I0(V6_1__n00005),
    .I1(V6_1__n00006),
    .O(V6_1__n00009)
  );
  OR2 V6_1__n000010_784 (
    .I0(V6_1__n00008),
    .I1(V6_1__n00003),
    .O(V6_1__n000010)
  );
  AND2 V6_1__n000011_785 (
    .I0(V6_1__n00004),
    .I1(V6_1__n00009),
    .O(V6_1__n000011)
  );
  AND2 V6_1__n000012_786 (
    .I0(NlwRenamedSig_OI_VBH6),
    .I1(V6_1__n000010),
    .O(V6_1__n000012)
  );
  OR2 V6_1__n000013_787 (
    .I0(V6_1__n000012),
    .I1(V6_1__n000011),
    .O(V6_1__n000013)
  );
  INV V6_0__n00001_788 (
    .I(inDATA[4]),
    .O(V6_0__n00001)
  );
  INV V6_0__n00002_789 (
    .I(NlwRenamedSig_OI_VBH6),
    .O(V6_0__n00002)
  );
  INV V6_0__n00003_790 (
    .I(DRVVALV1w),
    .O(V6_0__n00003)
  );
  AND2 V6_0__n00004_791 (
    .I0(inDATA[4]),
    .I1(DRVVALV1w),
    .O(V6_0__n00004)
  );
  INV V6_0__n00005_792 (
    .I(inDATA[5]),
    .O(V6_0__n00005)
  );
  INV V6_0__n00006_793 (
    .I(NlwRenamedSig_OI_VBH6),
    .O(V6_0__n00006)
  );
  INV V6_0__n00007_794 (
    .I(Reset),
    .O(V6_0__n00007)
  );
  AND3 V6_0__n00008_795 (
    .I0(V6_0__n00001),
    .I1(inDATA[5]),
    .I2(V6_0__n00002),
    .O(V6_0__n00008)
  );
  AND2 V6_0__n00009_796 (
    .I0(V6_0__n00005),
    .I1(V6_0__n00006),
    .O(V6_0__n00009)
  );
  OR2 V6_0__n000010_797 (
    .I0(V6_0__n00008),
    .I1(V6_0__n00003),
    .O(V6_0__n000010)
  );
  AND2 V6_0__n000011_798 (
    .I0(V6_0__n00004),
    .I1(V6_0__n00009),
    .O(V6_0__n000011)
  );
  AND2 V6_0__n000012_799 (
    .I0(NlwRenamedSig_OI_VBL6),
    .I1(V6_0__n000010),
    .O(V6_0__n000012)
  );
  OR2 V6_0__n000013_800 (
    .I0(V6_0__n000012),
    .I1(V6_0__n000011),
    .O(V6_0__n000013)
  );
  INV V5_1__n00001_801 (
    .I(inDATA[3]),
    .O(V5_1__n00001)
  );
  INV V5_1__n00002_802 (
    .I(NlwRenamedSig_OI_VBL5),
    .O(V5_1__n00002)
  );
  INV V5_1__n00003_803 (
    .I(DRVVALV1w),
    .O(V5_1__n00003)
  );
  AND2 V5_1__n00004_804 (
    .I0(inDATA[3]),
    .I1(DRVVALV1w),
    .O(V5_1__n00004)
  );
  INV V5_1__n00005_805 (
    .I(inDATA[2]),
    .O(V5_1__n00005)
  );
  INV V5_1__n00006_806 (
    .I(NlwRenamedSig_OI_VBL5),
    .O(V5_1__n00006)
  );
  INV V5_1__n00007_807 (
    .I(Reset),
    .O(V5_1__n00007)
  );
  AND3 V5_1__n00008_808 (
    .I0(V5_1__n00001),
    .I1(inDATA[2]),
    .I2(V5_1__n00002),
    .O(V5_1__n00008)
  );
  AND2 V5_1__n00009_809 (
    .I0(V5_1__n00005),
    .I1(V5_1__n00006),
    .O(V5_1__n00009)
  );
  OR2 V5_1__n000010_810 (
    .I0(V5_1__n00008),
    .I1(V5_1__n00003),
    .O(V5_1__n000010)
  );
  AND2 V5_1__n000011_811 (
    .I0(V5_1__n00004),
    .I1(V5_1__n00009),
    .O(V5_1__n000011)
  );
  AND2 V5_1__n000012_812 (
    .I0(NlwRenamedSig_OI_VBH5),
    .I1(V5_1__n000010),
    .O(V5_1__n000012)
  );
  OR2 V5_1__n000013_813 (
    .I0(V5_1__n000012),
    .I1(V5_1__n000011),
    .O(V5_1__n000013)
  );
  INV V5_0__n00001_814 (
    .I(inDATA[2]),
    .O(V5_0__n00001)
  );
  INV V5_0__n00002_815 (
    .I(NlwRenamedSig_OI_VBH5),
    .O(V5_0__n00002)
  );
  INV V5_0__n00003_816 (
    .I(DRVVALV1w),
    .O(V5_0__n00003)
  );
  AND2 V5_0__n00004_817 (
    .I0(inDATA[2]),
    .I1(DRVVALV1w),
    .O(V5_0__n00004)
  );
  INV V5_0__n00005_818 (
    .I(inDATA[3]),
    .O(V5_0__n00005)
  );
  INV V5_0__n00006_819 (
    .I(NlwRenamedSig_OI_VBH5),
    .O(V5_0__n00006)
  );
  INV V5_0__n00007_820 (
    .I(Reset),
    .O(V5_0__n00007)
  );
  AND3 V5_0__n00008_821 (
    .I0(V5_0__n00001),
    .I1(inDATA[3]),
    .I2(V5_0__n00002),
    .O(V5_0__n00008)
  );
  AND2 V5_0__n00009_822 (
    .I0(V5_0__n00005),
    .I1(V5_0__n00006),
    .O(V5_0__n00009)
  );
  OR2 V5_0__n000010_823 (
    .I0(V5_0__n00008),
    .I1(V5_0__n00003),
    .O(V5_0__n000010)
  );
  AND2 V5_0__n000011_824 (
    .I0(V5_0__n00004),
    .I1(V5_0__n00009),
    .O(V5_0__n000011)
  );
  AND2 V5_0__n000012_825 (
    .I0(NlwRenamedSig_OI_VBL5),
    .I1(V5_0__n000010),
    .O(V5_0__n000012)
  );
  OR2 V5_0__n000013_826 (
    .I0(V5_0__n000012),
    .I1(V5_0__n000011),
    .O(V5_0__n000013)
  );
  INV V4_1__n00001_827 (
    .I(inDATA[1]),
    .O(V4_1__n00001)
  );
  INV V4_1__n00002_828 (
    .I(NlwRenamedSig_OI_VBL4),
    .O(V4_1__n00002)
  );
  INV V4_1__n00003_829 (
    .I(DRVVALV1w),
    .O(V4_1__n00003)
  );
  AND2 V4_1__n00004_830 (
    .I0(inDATA[1]),
    .I1(DRVVALV1w),
    .O(V4_1__n00004)
  );
  INV V4_1__n00005_831 (
    .I(inDATA[0]),
    .O(V4_1__n00005)
  );
  INV V4_1__n00006_832 (
    .I(NlwRenamedSig_OI_VBL4),
    .O(V4_1__n00006)
  );
  INV V4_1__n00007_833 (
    .I(Reset),
    .O(V4_1__n00007)
  );
  AND3 V4_1__n00008_834 (
    .I0(V4_1__n00001),
    .I1(inDATA[0]),
    .I2(V4_1__n00002),
    .O(V4_1__n00008)
  );
  AND2 V4_1__n00009_835 (
    .I0(V4_1__n00005),
    .I1(V4_1__n00006),
    .O(V4_1__n00009)
  );
  OR2 V4_1__n000010_836 (
    .I0(V4_1__n00008),
    .I1(V4_1__n00003),
    .O(V4_1__n000010)
  );
  AND2 V4_1__n000011_837 (
    .I0(V4_1__n00004),
    .I1(V4_1__n00009),
    .O(V4_1__n000011)
  );
  AND2 V4_1__n000012_838 (
    .I0(NlwRenamedSig_OI_VBH4),
    .I1(V4_1__n000010),
    .O(V4_1__n000012)
  );
  OR2 V4_1__n000013_839 (
    .I0(V4_1__n000012),
    .I1(V4_1__n000011),
    .O(V4_1__n000013)
  );
  INV V7_0__n00021_840 (
    .I(Reset),
    .O(V7_0__n00021)
  );
  AND2 V7_0__n00022_841 (
    .I0(DRVVALV0w),
    .I1(V7_0__n00021),
    .O(V7_0__n00022)
  );
  INV V4_0__n00001_842 (
    .I(inDATA[0]),
    .O(V4_0__n00001)
  );
  INV V4_0__n00002_843 (
    .I(NlwRenamedSig_OI_VBH4),
    .O(V4_0__n00002)
  );
  INV V4_0__n00003_844 (
    .I(DRVVALV1w),
    .O(V4_0__n00003)
  );
  AND2 V4_0__n00004_845 (
    .I0(inDATA[0]),
    .I1(DRVVALV1w),
    .O(V4_0__n00004)
  );
  INV V4_0__n00005_846 (
    .I(inDATA[1]),
    .O(V4_0__n00005)
  );
  INV V4_0__n00006_847 (
    .I(NlwRenamedSig_OI_VBH4),
    .O(V4_0__n00006)
  );
  INV V4_0__n00007_848 (
    .I(Reset),
    .O(V4_0__n00007)
  );
  AND3 V4_0__n00008_849 (
    .I0(V4_0__n00001),
    .I1(inDATA[1]),
    .I2(V4_0__n00002),
    .O(V4_0__n00008)
  );
  AND2 V4_0__n00009_850 (
    .I0(V4_0__n00005),
    .I1(V4_0__n00006),
    .O(V4_0__n00009)
  );
  OR2 V4_0__n000010_851 (
    .I0(V4_0__n00008),
    .I1(V4_0__n00003),
    .O(V4_0__n000010)
  );
  AND2 V4_0__n000011_852 (
    .I0(V4_0__n00004),
    .I1(V4_0__n00009),
    .O(V4_0__n000011)
  );
  AND2 V4_0__n000012_853 (
    .I0(NlwRenamedSig_OI_VBL4),
    .I1(V4_0__n000010),
    .O(V4_0__n000012)
  );
  OR2 V4_0__n000013_854 (
    .I0(V4_0__n000012),
    .I1(V4_0__n000011),
    .O(V4_0__n000013)
  );
  INV V3_1__n00001_855 (
    .I(inDATA[7]),
    .O(V3_1__n00001)
  );
  INV V3_1__n00002_856 (
    .I(NlwRenamedSig_OI_VBL3),
    .O(V3_1__n00002)
  );
  INV V3_1__n00003_857 (
    .I(DRVVALV0w),
    .O(V3_1__n00003)
  );
  AND2 V3_1__n00004_858 (
    .I0(inDATA[7]),
    .I1(DRVVALV0w),
    .O(V3_1__n00004)
  );
  INV V3_1__n00005_859 (
    .I(inDATA[6]),
    .O(V3_1__n00005)
  );
  INV V3_1__n00006_860 (
    .I(NlwRenamedSig_OI_VBL3),
    .O(V3_1__n00006)
  );
  INV V3_1__n00007_861 (
    .I(Reset),
    .O(V3_1__n00007)
  );
  AND3 V3_1__n00008_862 (
    .I0(V3_1__n00001),
    .I1(inDATA[6]),
    .I2(V3_1__n00002),
    .O(V3_1__n00008)
  );
  AND2 V3_1__n00009_863 (
    .I0(V3_1__n00005),
    .I1(V3_1__n00006),
    .O(V3_1__n00009)
  );
  OR2 V3_1__n000010_864 (
    .I0(V3_1__n00008),
    .I1(V3_1__n00003),
    .O(V3_1__n000010)
  );
  AND2 V3_1__n000011_865 (
    .I0(V3_1__n00004),
    .I1(V3_1__n00009),
    .O(V3_1__n000011)
  );
  AND2 V3_1__n000012_866 (
    .I0(NlwRenamedSig_OI_VBH3),
    .I1(V3_1__n000010),
    .O(V3_1__n000012)
  );
  OR2 V3_1__n000013_867 (
    .I0(V3_1__n000012),
    .I1(V3_1__n000011),
    .O(V3_1__n000013)
  );
  INV V3_0__n00001_868 (
    .I(inDATA[6]),
    .O(V3_0__n00001)
  );
  INV V3_0__n00002_869 (
    .I(NlwRenamedSig_OI_VBH3),
    .O(V3_0__n00002)
  );
  INV V3_0__n00003_870 (
    .I(DRVVALV0w),
    .O(V3_0__n00003)
  );
  AND2 V3_0__n00004_871 (
    .I0(inDATA[6]),
    .I1(DRVVALV0w),
    .O(V3_0__n00004)
  );
  INV V3_0__n00005_872 (
    .I(inDATA[7]),
    .O(V3_0__n00005)
  );
  INV V3_0__n00006_873 (
    .I(NlwRenamedSig_OI_VBH3),
    .O(V3_0__n00006)
  );
  INV V3_0__n00007_874 (
    .I(Reset),
    .O(V3_0__n00007)
  );
  AND3 V3_0__n00008_875 (
    .I0(V3_0__n00001),
    .I1(inDATA[7]),
    .I2(V3_0__n00002),
    .O(V3_0__n00008)
  );
  AND2 V3_0__n00009_876 (
    .I0(V3_0__n00005),
    .I1(V3_0__n00006),
    .O(V3_0__n00009)
  );
  OR2 V3_0__n000010_877 (
    .I0(V3_0__n00008),
    .I1(V3_0__n00003),
    .O(V3_0__n000010)
  );
  AND2 V3_0__n000011_878 (
    .I0(V3_0__n00004),
    .I1(V3_0__n00009),
    .O(V3_0__n000011)
  );
  AND2 V3_0__n000012_879 (
    .I0(NlwRenamedSig_OI_VBL3),
    .I1(V3_0__n000010),
    .O(V3_0__n000012)
  );
  OR2 V3_0__n000013_880 (
    .I0(V3_0__n000012),
    .I1(V3_0__n000011),
    .O(V3_0__n000013)
  );
  INV V2_1__n00001_881 (
    .I(inDATA[5]),
    .O(V2_1__n00001)
  );
  INV V2_1__n00002_882 (
    .I(NlwRenamedSig_OI_VBL2),
    .O(V2_1__n00002)
  );
  INV V2_1__n00003_883 (
    .I(DRVVALV0w),
    .O(V2_1__n00003)
  );
  AND2 V2_1__n00004_884 (
    .I0(inDATA[5]),
    .I1(DRVVALV0w),
    .O(V2_1__n00004)
  );
  INV V2_1__n00005_885 (
    .I(inDATA[4]),
    .O(V2_1__n00005)
  );
  INV V2_1__n00006_886 (
    .I(NlwRenamedSig_OI_VBL2),
    .O(V2_1__n00006)
  );
  INV V2_1__n00007_887 (
    .I(Reset),
    .O(V2_1__n00007)
  );
  AND3 V2_1__n00008_888 (
    .I0(V2_1__n00001),
    .I1(inDATA[4]),
    .I2(V2_1__n00002),
    .O(V2_1__n00008)
  );
  AND2 V2_1__n00009_889 (
    .I0(V2_1__n00005),
    .I1(V2_1__n00006),
    .O(V2_1__n00009)
  );
  OR2 V2_1__n000010_890 (
    .I0(V2_1__n00008),
    .I1(V2_1__n00003),
    .O(V2_1__n000010)
  );
  AND2 V2_1__n000011_891 (
    .I0(V2_1__n00004),
    .I1(V2_1__n00009),
    .O(V2_1__n000011)
  );
  AND2 V2_1__n000012_892 (
    .I0(NlwRenamedSig_OI_VBH2),
    .I1(V2_1__n000010),
    .O(V2_1__n000012)
  );
  OR2 V2_1__n000013_893 (
    .I0(V2_1__n000012),
    .I1(V2_1__n000011),
    .O(V2_1__n000013)
  );
  INV V2_0__n00001_894 (
    .I(inDATA[4]),
    .O(V2_0__n00001)
  );
  INV V2_0__n00002_895 (
    .I(NlwRenamedSig_OI_VBH2),
    .O(V2_0__n00002)
  );
  INV V2_0__n00003_896 (
    .I(DRVVALV0w),
    .O(V2_0__n00003)
  );
  AND2 V2_0__n00004_897 (
    .I0(inDATA[4]),
    .I1(DRVVALV0w),
    .O(V2_0__n00004)
  );
  INV V2_0__n00005_898 (
    .I(inDATA[5]),
    .O(V2_0__n00005)
  );
  INV V2_0__n00006_899 (
    .I(NlwRenamedSig_OI_VBH2),
    .O(V2_0__n00006)
  );
  INV V2_0__n00007_900 (
    .I(Reset),
    .O(V2_0__n00007)
  );
  AND3 V2_0__n00008_901 (
    .I0(V2_0__n00001),
    .I1(inDATA[5]),
    .I2(V2_0__n00002),
    .O(V2_0__n00008)
  );
  AND2 V2_0__n00009_902 (
    .I0(V2_0__n00005),
    .I1(V2_0__n00006),
    .O(V2_0__n00009)
  );
  OR2 V2_0__n000010_903 (
    .I0(V2_0__n00008),
    .I1(V2_0__n00003),
    .O(V2_0__n000010)
  );
  AND2 V2_0__n000011_904 (
    .I0(V2_0__n00004),
    .I1(V2_0__n00009),
    .O(V2_0__n000011)
  );
  AND2 V2_0__n000012_905 (
    .I0(NlwRenamedSig_OI_VBL2),
    .I1(V2_0__n000010),
    .O(V2_0__n000012)
  );
  OR2 V2_0__n000013_906 (
    .I0(V2_0__n000012),
    .I1(V2_0__n000011),
    .O(V2_0__n000013)
  );
  INV V1_1__n00001_907 (
    .I(inDATA[3]),
    .O(V1_1__n00001)
  );
  INV V1_1__n00002_908 (
    .I(NlwRenamedSig_OI_VBL1),
    .O(V1_1__n00002)
  );
  INV V1_1__n00003_909 (
    .I(DRVVALV0w),
    .O(V1_1__n00003)
  );
  AND2 V1_1__n00004_910 (
    .I0(inDATA[3]),
    .I1(DRVVALV0w),
    .O(V1_1__n00004)
  );
  INV V1_1__n00005_911 (
    .I(inDATA[2]),
    .O(V1_1__n00005)
  );
  INV V1_1__n00006_912 (
    .I(NlwRenamedSig_OI_VBL1),
    .O(V1_1__n00006)
  );
  INV V1_1__n00007_913 (
    .I(Reset),
    .O(V1_1__n00007)
  );
  AND3 V1_1__n00008_914 (
    .I0(V1_1__n00001),
    .I1(inDATA[2]),
    .I2(V1_1__n00002),
    .O(V1_1__n00008)
  );
  AND2 V1_1__n00009_915 (
    .I0(V1_1__n00005),
    .I1(V1_1__n00006),
    .O(V1_1__n00009)
  );
  OR2 V1_1__n000010_916 (
    .I0(V1_1__n00008),
    .I1(V1_1__n00003),
    .O(V1_1__n000010)
  );
  AND2 V1_1__n000011_917 (
    .I0(V1_1__n00004),
    .I1(V1_1__n00009),
    .O(V1_1__n000011)
  );
  AND2 V1_1__n000012_918 (
    .I0(NlwRenamedSig_OI_VBH1),
    .I1(V1_1__n000010),
    .O(V1_1__n000012)
  );
  OR2 V1_1__n000013_919 (
    .I0(V1_1__n000012),
    .I1(V1_1__n000011),
    .O(V1_1__n000013)
  );
  INV V1_0__n00001_920 (
    .I(inDATA[2]),
    .O(V1_0__n00001)
  );
  INV V1_0__n00002_921 (
    .I(NlwRenamedSig_OI_VBH1),
    .O(V1_0__n00002)
  );
  INV V1_0__n00003_922 (
    .I(DRVVALV0w),
    .O(V1_0__n00003)
  );
  AND2 V1_0__n00004_923 (
    .I0(inDATA[2]),
    .I1(DRVVALV0w),
    .O(V1_0__n00004)
  );
  INV V1_0__n00005_924 (
    .I(inDATA[3]),
    .O(V1_0__n00005)
  );
  INV V1_0__n00006_925 (
    .I(NlwRenamedSig_OI_VBH1),
    .O(V1_0__n00006)
  );
  INV V1_0__n00007_926 (
    .I(Reset),
    .O(V1_0__n00007)
  );
  AND3 V1_0__n00008_927 (
    .I0(V1_0__n00001),
    .I1(inDATA[3]),
    .I2(V1_0__n00002),
    .O(V1_0__n00008)
  );
  AND2 V1_0__n00009_928 (
    .I0(V1_0__n00005),
    .I1(V1_0__n00006),
    .O(V1_0__n00009)
  );
  OR2 V1_0__n000010_929 (
    .I0(V1_0__n00008),
    .I1(V1_0__n00003),
    .O(V1_0__n000010)
  );
  AND2 V1_0__n000011_930 (
    .I0(V1_0__n00004),
    .I1(V1_0__n00009),
    .O(V1_0__n000011)
  );
  AND2 V1_0__n000012_931 (
    .I0(NlwRenamedSig_OI_VBL1),
    .I1(V1_0__n000010),
    .O(V1_0__n000012)
  );
  OR2 V1_0__n000013_932 (
    .I0(V1_0__n000012),
    .I1(V1_0__n000011),
    .O(V1_0__n000013)
  );
  INV V0_1__n00001_933 (
    .I(inDATA[1]),
    .O(V0_1__n00001)
  );
  INV V0_1__n00002_934 (
    .I(NlwRenamedSig_OI_VBL0),
    .O(V0_1__n00002)
  );
  INV V0_1__n00003_935 (
    .I(DRVVALV0w),
    .O(V0_1__n00003)
  );
  AND2 V0_1__n00004_936 (
    .I0(inDATA[1]),
    .I1(DRVVALV0w),
    .O(V0_1__n00004)
  );
  INV V0_1__n00005_937 (
    .I(inDATA[0]),
    .O(V0_1__n00005)
  );
  INV V0_1__n00006_938 (
    .I(NlwRenamedSig_OI_VBL0),
    .O(V0_1__n00006)
  );
  INV V0_1__n00007_939 (
    .I(Reset),
    .O(V0_1__n00007)
  );
  AND3 V0_1__n00008_940 (
    .I0(V0_1__n00001),
    .I1(inDATA[0]),
    .I2(V0_1__n00002),
    .O(V0_1__n00008)
  );
  AND2 V0_1__n00009_941 (
    .I0(V0_1__n00005),
    .I1(V0_1__n00006),
    .O(V0_1__n00009)
  );
  OR2 V0_1__n000010_942 (
    .I0(V0_1__n00008),
    .I1(V0_1__n00003),
    .O(V0_1__n000010)
  );
  AND2 V0_1__n000011_943 (
    .I0(V0_1__n00004),
    .I1(V0_1__n00009),
    .O(V0_1__n000011)
  );
  AND2 V0_1__n000012_944 (
    .I0(NlwRenamedSig_OI_VBH0),
    .I1(V0_1__n000010),
    .O(V0_1__n000012)
  );
  OR2 V0_1__n000013_945 (
    .I0(V0_1__n000012),
    .I1(V0_1__n000011),
    .O(V0_1__n000013)
  );
  INV V0_0__n00001_946 (
    .I(inDATA[0]),
    .O(V0_0__n00001)
  );
  INV V0_0__n00002_947 (
    .I(NlwRenamedSig_OI_VBH0),
    .O(V0_0__n00002)
  );
  INV V0_0__n00003_948 (
    .I(DRVVALV0w),
    .O(V0_0__n00003)
  );
  AND2 V0_0__n00004_949 (
    .I0(inDATA[0]),
    .I1(DRVVALV0w),
    .O(V0_0__n00004)
  );
  INV V0_0__n00005_950 (
    .I(inDATA[1]),
    .O(V0_0__n00005)
  );
  INV V0_0__n00006_951 (
    .I(NlwRenamedSig_OI_VBH0),
    .O(V0_0__n00006)
  );
  INV V0_0__n00007_952 (
    .I(Reset),
    .O(V0_0__n00007)
  );
  AND3 V0_0__n00008_953 (
    .I0(V0_0__n00001),
    .I1(inDATA[1]),
    .I2(V0_0__n00002),
    .O(V0_0__n00008)
  );
  AND2 V0_0__n00009_954 (
    .I0(V0_0__n00005),
    .I1(V0_0__n00006),
    .O(V0_0__n00009)
  );
  OR2 V0_0__n000010_955 (
    .I0(V0_0__n00008),
    .I1(V0_0__n00003),
    .O(V0_0__n000010)
  );
  AND2 V0_0__n000011_956 (
    .I0(V0_0__n00004),
    .I1(V0_0__n00009),
    .O(V0_0__n000011)
  );
  AND2 V0_0__n000012_957 (
    .I0(NlwRenamedSig_OI_VBL0),
    .I1(V0_0__n000010),
    .O(V0_0__n000012)
  );
  OR2 V0_0__n000013_958 (
    .I0(V0_0__n000012),
    .I1(V0_0__n000011),
    .O(V0_0__n000013)
  );
endmodule

module AnalogSel (
  DRVCURSELw, Reset, Mclk, ACE, AS0, AS1, AS2, inDATA
);
  input DRVCURSELw;
  input Reset;
  input Mclk;
  output ACE;
  output AS0;
  output AS1;
  output AS2;
  input [7 : 0] inDATA;
  wire NlwRenamedSignal_AS2;
  assign
    ACE = NlwRenamedSignal_AS2,
    AS0 = NlwRenamedSignal_AS2,
    AS1 = NlwRenamedSignal_AS2,
    AS2 = NlwRenamedSignal_AS2;
  GND XST_GND (
    .G(NlwRenamedSignal_AS2)
  );
endmodule

module U4 (
  R0flg, AS, R0data, R2flg, R1data, RD, GPIO8, GPIO9, R2data, WR, R1flg, R3data, Mclk, BUSReset, R3flg, Motor4_Phase_B_LIN, Motor1_Phase_B_LIN, 
PhaseB_Low_1, PhaseB_Low_2, PhaseB_Low_3, PhaseB_Low_4, PhaseB_Low_5, PhaseB_Low_6, PhaseB_Low_7, PhaseB_Low_8, PhaseA_Low_1, PhaseA_Low_2, 
PhaseA_Low_3, PhaseA_Low_4, Motor_Power_n, PhaseA_Low_5, Motor2_Phase_A_LIN, PhaseA_Low_6, PhaseA_Low_7, PhaseA_Low_8, Motor3_Phase_B_HIN, 
Current_enable, Motor4_Phase_A_HIN, R1clk, Motor1_Phase_A_HIN, Motor2_Phase_B_LIN, PhaseB_High_1, PhaseB_High_2, PhaseB_High_3, PhaseB_High_4, 
PhaseB_High_5, PhaseB_High_6, PhaseB_High_7, PhaseB_High_8, Motor3_Phase_A_LIN, Motor4_Phase_B_HIN, Motor1_Phase_B_HIN, BusINT, R3clk, PhaseA_High_1, 
PhaseA_High_2, PhaseA_High_3, PhaseA_High_4, Motor2_Phase_A_HIN, PhaseA_High_5, PhaseA_High_6, PhaseA_High_7, Heater_Control, R0clk, PhaseA_High_8, 
R3enable, R2enable, Motor3_Phase_B_LIN, R1enable, R0enable, AS0, AS1, Motor4_Phase_A_LIN, AS2, Motor1_Phase_A_LIN, Motor2_Phase_B_HIN, R2clk, 
Motor_Power, Motor3_Phase_A_HIN, AD
);
  input R0flg;
  input AS;
  input R0data;
  input R2flg;
  input R1data;
  input RD;
  input GPIO8;
  input GPIO9;
  input R2data;
  input WR;
  input R1flg;
  input R3data;
  input Mclk;
  input BUSReset;
  input R3flg;
  output Motor4_Phase_B_LIN;
  output Motor1_Phase_B_LIN;
  output PhaseB_Low_1;
  output PhaseB_Low_2;
  output PhaseB_Low_3;
  output PhaseB_Low_4;
  output PhaseB_Low_5;
  output PhaseB_Low_6;
  output PhaseB_Low_7;
  output PhaseB_Low_8;
  output PhaseA_Low_1;
  output PhaseA_Low_2;
  output PhaseA_Low_3;
  output PhaseA_Low_4;
  output Motor_Power_n;
  output PhaseA_Low_5;
  output Motor2_Phase_A_LIN;
  output PhaseA_Low_6;
  output PhaseA_Low_7;
  output PhaseA_Low_8;
  output Motor3_Phase_B_HIN;
  output Current_enable;
  output Motor4_Phase_A_HIN;
  output R1clk;
  output Motor1_Phase_A_HIN;
  output Motor2_Phase_B_LIN;
  output PhaseB_High_1;
  output PhaseB_High_2;
  output PhaseB_High_3;
  output PhaseB_High_4;
  output PhaseB_High_5;
  output PhaseB_High_6;
  output PhaseB_High_7;
  output PhaseB_High_8;
  output Motor3_Phase_A_LIN;
  output Motor4_Phase_B_HIN;
  output Motor1_Phase_B_HIN;
  output BusINT;
  output R3clk;
  output PhaseA_High_1;
  output PhaseA_High_2;
  output PhaseA_High_3;
  output PhaseA_High_4;
  output Motor2_Phase_A_HIN;
  output PhaseA_High_5;
  output PhaseA_High_6;
  output PhaseA_High_7;
  output Heater_Control;
  output R0clk;
  output PhaseA_High_8;
  output R3enable;
  output R2enable;
  output Motor3_Phase_B_LIN;
  output R1enable;
  output R0enable;
  output AS0;
  output AS1;
  output Motor4_Phase_A_LIN;
  output AS2;
  output Motor1_Phase_A_LIN;
  output Motor2_Phase_B_HIN;
  output R2clk;
  output Motor_Power;
  output Motor3_Phase_A_HIN;
  inout [7 : 0] AD;
  wire R0flg_IBUF;
  wire Motor4_Phase_B_LIN_OBUF;
  wire Motor1_Phase_B_LIN_OBUF;
  wire PhaseB_Low_1_OBUF;
  wire PhaseB_Low_2_OBUF;
  wire PhaseB_Low_3_OBUF;
  wire AS_IBUF;
  wire PhaseB_Low_4_OBUF;
  wire PhaseB_Low_5_OBUF;
  wire PhaseB_Low_6_OBUF;
  wire PhaseB_Low_7_OBUF;
  wire R0data_IBUF;
  wire PhaseB_Low_8_OBUF;
  wire PhaseA_Low_1_OBUF;
  wire PhaseA_Low_2_OBUF;
  wire PhaseA_Low_3_OBUF;
  wire PhaseA_Low_4_OBUF;
  wire Motor_Power_n_OBUF;
  wire PhaseA_Low_5_OBUF;
  wire Motor2_Phase_A_LIN_OBUF;
  wire PhaseA_Low_6_OBUF;
  wire PhaseA_Low_7_OBUF;
  wire PhaseA_Low_8_OBUF;
  wire Motor3_Phase_B_HIN_OBUF;
  wire Current_enable_OBUF;
  wire Motor4_Phase_A_HIN_OBUF;
  wire Motor1_Phase_A_HIN_OBUF;
  wire R2flg_IBUF;
  wire R1data_IBUF;
  wire Motor2_Phase_B_LIN_OBUF;
  wire PhaseB_High_1_OBUF;
  wire PhaseB_High_2_OBUF;
  wire PhaseB_High_3_OBUF;
  wire PhaseB_High_4_OBUF;
  wire PhaseB_High_5_OBUF;
  wire PhaseB_High_6_OBUF;
  wire PhaseB_High_7_OBUF;
  wire PhaseB_High_8_OBUF;
  wire RD_IBUF;
  wire Motor3_Phase_A_LIN_OBUF;
  wire GPIO8_IBUF;
  wire DRV3HIGHr;
  wire Motor4_Phase_B_HIN_OBUF;
  wire Motor1_Phase_B_HIN_OBUF;
  wire R2data_IBUF;
  wire PhaseA_High_1_OBUF;
  wire PhaseA_High_2_OBUF;
  wire PhaseA_High_3_OBUF;
  wire PhaseA_High_4_OBUF;
  wire Motor2_Phase_A_HIN_OBUF;
  wire PhaseA_High_5_OBUF;
  wire PhaseA_High_6_OBUF;
  wire PhaseA_High_7_OBUF;
  wire Heater_Control_OBUF;
  wire PhaseA_High_8_OBUF;
  wire WR_IBUF;
  wire R3enable_OBUF;
  wire R1flg_IBUF;
  wire R2enable_OBUF;
  wire Motor3_Phase_B_LIN_OBUF;
  wire R1enable_OBUF;
  wire R0enable_OBUF;
  wire AS0_OBUF;
  wire AS1_OBUF;
  wire Motor4_Phase_A_LIN_OBUF;
  wire AS2_OBUF;
  wire Motor1_Phase_A_LIN_OBUF;
  wire R3data_IBUF;
  wire Motor2_Phase_B_HIN_OBUF;
  wire Mclk_IBUF;
  wire BUSReset_IBUF;
  wire Motor_Power_OBUF;
  wire Motor3_Phase_A_HIN_OBUF;
  wire R3flg_IBUF;
  wire DRVVALV0w;
  wire DRVMTRCTLw;
  wire DRVVALV1w;
  wire DRV2LOWr;
  wire DRVCURSELw;
  wire DRVCTLw;
  wire DRV0HIGHr;
  wire DRVSTATr;
  wire Reset;
  wire DRV1LOWr;
  wire DRV3LOWr;
  wire DRV1HIGHr;
  wire DRV2HIGHr;
  wire DRV0LOWr;
  wire U3_U3_EncPWR;
  wire U1_ADDR_reg_0__n0002;
  wire U3_U3_EncReg_6__n0000;
  wire U1_ADDR_reg_0__n0000;
  wire U3_U4_EncReg_7__n0000;
  wire U1_ADDR_reg_6__n0000;
  wire U1_ADDR_reg_7__n0000;
  wire U1_WRRDedge;
  wire U1__n0000;
  wire U1__n0003;
  wire U3_U4_EncReg_8__n0000;
  wire U1__n0005;
  wire U3_U4_EncReg_1__n0001;
  wire U1__n0006;
  wire U3_U4_EncReg_4__n0000;
  wire U3_U4_EncReg_2__n0000;
  wire U3_U4_EncReg_1__n0000;
  wire U3_U3_EncReg_3__n0000;
  wire U3_U4_EncReg_3__n0000;
  wire U3_U4_EncReg_6__n0000;
  wire U1__n0021;
  wire U3_U3_EncReg_7__n0000;
  wire U1_Enable_AD;
  wire U1_ASedge;
  wire U1_AutoInc;
  wire U1_ADDR_in_Range;
  wire BusINT_OBUFE;
  wire U3_U4_EncPWR;
  wire U1_ADDR_reg_3__n0000;
  wire U1_ADDR_reg_5__n0000;
  wire U1_ADDR_reg_0__n0003;
  wire U1_ADDR_reg_2__n0000;
  wire U1_ADDR_reg_1__n0000;
  wire U1_ADDR_reg_4__n0000;
  wire U3_U2_EncPWR;
  wire U3_U2_EncReg_6__n0000;
  wire U3_U2_EncReg_4__n0000;
  wire U3_U2_EncReg_1__n0000;
  wire U3_U2_EncPWR__n0000;
  wire U3_U2_EncReg_8__n0000;
  wire U3_U3__n0006;
  wire U3_U3_EncPWR__n0000;
  wire U3_U4_EncReg_0__n0000;
  wire U3_U3_EncReg_5__n0000;
  wire U3_U2_EncReg_0__n0000;
  wire U3_U2_EncReg_5__n0000;
  wire U3_U2__n0006;
  wire U3_U2_EncReg_3__n0000;
  wire U3_U2_EncReg_7__n0000;
  wire U3_U2_EncReg_2__n0000;
  wire U3_NET266;
  wire U3_NET282;
  wire U3_U2_EncReg_2__n0001;
  wire U3_U6_PWRflgier__n0002;
  wire U3_U3_EncReg_0__n0000;
  wire U3_U6_PWRflgier__n0000;
  wire U3_U6_intENCint;
  wire U3_U6_PWRflgier;
  wire U3_U5_EncReg_2__n0000;
  wire U3_U5_EncReg_7__n0000;
  wire U3_U3_EncReg_8__n0000;
  wire U3_U5_EncReg_3__n0000;
  wire U3_U3_EncReg_1__n0001;
  wire U3_U3_EncReg_1__n0000;
  wire U3_U4_EncPWR__n0000;
  wire U3_U5_EncReg_8__n0000;
  wire U3_U5_EncReg_1__n0001;
  wire U3_U5_EncReg_1__n0000;
  wire U3_U5_EncReg_4__n0000;
  wire U3_U5_EncReg_6__n0000;
  wire U3_U5_EncPWR;
  wire U3_U4__n0006;
  wire U3_U4_EncReg_5__n0000;
  wire U3_U5__n0006;
  wire U3_U5_EncReg_5__n0000;
  wire U3_U5_EncReg_0__n0000;
  wire U3_U3_EncReg_4__n0000;
  wire U3_U3_EncReg_2__n0000;
  wire U3_U5_EncPWR__n0000;
  wire U1_ADDR_reg_2__n00001;
  wire U1_ADDR_reg_2__n00002;
  wire U1_ADDR_reg_2__n00003;
  wire U1_ADDR_reg_2__n00004;
  wire U1_ADDR_reg_2__n00005;
  wire U1_ADDR_reg_3__n00001;
  wire U1_ADDR_reg_3__n00002;
  wire U1_ADDR_reg_3__n00003;
  wire U1_ADDR_reg_3__n00004;
  wire U1_ADDR_reg_3__n00005;
  wire U1_ADDR_reg_4__n00001;
  wire U1_ADDR_reg_4__n00002;
  wire U1_ADDR_reg_4__n00003;
  wire U1_ADDR_reg_4__n00004;
  wire U1_ADDR_reg_4__n00005;
  wire U1_ADDR_reg_5__n00001;
  wire U1_ADDR_reg_5__n00002;
  wire U1_ADDR_reg_5__n00003;
  wire U1_ADDR_reg_5__n00004;
  wire U1_ADDR_reg_5__n00005;
  wire U1_ADDR_reg_6__n00001;
  wire U1_ADDR_reg_6__n00002;
  wire U1_ADDR_reg_6__n00003;
  wire U1_ADDR_reg_6__n00004;
  wire U1_ADDR_reg_6__n00005;
  wire U1_ADDR_reg_7__n00001;
  wire U1_ADDR_reg_7__n00002;
  wire U1_ADDR_reg_7__n00003;
  wire U1_ADDR_reg_7__n00004;
  wire U1_ADDR_reg_7__n00005;
  wire U1_ADDR_reg_0__n00021;
  wire U1_ADDR_reg_0__n00022;
  wire U1_ADDR_reg_0__n00023;
  wire U1_ADDR_reg_0__n00024;
  wire U1_ADDR_reg_0__n00025;
  wire U1_ADDR_reg_0__n00026;
  wire U1_ADDR_reg_0__n00027;
  wire U1_ADDR_reg_0__n00028;
  wire U1_ADDR_reg_0__n00029;
  wire U1_ADDR_reg_0__n00001;
  wire U1_ADDR_reg_0__n00002;
  wire U1_ADDR_reg_0__n00003;
  wire U1_ADDR_reg_0__n00004;
  wire U1_ADDR_reg_0__n00005;
  wire U1_ADDR_reg_0__n00006;
  wire U1_ADDR_reg_0__n00007;
  wire U1_ADDR_reg_0__n00008;
  wire U1_ADDR_reg_0__n00009;
  wire U1_ADDR_reg_0__n000010;
  wire U1_ADDR_reg_0__n000011;
  wire U1_ADDR_reg_0__n000012;
  wire U1_ADDR_reg_0__n000013;
  wire U1_ADDR_reg_0__n000014;
  wire U1_ADDR_reg_0__n000015;
  wire U1_ADDR_reg_0__n000016;
  wire U1_ADDR_reg_0__n000017;
  wire U1_ADDR_reg_0__n000018;
  wire U1_ADDR_reg_0__n000019;
  wire U1_ADDR_reg_0__n000020;
  wire U1_ADDR_reg_0__n000021;
  wire U3_U3_Mmux__n0001_I2_Result;
  wire U1__n00031;
  wire U3_U3_Mmux__n0001_I3_Result;
  wire U1_ADDR_reg_1__n00001;
  wire U1_ADDR_reg_1__n00002;
  wire U1_ADDR_reg_1__n00003;
  wire U1_ADDR_reg_1__n00004;
  wire U1_ADDR_reg_1__n00005;
  wire U1_ADDR_in_Range1;
  wire U1_ADDR_in_Range2;
  wire U1_ADDR_in_Range3;
  wire U1_ADDR_in_Range4;
  wire U1_ADDR_in_Range5;
  wire U1_ADDR_in_Range6;
  wire U3_U3_Mmux__n0001_I1_Result;
  wire U1__n00051;
  wire U1__n00052;
  wire U1__n00053;
  wire U1_Enable_AD1;
  wire U1_Enable_AD2;
  wire U1__n00061;
  wire U1__n00062;
  wire U1__n00063;
  wire U1__n00064;
  wire U1__n00065;
  wire U1__n00066;
  wire U1__n00067;
  wire U1__n00068;
  wire U1__n00069;
  wire U1__n000610;
  wire U1__n000611;
  wire U3_U3_Mmux__n0001_I4_Result;
  wire U3_U3_Mmux__n0001_I5_Result;
  wire U3_U2_Mmux__n0001_I1_Result;
  wire U3_U3_Mmux__n0001_I6_Result;
  wire U3_U2_Mmux__n0001_I2_Result;
  wire U3_U2_Mmux__n0001_I3_Result;
  wire U3_U2_EncReg_2__n00011;
  wire U3_U2_EncReg_2__n00012;
  wire U3_U2_Mmux__n0001_I4_Result;
  wire U3_U3_Mmux__n0001_I7_Result;
  wire U3_U3_Mmux__n0001_I7_Result1;
  wire U3_U3_Mmux__n0001_I7_Result2;
  wire U3_U6_intENCint1;
  wire U3_U6_intENCint2;
  wire U3_U6_PWRflgier__n00021;
  wire U3_U6_PWRflgier__n00022;
  wire U3_U5_EncReg_1__n00011;
  wire U3_U5_EncReg_1__n00012;
  wire U3_U5_Mmux__n0001_I0_Result;
  wire U3_U5__n00061;
  wire U3_U5__n00062;
  wire U3_U5__n00063;
  wire U3_U2_Mmux__n0001_I5_Result;
  wire U3_U5_Mmux__n0001_I7_Result;
  wire U3_U5_Mmux__n0001_I7_Result1;
  wire U3_U5_Mmux__n0001_I7_Result2;
  wire U3_U5_Mmux__n0001_I6_Result;
  wire U3_U5_Mmux__n0001_I5_Result;
  wire U3_U5_Mmux__n0001_I4_Result;
  wire U3_U5_Mmux__n0001_I3_Result;
  wire U3_U5_Mmux__n0001_I2_Result;
  wire U3_U5_Mmux__n0001_I1_Result;
  wire U3_U2_Mmux__n0001_I6_Result;
  wire U3_U2_Mmux__n0001_I7_Result;
  wire U3_U2_Mmux__n0001_I7_Result1;
  wire U3_U2_Mmux__n0001_I7_Result2;
  wire U3_U4_EncReg_1__n00011;
  wire U3_U4_EncReg_1__n00012;
  wire U3_U4_Mmux__n0001_I0_Result;
  wire U3_U4__n00061;
  wire U3_U4__n00062;
  wire U3_U4__n00063;
  wire U3_U4_Mmux__n0001_I7_Result;
  wire U3_U4_Mmux__n0001_I7_Result1;
  wire U3_U4_Mmux__n0001_I7_Result2;
  wire U3_U4_Mmux__n0001_I6_Result;
  wire U3_U4_Mmux__n0001_I5_Result;
  wire U3_U4_Mmux__n0001_I4_Result;
  wire U3_U4_Mmux__n0001_I3_Result;
  wire U3_U4_Mmux__n0001_I2_Result;
  wire U3_U4_Mmux__n0001_I1_Result;
  wire U3_U2__n00061;
  wire U3_U2__n00062;
  wire U3_U2__n00063;
  wire U3_U3_EncReg_1__n00011;
  wire U3_U3_EncReg_1__n00012;
  wire U3_U3_Mmux__n0001_I0_Result;
  wire U3_U2_Mmux__n0001_I0_Result;
  wire U3_U3__n00061;
  wire U3_U3__n00062;
  wire U3_U3__n00063;
  wire N11864;
  wire N11866;
  wire N11868;
  wire N11870;
  wire N11872;
  wire N11874;
  wire N11876;
  wire N11878;
  wire [7 : 0] U1_ADDR_reg;
  wire [7 : 0] U3_U3__n0001;
  wire [0 : 0] U1_Madd__n0013__n0016;
  wire [0 : 0] U1_Madd__n0013__n0014;
  wire [7 : 0] outDATA;
  wire [7 : 1] U1__n0013;
  wire [7 : 0] U3_U5__n0001;
  wire [7 : 0] U3_U4__n0001;
  wire [8 : 0] U3_U4_EncReg;
  wire [8 : 0] U3_U3_EncReg;
  wire [8 : 0] U3_U5_EncReg;
  wire [0 : 0] U1_Madd__n0013__n0008;
  wire [0 : 0] U1_Madd__n0013__n0018;
  wire [0 : 0] U1_Madd__n0013__n0010;
  wire [0 : 0] U1_Madd__n0013__n0012;
  wire [8 : 0] U3_U2_EncReg;
  wire [7 : 0] U3_U2__n0001;
  AnalogSel U6 (
    .DRVCURSELw(DRVCURSELw),
    .Reset(Reset),
    .Mclk(Mclk_IBUF),
    .ACE(Current_enable_OBUF),
    .AS0(AS0_OBUF),
    .AS1(AS1_OBUF),
    .AS2(AS2_OBUF),
    .inDATA({N11868, N11866, N11864, N11878, N11876, N11874, N11872, N11870})
  );
  ValveTranslator U5 (
    .DRVVALV0w(DRVVALV0w),
    .DRVVALV1w(DRVVALV1w),
    .Reset(Reset),
    .Mclk(Mclk_IBUF),
    .VAH0(PhaseA_High_1_OBUF),
    .VAH1(PhaseA_High_2_OBUF),
    .VAH2(PhaseA_High_3_OBUF),
    .VAH3(PhaseA_High_4_OBUF),
    .VAH4(PhaseA_High_5_OBUF),
    .VAH5(PhaseA_High_6_OBUF),
    .VAH6(PhaseA_High_7_OBUF),
    .VAH7(PhaseA_High_8_OBUF),
    .VAL0(PhaseA_Low_1_OBUF),
    .VAL1(PhaseA_Low_2_OBUF),
    .VAL2(PhaseA_Low_3_OBUF),
    .VAL3(PhaseA_Low_4_OBUF),
    .VAL4(PhaseA_Low_5_OBUF),
    .VAL5(PhaseA_Low_6_OBUF),
    .VBH0(PhaseB_High_1_OBUF),
    .VAL6(PhaseA_Low_7_OBUF),
    .VBH1(PhaseB_High_2_OBUF),
    .VAL7(PhaseA_Low_8_OBUF),
    .VBH2(PhaseB_High_3_OBUF),
    .VBH3(PhaseB_High_4_OBUF),
    .VBH4(PhaseB_High_5_OBUF),
    .VBH5(PhaseB_High_6_OBUF),
    .VBH6(PhaseB_High_7_OBUF),
    .VBH7(PhaseB_High_8_OBUF),
    .VBL0(PhaseB_Low_1_OBUF),
    .VBL1(PhaseB_Low_2_OBUF),
    .VBL2(PhaseB_Low_3_OBUF),
    .VBL3(PhaseB_Low_4_OBUF),
    .VBL4(PhaseB_Low_5_OBUF),
    .VBL5(PhaseB_Low_6_OBUF),
    .VBL6(PhaseB_Low_7_OBUF),
    .VBL7(PhaseB_Low_8_OBUF),
    .inDATA({N11868, N11866, N11864, N11878, N11876, N11874, N11872, N11870})
  );
  INV Reset1 (
    .I(BUSReset_IBUF),
    .O(Reset)
  );
  INV U1_ADDR_reg_0__n00031 (
    .I(Mclk_IBUF),
    .O(U1_ADDR_reg_0__n0003)
  );
  AddressDecode U2 (
    .RD(RD_IBUF),
    .WR(WR_IBUF),
    .DRVVALV0w(DRVVALV0w),
    .DRVMTRCTLw(DRVMTRCTLw),
    .DRVVALV1w(DRVVALV1w),
    .DRV2LOWr(DRV2LOWr),
    .DRVCURSELw(DRVCURSELw),
    .DRVCTLw(DRVCTLw),
    .DRV0HIGHr(DRV0HIGHr),
    .DRVSTATr(DRVSTATr),
    .DRV3LOWr(DRV3LOWr),
    .DRV1HIGHr(DRV1HIGHr),
    .DRV2HIGHr(DRV2HIGHr),
    .DRV0LOWr(DRV0LOWr),
    .DRV3HIGHr(DRV3HIGHr),
    .DRV1LOWr(DRV1LOWr),
    .ADDR({U1_ADDR_reg[7], U1_ADDR_reg[6], U1_ADDR_reg[5], U1_ADDR_reg[4], U1_ADDR_reg[3], U1_ADDR_reg[2], U1_ADDR_reg[1], U1_ADDR_reg[0]})
  );
  AND2 U3_U3_EncReg_6__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[5]),
    .O(U3_U3_EncReg_6__n0000)
  );
  PWMTranslator U4 (
    .DRVMTRCTLw(DRVMTRCTLw),
    .DRVCTLw(DRVCTLw),
    .Reset(Reset),
    .PWMsource(GPIO8_IBUF),
    .Mclk(Mclk_IBUF),
    .Motor1_Phase_B_LIN(Motor2_Phase_B_LIN_OBUF),
    .Motor2_Phase_A_LIN(Motor3_Phase_A_LIN_OBUF),
    .MTRPWR_n(Motor_Power_n_OBUF),
    .Motor3_Phase_B_HIN(Motor4_Phase_B_HIN_OBUF),
    .Motor0_Phase_B_HIN(Motor1_Phase_B_HIN_OBUF),
    .Motor1_Phase_A_HIN(Motor2_Phase_A_HIN_OBUF),
    .Motor2_Phase_B_LIN(Motor3_Phase_B_LIN_OBUF),
    .Motor3_Phase_A_LIN(Motor4_Phase_A_LIN_OBUF),
    .Motor0_Phase_A_LIN(Motor1_Phase_A_LIN_OBUF),
    .Motor1_Phase_B_HIN(Motor2_Phase_B_HIN_OBUF),
    .Motor2_Phase_A_HIN(Motor3_Phase_A_HIN_OBUF),
    .Motor3_Phase_B_LIN(Motor4_Phase_B_LIN_OBUF),
    .Motor0_Phase_B_LIN(Motor1_Phase_B_LIN_OBUF),
    .Motor1_Phase_A_LIN(Motor2_Phase_A_LIN_OBUF),
    .Motor2_Phase_B_HIN(Motor3_Phase_B_HIN_OBUF),
    .MTRPWR(Motor_Power_OBUF),
    .Motor3_Phase_A_HIN(Motor4_Phase_A_HIN_OBUF),
    .Motor0_Phase_A_HIN(Motor1_Phase_A_HIN_OBUF),
    .inDATA({N11868, N11866, N11864, N11878, N11876, N11874, N11872, N11870})
  );
  AND2 U1_ADDR_reg_2__n00006 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_2__n00005),
    .O(U1_ADDR_reg_2__n0000)
  );
  AND2 U1_ADDR_reg_3__n00006 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_3__n00005),
    .O(U1_ADDR_reg_3__n0000)
  );
  AND2 U1_ADDR_reg_4__n00006 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_4__n00005),
    .O(U1_ADDR_reg_4__n0000)
  );
  AND2 U1_ADDR_reg_5__n00006 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_5__n00005),
    .O(U1_ADDR_reg_5__n0000)
  );
  OBUF Motor3_Phase_A_HIN_OBUF_1395 (
    .I(Motor3_Phase_A_HIN_OBUF),
    .O(Motor3_Phase_A_HIN)
  );
  AND2 U1_ADDR_reg_6__n00006 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_6__n00005),
    .O(U1_ADDR_reg_6__n0000)
  );
  AND2 U1_ADDR_reg_7__n00006 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_7__n00005),
    .O(U1_ADDR_reg_7__n0000)
  );
  AND2 U1__n00001 (
    .I0(WR_IBUF),
    .I1(RD_IBUF),
    .O(U1__n0000)
  );
  INV U1__n00211 (
    .I(AS_IBUF),
    .O(U1__n0021)
  );
  OBUFE R0clk_OBUFE (
    .E(U3_U2_EncPWR),
    .I(U3_NET266),
    .O(R0clk)
  );
  FDCE U3_U3_EncReg_0 (
    .D(U3_U3_EncReg_0__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[0])
  );
  BUFE U3_U3_I4_5 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[5]),
    .O(outDATA[5])
  );
  OR2 U1_ADDR_reg_0__n000210 (
    .I0(U1_ADDR_reg_0__n00029),
    .I1(U1_ADDR_reg_0__n00025),
    .O(U1_ADDR_reg_0__n0002)
  );
  FDCE U3_U3_EncReg_8 (
    .D(U3_U3_EncReg_8__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[8])
  );
  AND2 U1_ADDR_reg_0__n000022 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_0__n000021),
    .O(U1_ADDR_reg_0__n0000)
  );
  AND2 U3_U3_Mmux__n0001_I2_Result2 (
    .I0(U3_U3_EncReg[5]),
    .I1(U3_U3_Mmux__n0001_I2_Result),
    .O(U3_U3__n0001[5])
  );
  FDCE U3_U3_EncReg_1 (
    .D(U3_U3_EncReg_1__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[1])
  );
  FDCE U3_U3_EncReg_4 (
    .D(U3_U3_EncReg_4__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[4])
  );
  AND2 U3_U3_EncReg_8__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[7]),
    .O(U3_U3_EncReg_8__n0000)
  );
  AND2 U1__n00032 (
    .I0(U1_WRRDedge),
    .I1(U1__n00031),
    .O(U1__n0003)
  );
  AND2 U3_U3_Mmux__n0001_I3_Result2 (
    .I0(U3_U3_EncReg[4]),
    .I1(U3_U3_Mmux__n0001_I3_Result),
    .O(U3_U3__n0001[4])
  );
  AND2 U1_ADDR_reg_1__n00006 (
    .I0(BUSReset_IBUF),
    .I1(U1_ADDR_reg_1__n00005),
    .O(U1_ADDR_reg_1__n0000)
  );
  FD U1_ASedge_1396 (
    .D(AS_IBUF),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ASedge)
  );
  FD U1_WRRDedge_1397 (
    .D(U1__n0000),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_WRRDedge)
  );
  FDCE U3_U3_EncReg_7 (
    .D(U3_U3_EncReg_7__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[7])
  );
  GND XST_GND (
    .G(BusINT_OBUFE)
  );
  IOBUFE AD_7_IOBUFE (
    .I(outDATA[7]),
    .E(U1_Enable_AD),
    .O(N11868),
    .IO(AD[7])
  );
  AND2 U1_ADDR_in_Range7 (
    .I0(U1_ADDR_in_Range5),
    .I1(U1_ADDR_in_Range6),
    .O(U1_ADDR_in_Range)
  );
  FDCE U3_U3_EncReg_3 (
    .D(U3_U3_EncReg_3__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[3])
  );
  AND2 U3_U3_Mmux__n0001_I1_Result2 (
    .I0(U3_U3_EncReg[6]),
    .I1(U3_U3_Mmux__n0001_I1_Result),
    .O(U3_U3__n0001[6])
  );
  LPM_XOR2_1 U1_Madd__n0013_Mxor_Result_1_ (
    .Data_0_(U1_ADDR_reg[0]),
    .Data_1_(U1_ADDR_reg[1]),
    .Result(U1__n0013[1])
  );
  AND2 U1__n00054 (
    .I0(U1__n00051),
    .I1(U1__n00053),
    .O(U1__n0005)
  );
  FDCE U3_U3_EncReg_2 (
    .D(U3_U3_EncReg_2__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[2])
  );
  AND2 U1_Enable_AD3 (
    .I0(U1_Enable_AD1),
    .I1(U1_Enable_AD2),
    .O(U1_Enable_AD)
  );
  AND2 U1__n000612 (
    .I0(U1__n000611),
    .I1(U1__n00066),
    .O(U1__n0006)
  );
  IOBUFE AD_6_IOBUFE (
    .I(outDATA[6]),
    .E(U1_Enable_AD),
    .O(N11866),
    .IO(AD[6])
  );
  IOBUFE AD_5_IOBUFE (
    .I(outDATA[5]),
    .E(U1_Enable_AD),
    .O(N11864),
    .IO(AD[5])
  );
  FDCE U1_AutoInc_1398 (
    .D(U1__n0021),
    .CE(U1__n0003),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_AutoInc)
  );
  IOBUFE AD_0_IOBUFE (
    .I(outDATA[0]),
    .E(U1_Enable_AD),
    .O(N11870),
    .IO(AD[0])
  );
  IOBUFE AD_1_IOBUFE (
    .I(outDATA[1]),
    .E(U1_Enable_AD),
    .O(N11872),
    .IO(AD[1])
  );
  IOBUFE AD_2_IOBUFE (
    .I(outDATA[2]),
    .E(U1_Enable_AD),
    .O(N11874),
    .IO(AD[2])
  );
  IOBUFE AD_3_IOBUFE (
    .I(outDATA[3]),
    .E(U1_Enable_AD),
    .O(N11876),
    .IO(AD[3])
  );
  IOBUFE AD_4_IOBUFE (
    .I(outDATA[4]),
    .E(U1_Enable_AD),
    .O(N11878),
    .IO(AD[4])
  );
  FDCE U3_U3_EncReg_6 (
    .D(U3_U3_EncReg_6__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[6])
  );
  AND2 U1_Madd__n0013__n00051 (
    .I0(U1_ADDR_reg[6]),
    .I1(U1_Madd__n0013__n0016[0]),
    .O(U1_Madd__n0013__n0018[0])
  );
  AND2 U1_Madd__n0013__n00041 (
    .I0(U1_ADDR_reg[5]),
    .I1(U1_Madd__n0013__n0014[0]),
    .O(U1_Madd__n0013__n0016[0])
  );
  AND2 U1_Madd__n0013__n00031 (
    .I0(U1_ADDR_reg[4]),
    .I1(U1_Madd__n0013__n0012[0]),
    .O(U1_Madd__n0013__n0014[0])
  );
  AND2 U1_Madd__n0013__n00021 (
    .I0(U1_ADDR_reg[3]),
    .I1(U1_Madd__n0013__n0010[0]),
    .O(U1_Madd__n0013__n0012[0])
  );
  AND2 U1_Madd__n0013__n00011 (
    .I0(U1_ADDR_reg[2]),
    .I1(U1_Madd__n0013__n0008[0]),
    .O(U1_Madd__n0013__n0010[0])
  );
  AND2 U1_Madd__n0013__n00001 (
    .I0(U1_ADDR_reg[1]),
    .I1(U1_ADDR_reg[0]),
    .O(U1_Madd__n0013__n0008[0])
  );
  LPM_XOR2_1 U1_Madd__n0013_Mxor_Result_7_ (
    .Data_0_(U1_Madd__n0013__n0018[0]),
    .Data_1_(U1_ADDR_reg[7]),
    .Result(U1__n0013[7])
  );
  LPM_XOR2_1 U1_Madd__n0013_Mxor_Result_6_ (
    .Data_0_(U1_Madd__n0013__n0016[0]),
    .Data_1_(U1_ADDR_reg[6]),
    .Result(U1__n0013[6])
  );
  LPM_XOR2_1 U1_Madd__n0013_Mxor_Result_5_ (
    .Data_0_(U1_Madd__n0013__n0014[0]),
    .Data_1_(U1_ADDR_reg[5]),
    .Result(U1__n0013[5])
  );
  LPM_XOR2_1 U1_Madd__n0013_Mxor_Result_4_ (
    .Data_0_(U1_Madd__n0013__n0012[0]),
    .Data_1_(U1_ADDR_reg[4]),
    .Result(U1__n0013[4])
  );
  LPM_XOR2_1 U1_Madd__n0013_Mxor_Result_3_ (
    .Data_0_(U1_Madd__n0013__n0010[0]),
    .Data_1_(U1_ADDR_reg[3]),
    .Result(U1__n0013[3])
  );
  LPM_XOR2_1 U1_Madd__n0013_Mxor_Result_2_ (
    .Data_0_(U1_Madd__n0013__n0008[0]),
    .Data_1_(U1_ADDR_reg[2]),
    .Result(U1__n0013[2])
  );
  FDCE U1_ADDR_reg_7 (
    .D(U1_ADDR_reg_7__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[7])
  );
  FDCE U1_ADDR_reg_6 (
    .D(U1_ADDR_reg_6__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[6])
  );
  FDCE U1_ADDR_reg_0 (
    .D(U1_ADDR_reg_0__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[0])
  );
  FDCE U1_ADDR_reg_1 (
    .D(U1_ADDR_reg_1__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[1])
  );
  FDCE U1_ADDR_reg_2 (
    .D(U1_ADDR_reg_2__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[2])
  );
  FDCE U1_ADDR_reg_3 (
    .D(U1_ADDR_reg_3__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[3])
  );
  FDCE U1_ADDR_reg_4 (
    .D(U1_ADDR_reg_4__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[4])
  );
  FDCE U1_ADDR_reg_5 (
    .D(U1_ADDR_reg_5__n0000),
    .CE(U1_ADDR_reg_0__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U1_ADDR_reg[5])
  );
  FDCE U3_U2_EncReg_3 (
    .D(U3_U2_EncReg_3__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[3])
  );
  FDCE U3_U2_EncReg_8 (
    .D(U3_U2_EncReg_8__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[8])
  );
  AND2 U3_U3_Mmux__n0001_I4_Result2 (
    .I0(U3_U3_EncReg[3]),
    .I1(U3_U3_Mmux__n0001_I4_Result),
    .O(U3_U3__n0001[3])
  );
  AND2 U3_U3_Mmux__n0001_I5_Result2 (
    .I0(U3_U3_EncReg[2]),
    .I1(U3_U3_Mmux__n0001_I5_Result),
    .O(U3_U3__n0001[2])
  );
  AND2 U3_U2_EncReg_5__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[4]),
    .O(U3_U2_EncReg_5__n0000)
  );
  AND2 U3_U2_Mmux__n0001_I1_Result2 (
    .I0(U3_U2_EncReg[6]),
    .I1(U3_U2_Mmux__n0001_I1_Result),
    .O(U3_U2__n0001[6])
  );
  AND2 U3_U3_Mmux__n0001_I6_Result2 (
    .I0(U3_U3_EncReg[1]),
    .I1(U3_U3_Mmux__n0001_I6_Result),
    .O(U3_U3__n0001[1])
  );
  FDCE U3_U2_EncReg_2 (
    .D(U3_U2_EncReg_2__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[2])
  );
  AND2 U3_U2_Mmux__n0001_I2_Result2 (
    .I0(U3_U2_EncReg[5]),
    .I1(U3_U2_Mmux__n0001_I2_Result),
    .O(U3_U2__n0001[5])
  );
  AND2 U3_U3_EncPWR__n00001 (
    .I0(BUSReset_IBUF),
    .I1(N11864),
    .O(U3_U3_EncPWR__n0000)
  );
  AND2 U3_U2_EncReg_4__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[3]),
    .O(U3_U2_EncReg_4__n0000)
  );
  AND2 U3_U2_Mmux__n0001_I3_Result2 (
    .I0(U3_U2_EncReg[4]),
    .I1(U3_U2_Mmux__n0001_I3_Result),
    .O(U3_U2__n0001[4])
  );
  OR2 U3_U2_EncReg_2__n00013 (
    .I0(U3_U2_EncReg_2__n00011),
    .I1(U3_U2_EncReg_2__n00012),
    .O(U3_U2_EncReg_2__n0001)
  );
  FDCE U3_U2_EncReg_1 (
    .D(U3_U2_EncReg_1__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[1])
  );
  AND2 U3_U2_Mmux__n0001_I4_Result2 (
    .I0(U3_U2_EncReg[3]),
    .I1(U3_U2_Mmux__n0001_I4_Result),
    .O(U3_U2__n0001[3])
  );
  OR2 U3_U3_Mmux__n0001_I7_Result4 (
    .I0(U3_U3_Mmux__n0001_I7_Result),
    .I1(U3_U3_Mmux__n0001_I7_Result2),
    .O(U3_U3__n0001[0])
  );
  AND2 U3_U2_EncReg_3__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[2]),
    .O(U3_U2_EncReg_3__n0000)
  );
  FDCE U3_U2_EncReg_0 (
    .D(U3_U2_EncReg_0__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[0])
  );
  FDCE U3_U2_EncReg_4 (
    .D(U3_U2_EncReg_4__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[4])
  );
  FDCE U3_U3_EncReg_5 (
    .D(U3_U3_EncReg_5__n0000),
    .CE(U3_U3_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U3_EncReg[5])
  );
  FDCE U3_U2_EncReg_7 (
    .D(U3_U2_EncReg_7__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[7])
  );
  BUFE U3_U3_I4_6 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[6]),
    .O(outDATA[6])
  );
  AND2 U3_U6_PWRflgier__n00001 (
    .I0(BUSReset_IBUF),
    .I1(N11872),
    .O(U3_U6_PWRflgier__n0000)
  );
  BUFE U3_U2_I4_7 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[7]),
    .O(outDATA[7])
  );
  AND2 U3_U3_EncReg_7__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[6]),
    .O(U3_U3_EncReg_7__n0000)
  );
  EncoderControl U3_U1 (
    .DRVCTLw(DRVCTLw),
    .Start(N11870),
    .DRVSTATr(DRVSTATr),
    .Reset(Reset),
    .Mclk(Mclk_IBUF),
    .Shift(U3_NET282),
    .Eclk(U3_NET266),
    .DAV(outDATA[0])
  );
  AND2 U3_U2_EncReg_8__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[7]),
    .O(U3_U2_EncReg_8__n0000)
  );
  BUFE U3_U2_I3_0 (
    .E(DRVSTATr),
    .I(R0flg_IBUF),
    .O(outDATA[4])
  );
  AND2 U3_U2_EncReg_2__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[1]),
    .O(U3_U2_EncReg_2__n0000)
  );
  AND2 U3_U6_intENCint3 (
    .I0(U3_U6_PWRflgier),
    .I1(U3_U6_intENCint2),
    .O(U3_U6_intENCint)
  );
  AND2 U3_U3_EncReg_0__n00001 (
    .I0(BUSReset_IBUF),
    .I1(R1data_IBUF),
    .O(U3_U3_EncReg_0__n0000)
  );
  BUFE U3_U6_I4_0 (
    .E(DRVSTATr),
    .I(U3_U6_PWRflgier),
    .O(outDATA[1])
  );
  FDCE U3_U6_PWRflgier_1399 (
    .D(U3_U6_PWRflgier__n0000),
    .CE(U3_U6_PWRflgier__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U3_U6_PWRflgier)
  );
  OBUFE BusINT_OBUFE_1400 (
    .E(U3_U6_intENCint),
    .I(BusINT_OBUFE),
    .O(BusINT)
  );
  BUFE U3_U6_I2_0 (
    .E(DRVSTATr),
    .I(BusINT_OBUFE),
    .O(outDATA[3])
  );
  BUFE U3_U6_I3_0 (
    .E(DRVSTATr),
    .I(BusINT_OBUFE),
    .O(outDATA[2])
  );
  AND2 U3_U2_EncReg_0__n00001 (
    .I0(BUSReset_IBUF),
    .I1(R0data_IBUF),
    .O(U3_U2_EncReg_0__n0000)
  );
  INV U3_U6_PWRflgier__n00023 (
    .I(U3_U6_PWRflgier__n00022),
    .O(U3_U6_PWRflgier__n0002)
  );
  AND2 U3_U5_EncReg_1__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[0]),
    .O(U3_U5_EncReg_1__n0000)
  );
  OR2 U3_U5_EncReg_1__n00013 (
    .I0(U3_U5_EncReg_1__n00011),
    .I1(U3_U5_EncReg_1__n00012),
    .O(U3_U5_EncReg_1__n0001)
  );
  INV U3_U5_PWRenc1 (
    .I(U3_U5_EncPWR),
    .O(R3enable_OBUF)
  );
  AND2 U3_U5_Mmux__n0001_I0_Result2 (
    .I0(U3_U5_EncReg[7]),
    .I1(U3_U5_Mmux__n0001_I0_Result),
    .O(U3_U5__n0001[7])
  );
  BUFE U3_U5_I4_7 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[7]),
    .O(outDATA[7])
  );
  BUFE U3_U5_I3_0 (
    .E(DRVSTATr),
    .I(R3flg_IBUF),
    .O(outDATA[7])
  );
  OBUFE R3clk_OBUFE (
    .E(U3_U5_EncPWR),
    .I(U3_NET266),
    .O(R3clk)
  );
  AND2 U3_U3_EncReg_4__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[3]),
    .O(U3_U3_EncReg_4__n0000)
  );
  INV U3_U5__n00064 (
    .I(U3_U5__n00063),
    .O(U3_U5__n0006)
  );
  FDCE U3_U5_EncPWR_1401 (
    .D(U3_U5_EncPWR__n0000),
    .CE(U3_U6_PWRflgier__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U3_U5_EncPWR)
  );
  AND2 U3_U2_Mmux__n0001_I5_Result2 (
    .I0(U3_U2_EncReg[2]),
    .I1(U3_U2_Mmux__n0001_I5_Result),
    .O(U3_U2__n0001[2])
  );
  BUFE U3_U5_I4_0 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[0]),
    .O(outDATA[0])
  );
  BUFE U3_U5_I4_1 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[1]),
    .O(outDATA[1])
  );
  BUFE U3_U5_I4_2 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[2]),
    .O(outDATA[2])
  );
  BUFE U3_U5_I4_3 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[3]),
    .O(outDATA[3])
  );
  BUFE U3_U5_I4_4 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[4]),
    .O(outDATA[4])
  );
  BUFE U3_U5_I4_5 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[5]),
    .O(outDATA[5])
  );
  BUFE U3_U5_I4_6 (
    .E(U3_U5__n0006),
    .I(U3_U5__n0001[6]),
    .O(outDATA[6])
  );
  FDCE U3_U2_EncReg_5 (
    .D(U3_U2_EncReg_5__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[5])
  );
  AND2 U3_U2_EncReg_1__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[0]),
    .O(U3_U2_EncReg_1__n0000)
  );
  AND2 U3_U5_EncPWR__n00001 (
    .I0(BUSReset_IBUF),
    .I1(N11868),
    .O(U3_U5_EncPWR__n0000)
  );
  OR2 U3_U5_Mmux__n0001_I7_Result4 (
    .I0(U3_U5_Mmux__n0001_I7_Result),
    .I1(U3_U5_Mmux__n0001_I7_Result2),
    .O(U3_U5__n0001[0])
  );
  AND2 U3_U5_Mmux__n0001_I6_Result2 (
    .I0(U3_U5_EncReg[1]),
    .I1(U3_U5_Mmux__n0001_I6_Result),
    .O(U3_U5__n0001[1])
  );
  AND2 U3_U5_Mmux__n0001_I5_Result2 (
    .I0(U3_U5_EncReg[2]),
    .I1(U3_U5_Mmux__n0001_I5_Result),
    .O(U3_U5__n0001[2])
  );
  AND2 U3_U5_Mmux__n0001_I4_Result2 (
    .I0(U3_U5_EncReg[3]),
    .I1(U3_U5_Mmux__n0001_I4_Result),
    .O(U3_U5__n0001[3])
  );
  AND2 U3_U5_Mmux__n0001_I3_Result2 (
    .I0(U3_U5_EncReg[4]),
    .I1(U3_U5_Mmux__n0001_I3_Result),
    .O(U3_U5__n0001[4])
  );
  AND2 U3_U5_Mmux__n0001_I2_Result2 (
    .I0(U3_U5_EncReg[5]),
    .I1(U3_U5_Mmux__n0001_I2_Result),
    .O(U3_U5__n0001[5])
  );
  AND2 U3_U5_Mmux__n0001_I1_Result2 (
    .I0(U3_U5_EncReg[6]),
    .I1(U3_U5_Mmux__n0001_I1_Result),
    .O(U3_U5__n0001[6])
  );
  FDCE U3_U5_EncReg_8 (
    .D(U3_U5_EncReg_8__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[8])
  );
  FDCE U3_U5_EncReg_7 (
    .D(U3_U5_EncReg_7__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[7])
  );
  FDCE U3_U5_EncReg_0 (
    .D(U3_U5_EncReg_0__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[0])
  );
  FDCE U3_U5_EncReg_1 (
    .D(U3_U5_EncReg_1__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[1])
  );
  FDCE U3_U5_EncReg_2 (
    .D(U3_U5_EncReg_2__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[2])
  );
  FDCE U3_U5_EncReg_3 (
    .D(U3_U5_EncReg_3__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[3])
  );
  FDCE U3_U5_EncReg_4 (
    .D(U3_U5_EncReg_4__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[4])
  );
  FDCE U3_U5_EncReg_5 (
    .D(U3_U5_EncReg_5__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[5])
  );
  FDCE U3_U5_EncReg_6 (
    .D(U3_U5_EncReg_6__n0000),
    .CE(U3_U5_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U5_EncReg[6])
  );
  AND2 U3_U2_Mmux__n0001_I6_Result2 (
    .I0(U3_U2_EncReg[1]),
    .I1(U3_U2_Mmux__n0001_I6_Result),
    .O(U3_U2__n0001[1])
  );
  AND2 U3_U5_EncReg_8__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[7]),
    .O(U3_U5_EncReg_8__n0000)
  );
  AND2 U3_U5_EncReg_0__n00001 (
    .I0(BUSReset_IBUF),
    .I1(R3data_IBUF),
    .O(U3_U5_EncReg_0__n0000)
  );
  OR2 U3_U2_Mmux__n0001_I7_Result4 (
    .I0(U3_U2_Mmux__n0001_I7_Result),
    .I1(U3_U2_Mmux__n0001_I7_Result2),
    .O(U3_U2__n0001[0])
  );
  AND2 U3_U5_EncReg_7__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[6]),
    .O(U3_U5_EncReg_7__n0000)
  );
  AND2 U3_U2_EncPWR__n00001 (
    .I0(BUSReset_IBUF),
    .I1(N11878),
    .O(U3_U2_EncPWR__n0000)
  );
  AND2 U3_U5_EncReg_6__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[5]),
    .O(U3_U5_EncReg_6__n0000)
  );
  AND2 U3_U3_EncReg_2__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[1]),
    .O(U3_U3_EncReg_2__n0000)
  );
  AND2 U3_U5_EncReg_5__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[4]),
    .O(U3_U5_EncReg_5__n0000)
  );
  AND2 U3_U2_EncReg_6__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[5]),
    .O(U3_U2_EncReg_6__n0000)
  );
  AND2 U3_U5_EncReg_4__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[3]),
    .O(U3_U5_EncReg_4__n0000)
  );
  BUFE U3_U2_I4_6 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[6]),
    .O(outDATA[6])
  );
  AND2 U3_U5_EncReg_3__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[2]),
    .O(U3_U5_EncReg_3__n0000)
  );
  BUFE U3_U2_I4_5 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[5]),
    .O(outDATA[5])
  );
  AND2 U3_U5_EncReg_2__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U5_EncReg[1]),
    .O(U3_U5_EncReg_2__n0000)
  );
  AND2 U3_U4_EncReg_1__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[0]),
    .O(U3_U4_EncReg_1__n0000)
  );
  OR2 U3_U4_EncReg_1__n00013 (
    .I0(U3_U4_EncReg_1__n00011),
    .I1(U3_U4_EncReg_1__n00012),
    .O(U3_U4_EncReg_1__n0001)
  );
  INV U3_U4_PWRenc1 (
    .I(U3_U4_EncPWR),
    .O(R2enable_OBUF)
  );
  AND2 U3_U4_Mmux__n0001_I0_Result2 (
    .I0(U3_U4_EncReg[7]),
    .I1(U3_U4_Mmux__n0001_I0_Result),
    .O(U3_U4__n0001[7])
  );
  BUFE U3_U4_I4_7 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[7]),
    .O(outDATA[7])
  );
  BUFE U3_U4_I3_0 (
    .E(DRVSTATr),
    .I(R2flg_IBUF),
    .O(outDATA[6])
  );
  OBUFE R2clk_OBUFE (
    .E(U3_U4_EncPWR),
    .I(U3_NET266),
    .O(R2clk)
  );
  AND2 U3_U3_EncReg_5__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[4]),
    .O(U3_U3_EncReg_5__n0000)
  );
  INV U3_U4__n00064 (
    .I(U3_U4__n00063),
    .O(U3_U4__n0006)
  );
  FDCE U3_U4_EncPWR_1402 (
    .D(U3_U4_EncPWR__n0000),
    .CE(U3_U6_PWRflgier__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U3_U4_EncPWR)
  );
  BUFE U3_U2_I4_4 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[4]),
    .O(outDATA[4])
  );
  BUFE U3_U4_I4_0 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[0]),
    .O(outDATA[0])
  );
  BUFE U3_U4_I4_1 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[1]),
    .O(outDATA[1])
  );
  BUFE U3_U4_I4_2 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[2]),
    .O(outDATA[2])
  );
  BUFE U3_U4_I4_3 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[3]),
    .O(outDATA[3])
  );
  BUFE U3_U4_I4_4 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[4]),
    .O(outDATA[4])
  );
  BUFE U3_U4_I4_5 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[5]),
    .O(outDATA[5])
  );
  BUFE U3_U4_I4_6 (
    .E(U3_U4__n0006),
    .I(U3_U4__n0001[6]),
    .O(outDATA[6])
  );
  AND2 U3_U2_EncReg_7__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U2_EncReg[6]),
    .O(U3_U2_EncReg_7__n0000)
  );
  AND2 U3_U3_EncReg_3__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[2]),
    .O(U3_U3_EncReg_3__n0000)
  );
  AND2 U3_U4_EncPWR__n00001 (
    .I0(BUSReset_IBUF),
    .I1(N11866),
    .O(U3_U4_EncPWR__n0000)
  );
  OR2 U3_U4_Mmux__n0001_I7_Result4 (
    .I0(U3_U4_Mmux__n0001_I7_Result),
    .I1(U3_U4_Mmux__n0001_I7_Result2),
    .O(U3_U4__n0001[0])
  );
  AND2 U3_U4_Mmux__n0001_I6_Result2 (
    .I0(U3_U4_EncReg[1]),
    .I1(U3_U4_Mmux__n0001_I6_Result),
    .O(U3_U4__n0001[1])
  );
  AND2 U3_U4_Mmux__n0001_I5_Result2 (
    .I0(U3_U4_EncReg[2]),
    .I1(U3_U4_Mmux__n0001_I5_Result),
    .O(U3_U4__n0001[2])
  );
  AND2 U3_U4_Mmux__n0001_I4_Result2 (
    .I0(U3_U4_EncReg[3]),
    .I1(U3_U4_Mmux__n0001_I4_Result),
    .O(U3_U4__n0001[3])
  );
  AND2 U3_U4_Mmux__n0001_I3_Result2 (
    .I0(U3_U4_EncReg[4]),
    .I1(U3_U4_Mmux__n0001_I3_Result),
    .O(U3_U4__n0001[4])
  );
  AND2 U3_U4_Mmux__n0001_I2_Result2 (
    .I0(U3_U4_EncReg[5]),
    .I1(U3_U4_Mmux__n0001_I2_Result),
    .O(U3_U4__n0001[5])
  );
  AND2 U3_U4_Mmux__n0001_I1_Result2 (
    .I0(U3_U4_EncReg[6]),
    .I1(U3_U4_Mmux__n0001_I1_Result),
    .O(U3_U4__n0001[6])
  );
  FDCE U3_U4_EncReg_8 (
    .D(U3_U4_EncReg_8__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[8])
  );
  FDCE U3_U4_EncReg_7 (
    .D(U3_U4_EncReg_7__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[7])
  );
  FDCE U3_U4_EncReg_0 (
    .D(U3_U4_EncReg_0__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[0])
  );
  FDCE U3_U4_EncReg_1 (
    .D(U3_U4_EncReg_1__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[1])
  );
  FDCE U3_U4_EncReg_2 (
    .D(U3_U4_EncReg_2__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[2])
  );
  FDCE U3_U4_EncReg_3 (
    .D(U3_U4_EncReg_3__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[3])
  );
  FDCE U3_U4_EncReg_4 (
    .D(U3_U4_EncReg_4__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[4])
  );
  FDCE U3_U4_EncReg_5 (
    .D(U3_U4_EncReg_5__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[5])
  );
  FDCE U3_U4_EncReg_6 (
    .D(U3_U4_EncReg_6__n0000),
    .CE(U3_U4_EncReg_1__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U4_EncReg[6])
  );
  BUFE U3_U2_I4_3 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[3]),
    .O(outDATA[3])
  );
  AND2 U3_U4_EncReg_8__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[7]),
    .O(U3_U4_EncReg_8__n0000)
  );
  AND2 U3_U4_EncReg_0__n00001 (
    .I0(BUSReset_IBUF),
    .I1(R2data_IBUF),
    .O(U3_U4_EncReg_0__n0000)
  );
  BUFE U3_U2_I4_2 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[2]),
    .O(outDATA[2])
  );
  AND2 U3_U4_EncReg_7__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[6]),
    .O(U3_U4_EncReg_7__n0000)
  );
  BUFE U3_U2_I4_1 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[1]),
    .O(outDATA[1])
  );
  AND2 U3_U4_EncReg_6__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[5]),
    .O(U3_U4_EncReg_6__n0000)
  );
  BUFE U3_U2_I4_0 (
    .E(U3_U2__n0006),
    .I(U3_U2__n0001[0]),
    .O(outDATA[0])
  );
  AND2 U3_U4_EncReg_5__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[4]),
    .O(U3_U4_EncReg_5__n0000)
  );
  FDCE U3_U2_EncReg_6 (
    .D(U3_U2_EncReg_6__n0000),
    .CE(U3_U2_EncReg_2__n0001),
    .CLR(BusINT_OBUFE),
    .C(Mclk_IBUF),
    .Q(U3_U2_EncReg[6])
  );
  AND2 U3_U4_EncReg_4__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[3]),
    .O(U3_U4_EncReg_4__n0000)
  );
  FDCE U3_U2_EncPWR_1403 (
    .D(U3_U2_EncPWR__n0000),
    .CE(U3_U6_PWRflgier__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U3_U2_EncPWR)
  );
  AND2 U3_U4_EncReg_3__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[2]),
    .O(U3_U4_EncReg_3__n0000)
  );
  INV U3_U2__n00064 (
    .I(U3_U2__n00063),
    .O(U3_U2__n0006)
  );
  AND2 U3_U4_EncReg_2__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U4_EncReg[1]),
    .O(U3_U4_EncReg_2__n0000)
  );
  AND2 U3_U3_EncReg_1__n00001 (
    .I0(BUSReset_IBUF),
    .I1(U3_U3_EncReg[0]),
    .O(U3_U3_EncReg_1__n0000)
  );
  OR2 U3_U3_EncReg_1__n00013 (
    .I0(U3_U3_EncReg_1__n00011),
    .I1(U3_U3_EncReg_1__n00012),
    .O(U3_U3_EncReg_1__n0001)
  );
  INV U3_U3_PWRenc1 (
    .I(U3_U3_EncPWR),
    .O(R1enable_OBUF)
  );
  AND2 U3_U3_Mmux__n0001_I0_Result2 (
    .I0(U3_U3_EncReg[7]),
    .I1(U3_U3_Mmux__n0001_I0_Result),
    .O(U3_U3__n0001[7])
  );
  BUFE U3_U3_I4_7 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[7]),
    .O(outDATA[7])
  );
  BUFE U3_U3_I3_0 (
    .E(DRVSTATr),
    .I(R1flg_IBUF),
    .O(outDATA[5])
  );
  OBUFE R1clk_OBUFE (
    .E(U3_U3_EncPWR),
    .I(U3_NET266),
    .O(R1clk)
  );
  AND2 U3_U2_Mmux__n0001_I0_Result2 (
    .I0(U3_U2_EncReg[7]),
    .I1(U3_U2_Mmux__n0001_I0_Result),
    .O(U3_U2__n0001[7])
  );
  INV U3_U3__n00064 (
    .I(U3_U3__n00063),
    .O(U3_U3__n0006)
  );
  FDCE U3_U3_EncPWR_1404 (
    .D(U3_U3_EncPWR__n0000),
    .CE(U3_U6_PWRflgier__n0002),
    .CLR(BusINT_OBUFE),
    .C(U1_ADDR_reg_0__n0003),
    .Q(U3_U3_EncPWR)
  );
  INV U3_U2_PWRenc1 (
    .I(U3_U2_EncPWR),
    .O(R0enable_OBUF)
  );
  BUFE U3_U3_I4_0 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[0]),
    .O(outDATA[0])
  );
  BUFE U3_U3_I4_1 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[1]),
    .O(outDATA[1])
  );
  BUFE U3_U3_I4_2 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[2]),
    .O(outDATA[2])
  );
  BUFE U3_U3_I4_3 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[3]),
    .O(outDATA[3])
  );
  BUFE U3_U3_I4_4 (
    .E(U3_U3__n0006),
    .I(U3_U3__n0001[4]),
    .O(outDATA[4])
  );
  AND2 U1_ADDR_reg_2__n00001_1405 (
    .I0(U1__n0005),
    .I1(N11874),
    .O(U1_ADDR_reg_2__n00001)
  );
  AND2 U1_ADDR_reg_2__n00002_1406 (
    .I0(U1__n0013[2]),
    .I1(U1__n0006),
    .O(U1_ADDR_reg_2__n00002)
  );
  INV U1_ADDR_reg_2__n00003_1407 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_2__n00003)
  );
  AND2 U1_ADDR_reg_2__n00004_1408 (
    .I0(U1_ADDR_reg_2__n00002),
    .I1(U1_ADDR_reg_2__n00003),
    .O(U1_ADDR_reg_2__n00004)
  );
  OR2 U1_ADDR_reg_2__n00005_1409 (
    .I0(U1_ADDR_reg_2__n00001),
    .I1(U1_ADDR_reg_2__n00004),
    .O(U1_ADDR_reg_2__n00005)
  );
  AND2 U1_ADDR_reg_3__n00001_1410 (
    .I0(U1__n0005),
    .I1(N11876),
    .O(U1_ADDR_reg_3__n00001)
  );
  AND2 U1_ADDR_reg_3__n00002_1411 (
    .I0(U1__n0013[3]),
    .I1(U1__n0006),
    .O(U1_ADDR_reg_3__n00002)
  );
  INV U1_ADDR_reg_3__n00003_1412 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_3__n00003)
  );
  AND2 U1_ADDR_reg_3__n00004_1413 (
    .I0(U1_ADDR_reg_3__n00002),
    .I1(U1_ADDR_reg_3__n00003),
    .O(U1_ADDR_reg_3__n00004)
  );
  OR2 U1_ADDR_reg_3__n00005_1414 (
    .I0(U1_ADDR_reg_3__n00001),
    .I1(U1_ADDR_reg_3__n00004),
    .O(U1_ADDR_reg_3__n00005)
  );
  AND2 U1_ADDR_reg_4__n00001_1415 (
    .I0(U1__n0005),
    .I1(N11878),
    .O(U1_ADDR_reg_4__n00001)
  );
  AND2 U1_ADDR_reg_4__n00002_1416 (
    .I0(U1__n0013[4]),
    .I1(U1__n0006),
    .O(U1_ADDR_reg_4__n00002)
  );
  INV U1_ADDR_reg_4__n00003_1417 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_4__n00003)
  );
  AND2 U1_ADDR_reg_4__n00004_1418 (
    .I0(U1_ADDR_reg_4__n00002),
    .I1(U1_ADDR_reg_4__n00003),
    .O(U1_ADDR_reg_4__n00004)
  );
  OR2 U1_ADDR_reg_4__n00005_1419 (
    .I0(U1_ADDR_reg_4__n00001),
    .I1(U1_ADDR_reg_4__n00004),
    .O(U1_ADDR_reg_4__n00005)
  );
  AND2 U1_ADDR_reg_5__n00001_1420 (
    .I0(U1__n0005),
    .I1(N11864),
    .O(U1_ADDR_reg_5__n00001)
  );
  AND2 U1_ADDR_reg_5__n00002_1421 (
    .I0(U1__n0013[5]),
    .I1(U1__n0006),
    .O(U1_ADDR_reg_5__n00002)
  );
  INV U1_ADDR_reg_5__n00003_1422 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_5__n00003)
  );
  AND2 U1_ADDR_reg_5__n00004_1423 (
    .I0(U1_ADDR_reg_5__n00002),
    .I1(U1_ADDR_reg_5__n00003),
    .O(U1_ADDR_reg_5__n00004)
  );
  OR2 U1_ADDR_reg_5__n00005_1424 (
    .I0(U1_ADDR_reg_5__n00001),
    .I1(U1_ADDR_reg_5__n00004),
    .O(U1_ADDR_reg_5__n00005)
  );
  AND2 U1_ADDR_reg_6__n00001_1425 (
    .I0(U1__n0005),
    .I1(N11866),
    .O(U1_ADDR_reg_6__n00001)
  );
  AND2 U1_ADDR_reg_6__n00002_1426 (
    .I0(U1__n0013[6]),
    .I1(U1__n0006),
    .O(U1_ADDR_reg_6__n00002)
  );
  INV U1_ADDR_reg_6__n00003_1427 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_6__n00003)
  );
  AND2 U1_ADDR_reg_6__n00004_1428 (
    .I0(U1_ADDR_reg_6__n00002),
    .I1(U1_ADDR_reg_6__n00003),
    .O(U1_ADDR_reg_6__n00004)
  );
  OR2 U1_ADDR_reg_6__n00005_1429 (
    .I0(U1_ADDR_reg_6__n00001),
    .I1(U1_ADDR_reg_6__n00004),
    .O(U1_ADDR_reg_6__n00005)
  );
  AND2 U1_ADDR_reg_7__n00001_1430 (
    .I0(U1__n0005),
    .I1(N11868),
    .O(U1_ADDR_reg_7__n00001)
  );
  AND2 U1_ADDR_reg_7__n00002_1431 (
    .I0(U1__n0013[7]),
    .I1(U1__n0006),
    .O(U1_ADDR_reg_7__n00002)
  );
  INV U1_ADDR_reg_7__n00003_1432 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_7__n00003)
  );
  AND2 U1_ADDR_reg_7__n00004_1433 (
    .I0(U1_ADDR_reg_7__n00002),
    .I1(U1_ADDR_reg_7__n00003),
    .O(U1_ADDR_reg_7__n00004)
  );
  OR2 U1_ADDR_reg_7__n00005_1434 (
    .I0(U1_ADDR_reg_7__n00001),
    .I1(U1_ADDR_reg_7__n00004),
    .O(U1_ADDR_reg_7__n00005)
  );
  AND2 U1_ADDR_reg_0__n00021_1435 (
    .I0(RD_IBUF),
    .I1(WR_IBUF),
    .O(U1_ADDR_reg_0__n00021)
  );
  INV U1_ADDR_reg_0__n00022_1436 (
    .I(AS_IBUF),
    .O(U1_ADDR_reg_0__n00022)
  );
  AND2 U1_ADDR_reg_0__n00023_1437 (
    .I0(U1_AutoInc),
    .I1(U1_ADDR_in_Range),
    .O(U1_ADDR_reg_0__n00023)
  );
  INV U1_ADDR_reg_0__n00024_1438 (
    .I(U1_WRRDedge),
    .O(U1_ADDR_reg_0__n00024)
  );
  INV U1_ADDR_reg_0__n00025_1439 (
    .I(BUSReset_IBUF),
    .O(U1_ADDR_reg_0__n00025)
  );
  AND2 U1_ADDR_reg_0__n00026_1440 (
    .I0(U1_ASedge),
    .I1(U1_ADDR_reg_0__n00022),
    .O(U1_ADDR_reg_0__n00026)
  );
  AND2 U1_ADDR_reg_0__n00027_1441 (
    .I0(U1_ADDR_reg_0__n00023),
    .I1(U1_ADDR_reg_0__n00024),
    .O(U1_ADDR_reg_0__n00027)
  );
  OR2 U1_ADDR_reg_0__n00028_1442 (
    .I0(U1_ADDR_reg_0__n00026),
    .I1(U1_ADDR_reg_0__n00027),
    .O(U1_ADDR_reg_0__n00028)
  );
  AND2 U1_ADDR_reg_0__n00029_1443 (
    .I0(U1_ADDR_reg_0__n00021),
    .I1(U1_ADDR_reg_0__n00028),
    .O(U1_ADDR_reg_0__n00029)
  );
  AND2 U1_ADDR_reg_0__n00001_1444 (
    .I0(U1__n0005),
    .I1(N11870),
    .O(U1_ADDR_reg_0__n00001)
  );
  INV U1_ADDR_reg_0__n00002_1445 (
    .I(U1_ADDR_reg[0]),
    .O(U1_ADDR_reg_0__n00002)
  );
  INV U1_ADDR_reg_0__n00003_1446 (
    .I(U1_ADDR_reg[0]),
    .O(U1_ADDR_reg_0__n00003)
  );
  INV U1_ADDR_reg_0__n00004_1447 (
    .I(U1_ADDR_reg[1]),
    .O(U1_ADDR_reg_0__n00004)
  );
  INV U1_ADDR_reg_0__n00005_1448 (
    .I(U1_ADDR_reg[2]),
    .O(U1_ADDR_reg_0__n00005)
  );
  INV U1_ADDR_reg_0__n00006_1449 (
    .I(U1_ADDR_reg[3]),
    .O(U1_ADDR_reg_0__n00006)
  );
  INV U1_ADDR_reg_0__n00007_1450 (
    .I(U1__n0006),
    .O(U1_ADDR_reg_0__n00007)
  );
  INV U1_ADDR_reg_0__n00008_1451 (
    .I(U1_ADDR_reg[4]),
    .O(U1_ADDR_reg_0__n00008)
  );
  INV U1_ADDR_reg_0__n00009_1452 (
    .I(U1_ADDR_reg[5]),
    .O(U1_ADDR_reg_0__n00009)
  );
  INV U1_ADDR_reg_0__n000010_1453 (
    .I(U1_ADDR_reg[6]),
    .O(U1_ADDR_reg_0__n000010)
  );
  INV U1_ADDR_reg_0__n000011_1454 (
    .I(U1_ADDR_reg[7]),
    .O(U1_ADDR_reg_0__n000011)
  );
  INV U1_ADDR_reg_0__n000012_1455 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_0__n000012)
  );
  AND2 U1_ADDR_reg_0__n000013_1456 (
    .I0(U1__n0006),
    .I1(U1_ADDR_reg_0__n00002),
    .O(U1_ADDR_reg_0__n000013)
  );
  AND4 U1_ADDR_reg_0__n000014_1457 (
    .I0(U1_ADDR_reg_0__n00003),
    .I1(U1_ADDR_reg_0__n00004),
    .I2(U1_ADDR_reg_0__n00005),
    .I3(U1_ADDR_reg_0__n00006),
    .O(U1_ADDR_reg_0__n000014)
  );
  AND2 U1_ADDR_reg_0__n000015_1458 (
    .I0(U1_ADDR_reg_0__n00007),
    .I1(U1_ADDR_reg_0__n00008),
    .O(U1_ADDR_reg_0__n000015)
  );
  AND2 U1_ADDR_reg_0__n000016_1459 (
    .I0(U1_ADDR_reg_0__n000010),
    .I1(U1_ADDR_reg_0__n000011),
    .O(U1_ADDR_reg_0__n000016)
  );
  OR2 U1_ADDR_reg_0__n000017_1460 (
    .I0(U1_ADDR_reg_0__n000014),
    .I1(U1_ADDR_reg_0__n000015),
    .O(U1_ADDR_reg_0__n000017)
  );
  AND3 U1_ADDR_reg_0__n000018_1461 (
    .I0(U1_ADDR_reg_0__n00009),
    .I1(U1_ADDR_reg_0__n000017),
    .I2(U1_ADDR_reg_0__n000016),
    .O(U1_ADDR_reg_0__n000018)
  );
  OR2 U1_ADDR_reg_0__n000019_1462 (
    .I0(U1_ADDR_reg_0__n000013),
    .I1(U1_ADDR_reg_0__n000018),
    .O(U1_ADDR_reg_0__n000019)
  );
  AND2 U1_ADDR_reg_0__n000020_1463 (
    .I0(U1_ADDR_reg_0__n000019),
    .I1(U1_ADDR_reg_0__n000012),
    .O(U1_ADDR_reg_0__n000020)
  );
  OR2 U1_ADDR_reg_0__n000021_1464 (
    .I0(U1_ADDR_reg_0__n00001),
    .I1(U1_ADDR_reg_0__n000020),
    .O(U1_ADDR_reg_0__n000021)
  );
  INV U3_U3_Mmux__n0001_I2_Result1 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I2_Result)
  );
  INV U1__n00031_1465 (
    .I(U1__n0000),
    .O(U1__n00031)
  );
  INV U3_U3_Mmux__n0001_I3_Result1 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I3_Result)
  );
  AND2 U1_ADDR_reg_1__n00001_1466 (
    .I0(U1__n0005),
    .I1(N11872),
    .O(U1_ADDR_reg_1__n00001)
  );
  AND2 U1_ADDR_reg_1__n00002_1467 (
    .I0(U1__n0013[1]),
    .I1(U1__n0006),
    .O(U1_ADDR_reg_1__n00002)
  );
  INV U1_ADDR_reg_1__n00003_1468 (
    .I(U1__n0005),
    .O(U1_ADDR_reg_1__n00003)
  );
  AND2 U1_ADDR_reg_1__n00004_1469 (
    .I0(U1_ADDR_reg_1__n00002),
    .I1(U1_ADDR_reg_1__n00003),
    .O(U1_ADDR_reg_1__n00004)
  );
  OR2 U1_ADDR_reg_1__n00005_1470 (
    .I0(U1_ADDR_reg_1__n00001),
    .I1(U1_ADDR_reg_1__n00004),
    .O(U1_ADDR_reg_1__n00005)
  );
  INV U1_ADDR_in_Range1_1471 (
    .I(U1_ADDR_reg[5]),
    .O(U1_ADDR_in_Range1)
  );
  INV U1_ADDR_in_Range2_1472 (
    .I(U1_ADDR_reg[6]),
    .O(U1_ADDR_in_Range2)
  );
  INV U1_ADDR_in_Range3_1473 (
    .I(U1_ADDR_reg[7]),
    .O(U1_ADDR_in_Range3)
  );
  AND2 U1_ADDR_in_Range4_1474 (
    .I0(U1_ADDR_reg[3]),
    .I1(U1_ADDR_reg[2]),
    .O(U1_ADDR_in_Range4)
  );
  AND4 U1_ADDR_in_Range5_1475 (
    .I0(U1_ADDR_reg[4]),
    .I1(U1_ADDR_in_Range1),
    .I2(U1_ADDR_in_Range2),
    .I3(U1_ADDR_in_Range3),
    .O(U1_ADDR_in_Range5)
  );
  INV U1_ADDR_in_Range6_1476 (
    .I(U1_ADDR_in_Range4),
    .O(U1_ADDR_in_Range6)
  );
  INV U3_U3_Mmux__n0001_I1_Result1 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I1_Result)
  );
  AND2 U1__n00051_1477 (
    .I0(RD_IBUF),
    .I1(WR_IBUF),
    .O(U1__n00051)
  );
  INV U1__n00052_1478 (
    .I(AS_IBUF),
    .O(U1__n00052)
  );
  AND2 U1__n00053_1479 (
    .I0(U1_ASedge),
    .I1(U1__n00052),
    .O(U1__n00053)
  );
  AND2 U1_Enable_AD1_1480 (
    .I0(U1_ADDR_in_Range),
    .I1(WR_IBUF),
    .O(U1_Enable_AD1)
  );
  INV U1_Enable_AD2_1481 (
    .I(RD_IBUF),
    .O(U1_Enable_AD2)
  );
  INV U1__n00061_1482 (
    .I(U1_ADDR_reg[2]),
    .O(U1__n00061)
  );
  AND2 U1__n00062_1483 (
    .I0(U1_ADDR_reg[1]),
    .I1(U1_ADDR_reg[0]),
    .O(U1__n00062)
  );
  INV U1__n00063_1484 (
    .I(U1_ADDR_reg[3]),
    .O(U1__n00063)
  );
  INV U1__n00064_1485 (
    .I(U1_ADDR_reg[5]),
    .O(U1__n00064)
  );
  INV U1__n00065_1486 (
    .I(U1_ADDR_reg[6]),
    .O(U1__n00065)
  );
  INV U1__n00066_1487 (
    .I(U1_ADDR_reg[7]),
    .O(U1__n00066)
  );
  INV U1__n00067_1488 (
    .I(U1__n00062),
    .O(U1__n00067)
  );
  AND2 U1__n00068_1489 (
    .I0(U1__n00064),
    .I1(U1__n00065),
    .O(U1__n00068)
  );
  AND2 U1__n00069_1490 (
    .I0(U1__n00061),
    .I1(U1__n00067),
    .O(U1__n00069)
  );
  OR2 U1__n000610_1491 (
    .I0(U1__n00069),
    .I1(U1__n00063),
    .O(U1__n000610)
  );
  AND3 U1__n000611_1492 (
    .I0(U1__n000610),
    .I1(U1_ADDR_reg[4]),
    .I2(U1__n00068),
    .O(U1__n000611)
  );
  INV U3_U3_Mmux__n0001_I4_Result1 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I4_Result)
  );
  INV U3_U3_Mmux__n0001_I5_Result1 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I5_Result)
  );
  INV U3_U2_Mmux__n0001_I1_Result1 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I1_Result)
  );
  INV U3_U3_Mmux__n0001_I6_Result1 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I6_Result)
  );
  INV U3_U2_Mmux__n0001_I2_Result1 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I2_Result)
  );
  INV U3_U2_Mmux__n0001_I3_Result1 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I3_Result)
  );
  AND2 U3_U2_EncReg_2__n00011_1493 (
    .I0(U3_U2_EncPWR),
    .I1(U3_NET282),
    .O(U3_U2_EncReg_2__n00011)
  );
  INV U3_U2_EncReg_2__n00012_1494 (
    .I(BUSReset_IBUF),
    .O(U3_U2_EncReg_2__n00012)
  );
  INV U3_U2_Mmux__n0001_I4_Result1 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I4_Result)
  );
  AND2 U3_U3_Mmux__n0001_I7_Result1_1495 (
    .I0(DRV1HIGHr),
    .I1(U3_U3_EncReg[8]),
    .O(U3_U3_Mmux__n0001_I7_Result)
  );
  INV U3_U3_Mmux__n0001_I7_Result2_1496 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I7_Result1)
  );
  AND2 U3_U3_Mmux__n0001_I7_Result3 (
    .I0(U3_U3_EncReg[0]),
    .I1(U3_U3_Mmux__n0001_I7_Result1),
    .O(U3_U3_Mmux__n0001_I7_Result2)
  );
  AND4 U3_U6_intENCint1_1497 (
    .I0(outDATA[7]),
    .I1(outDATA[6]),
    .I2(outDATA[4]),
    .I3(outDATA[5]),
    .O(U3_U6_intENCint1)
  );
  INV U3_U6_intENCint2_1498 (
    .I(U3_U6_intENCint1),
    .O(U3_U6_intENCint2)
  );
  INV U3_U6_PWRflgier__n00021_1499 (
    .I(DRVCTLw),
    .O(U3_U6_PWRflgier__n00021)
  );
  AND2 U3_U6_PWRflgier__n00022_1500 (
    .I0(BUSReset_IBUF),
    .I1(U3_U6_PWRflgier__n00021),
    .O(U3_U6_PWRflgier__n00022)
  );
  AND2 U3_U5_EncReg_1__n00011_1501 (
    .I0(U3_U5_EncPWR),
    .I1(U3_NET282),
    .O(U3_U5_EncReg_1__n00011)
  );
  INV U3_U5_EncReg_1__n00012_1502 (
    .I(BUSReset_IBUF),
    .O(U3_U5_EncReg_1__n00012)
  );
  INV U3_U5_Mmux__n0001_I0_Result1 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I0_Result)
  );
  INV U3_U5__n00061_1503 (
    .I(DRV3HIGHr),
    .O(U3_U5__n00061)
  );
  INV U3_U5__n00062_1504 (
    .I(DRV3LOWr),
    .O(U3_U5__n00062)
  );
  AND2 U3_U5__n00063_1505 (
    .I0(U3_U5__n00061),
    .I1(U3_U5__n00062),
    .O(U3_U5__n00063)
  );
  INV U3_U2_Mmux__n0001_I5_Result1 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I5_Result)
  );
  AND2 U3_U5_Mmux__n0001_I7_Result1_1506 (
    .I0(DRV3HIGHr),
    .I1(U3_U5_EncReg[8]),
    .O(U3_U5_Mmux__n0001_I7_Result)
  );
  INV U3_U5_Mmux__n0001_I7_Result2_1507 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I7_Result1)
  );
  AND2 U3_U5_Mmux__n0001_I7_Result3 (
    .I0(U3_U5_EncReg[0]),
    .I1(U3_U5_Mmux__n0001_I7_Result1),
    .O(U3_U5_Mmux__n0001_I7_Result2)
  );
  INV U3_U5_Mmux__n0001_I6_Result1 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I6_Result)
  );
  INV U3_U5_Mmux__n0001_I5_Result1 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I5_Result)
  );
  INV U3_U5_Mmux__n0001_I4_Result1 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I4_Result)
  );
  INV U3_U5_Mmux__n0001_I3_Result1 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I3_Result)
  );
  INV U3_U5_Mmux__n0001_I2_Result1 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I2_Result)
  );
  INV U3_U5_Mmux__n0001_I1_Result1 (
    .I(DRV3HIGHr),
    .O(U3_U5_Mmux__n0001_I1_Result)
  );
  INV U3_U2_Mmux__n0001_I6_Result1 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I6_Result)
  );
  AND2 U3_U2_Mmux__n0001_I7_Result1_1508 (
    .I0(DRV0HIGHr),
    .I1(U3_U2_EncReg[8]),
    .O(U3_U2_Mmux__n0001_I7_Result)
  );
  INV U3_U2_Mmux__n0001_I7_Result2_1509 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I7_Result1)
  );
  AND2 U3_U2_Mmux__n0001_I7_Result3 (
    .I0(U3_U2_EncReg[0]),
    .I1(U3_U2_Mmux__n0001_I7_Result1),
    .O(U3_U2_Mmux__n0001_I7_Result2)
  );
  AND2 U3_U4_EncReg_1__n00011_1510 (
    .I0(U3_U4_EncPWR),
    .I1(U3_NET282),
    .O(U3_U4_EncReg_1__n00011)
  );
  INV U3_U4_EncReg_1__n00012_1511 (
    .I(BUSReset_IBUF),
    .O(U3_U4_EncReg_1__n00012)
  );
  INV U3_U4_Mmux__n0001_I0_Result1 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I0_Result)
  );
  INV U3_U4__n00061_1512 (
    .I(DRV2HIGHr),
    .O(U3_U4__n00061)
  );
  INV U3_U4__n00062_1513 (
    .I(DRV2LOWr),
    .O(U3_U4__n00062)
  );
  AND2 U3_U4__n00063_1514 (
    .I0(U3_U4__n00061),
    .I1(U3_U4__n00062),
    .O(U3_U4__n00063)
  );
  AND2 U3_U4_Mmux__n0001_I7_Result1_1515 (
    .I0(DRV2HIGHr),
    .I1(U3_U4_EncReg[8]),
    .O(U3_U4_Mmux__n0001_I7_Result)
  );
  INV U3_U4_Mmux__n0001_I7_Result2_1516 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I7_Result1)
  );
  AND2 U3_U4_Mmux__n0001_I7_Result3 (
    .I0(U3_U4_EncReg[0]),
    .I1(U3_U4_Mmux__n0001_I7_Result1),
    .O(U3_U4_Mmux__n0001_I7_Result2)
  );
  INV U3_U4_Mmux__n0001_I6_Result1 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I6_Result)
  );
  INV U3_U4_Mmux__n0001_I5_Result1 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I5_Result)
  );
  INV U3_U4_Mmux__n0001_I4_Result1 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I4_Result)
  );
  INV U3_U4_Mmux__n0001_I3_Result1 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I3_Result)
  );
  INV U3_U4_Mmux__n0001_I2_Result1 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I2_Result)
  );
  INV U3_U4_Mmux__n0001_I1_Result1 (
    .I(DRV2HIGHr),
    .O(U3_U4_Mmux__n0001_I1_Result)
  );
  INV U3_U2__n00061_1517 (
    .I(DRV0HIGHr),
    .O(U3_U2__n00061)
  );
  INV U3_U2__n00062_1518 (
    .I(DRV0LOWr),
    .O(U3_U2__n00062)
  );
  AND2 U3_U2__n00063_1519 (
    .I0(U3_U2__n00061),
    .I1(U3_U2__n00062),
    .O(U3_U2__n00063)
  );
  AND2 U3_U3_EncReg_1__n00011_1520 (
    .I0(U3_U3_EncPWR),
    .I1(U3_NET282),
    .O(U3_U3_EncReg_1__n00011)
  );
  INV U3_U3_EncReg_1__n00012_1521 (
    .I(BUSReset_IBUF),
    .O(U3_U3_EncReg_1__n00012)
  );
  INV U3_U3_Mmux__n0001_I0_Result1 (
    .I(DRV1HIGHr),
    .O(U3_U3_Mmux__n0001_I0_Result)
  );
  INV U3_U2_Mmux__n0001_I0_Result1 (
    .I(DRV0HIGHr),
    .O(U3_U2_Mmux__n0001_I0_Result)
  );
  INV U3_U3__n00061_1522 (
    .I(DRV1HIGHr),
    .O(U3_U3__n00061)
  );
  INV U3_U3__n00062_1523 (
    .I(DRV1LOWr),
    .O(U3_U3__n00062)
  );
  AND2 U3_U3__n00063_1524 (
    .I0(U3_U3__n00061),
    .I1(U3_U3__n00062),
    .O(U3_U3__n00063)
  );
  IBUF Mclk_IBUF_1525 (
    .I(Mclk),
    .O(Mclk_IBUF)
  );
  IBUF R0flg_IBUF_1526 (
    .I(R0flg),
    .O(R0flg_IBUF)
  );
  IBUF AS_IBUF_1527 (
    .I(AS),
    .O(AS_IBUF)
  );
  IBUF R0data_IBUF_1528 (
    .I(R0data),
    .O(R0data_IBUF)
  );
  IBUF R2flg_IBUF_1529 (
    .I(R2flg),
    .O(R2flg_IBUF)
  );
  IBUF R1data_IBUF_1530 (
    .I(R1data),
    .O(R1data_IBUF)
  );
  IBUF RD_IBUF_1531 (
    .I(RD),
    .O(RD_IBUF)
  );
  IBUF GPIO8_IBUF_1532 (
    .I(GPIO8),
    .O(GPIO8_IBUF)
  );
  IBUF GPIO9_IBUF (
    .I(GPIO9),
    .O(Heater_Control_OBUF)
  );
  IBUF R2data_IBUF_1533 (
    .I(R2data),
    .O(R2data_IBUF)
  );
  IBUF WR_IBUF_1534 (
    .I(WR),
    .O(WR_IBUF)
  );
  IBUF R1flg_IBUF_1535 (
    .I(R1flg),
    .O(R1flg_IBUF)
  );
  IBUF R3data_IBUF_1536 (
    .I(R3data),
    .O(R3data_IBUF)
  );
  IBUF BUSReset_IBUF_1537 (
    .I(BUSReset),
    .O(BUSReset_IBUF)
  );
  IBUF R3flg_IBUF_1538 (
    .I(R3flg),
    .O(R3flg_IBUF)
  );
  OBUF Motor4_Phase_B_LIN_OBUF_1539 (
    .I(Motor4_Phase_B_LIN_OBUF),
    .O(Motor4_Phase_B_LIN)
  );
  OBUF Motor1_Phase_B_LIN_OBUF_1540 (
    .I(Motor1_Phase_B_LIN_OBUF),
    .O(Motor1_Phase_B_LIN)
  );
  OBUF PhaseB_Low_1_OBUF_1541 (
    .I(PhaseB_Low_1_OBUF),
    .O(PhaseB_Low_1)
  );
  OBUF PhaseB_Low_2_OBUF_1542 (
    .I(PhaseB_Low_2_OBUF),
    .O(PhaseB_Low_2)
  );
  OBUF PhaseB_Low_3_OBUF_1543 (
    .I(PhaseB_Low_3_OBUF),
    .O(PhaseB_Low_3)
  );
  OBUF PhaseB_Low_4_OBUF_1544 (
    .I(PhaseB_Low_4_OBUF),
    .O(PhaseB_Low_4)
  );
  OBUF PhaseB_Low_5_OBUF_1545 (
    .I(PhaseB_Low_5_OBUF),
    .O(PhaseB_Low_5)
  );
  OBUF PhaseB_Low_6_OBUF_1546 (
    .I(PhaseB_Low_6_OBUF),
    .O(PhaseB_Low_6)
  );
  OBUF PhaseB_Low_7_OBUF_1547 (
    .I(PhaseB_Low_7_OBUF),
    .O(PhaseB_Low_7)
  );
  OBUF PhaseB_Low_8_OBUF_1548 (
    .I(PhaseB_Low_8_OBUF),
    .O(PhaseB_Low_8)
  );
  OBUF PhaseA_Low_1_OBUF_1549 (
    .I(PhaseA_Low_1_OBUF),
    .O(PhaseA_Low_1)
  );
  OBUF PhaseA_Low_2_OBUF_1550 (
    .I(PhaseA_Low_2_OBUF),
    .O(PhaseA_Low_2)
  );
  OBUF PhaseA_Low_3_OBUF_1551 (
    .I(PhaseA_Low_3_OBUF),
    .O(PhaseA_Low_3)
  );
  OBUF PhaseA_Low_4_OBUF_1552 (
    .I(PhaseA_Low_4_OBUF),
    .O(PhaseA_Low_4)
  );
  OBUF Motor_Power_n_OBUF_1553 (
    .I(Motor_Power_n_OBUF),
    .O(Motor_Power_n)
  );
  OBUF PhaseA_Low_5_OBUF_1554 (
    .I(PhaseA_Low_5_OBUF),
    .O(PhaseA_Low_5)
  );
  OBUF Motor2_Phase_A_LIN_OBUF_1555 (
    .I(Motor2_Phase_A_LIN_OBUF),
    .O(Motor2_Phase_A_LIN)
  );
  OBUF PhaseA_Low_6_OBUF_1556 (
    .I(PhaseA_Low_6_OBUF),
    .O(PhaseA_Low_6)
  );
  OBUF PhaseA_Low_7_OBUF_1557 (
    .I(PhaseA_Low_7_OBUF),
    .O(PhaseA_Low_7)
  );
  OBUF PhaseA_Low_8_OBUF_1558 (
    .I(PhaseA_Low_8_OBUF),
    .O(PhaseA_Low_8)
  );
  OBUF Motor3_Phase_B_HIN_OBUF_1559 (
    .I(Motor3_Phase_B_HIN_OBUF),
    .O(Motor3_Phase_B_HIN)
  );
  OBUF Current_enable_OBUF_1560 (
    .I(Current_enable_OBUF),
    .O(Current_enable)
  );
  OBUF Motor4_Phase_A_HIN_OBUF_1561 (
    .I(Motor4_Phase_A_HIN_OBUF),
    .O(Motor4_Phase_A_HIN)
  );
  OBUF Motor1_Phase_A_HIN_OBUF_1562 (
    .I(Motor1_Phase_A_HIN_OBUF),
    .O(Motor1_Phase_A_HIN)
  );
  OBUF Motor2_Phase_B_LIN_OBUF_1563 (
    .I(Motor2_Phase_B_LIN_OBUF),
    .O(Motor2_Phase_B_LIN)
  );
  OBUF PhaseB_High_1_OBUF_1564 (
    .I(PhaseB_High_1_OBUF),
    .O(PhaseB_High_1)
  );
  OBUF PhaseB_High_2_OBUF_1565 (
    .I(PhaseB_High_2_OBUF),
    .O(PhaseB_High_2)
  );
  OBUF PhaseB_High_3_OBUF_1566 (
    .I(PhaseB_High_3_OBUF),
    .O(PhaseB_High_3)
  );
  OBUF PhaseB_High_4_OBUF_1567 (
    .I(PhaseB_High_4_OBUF),
    .O(PhaseB_High_4)
  );
  OBUF PhaseB_High_5_OBUF_1568 (
    .I(PhaseB_High_5_OBUF),
    .O(PhaseB_High_5)
  );
  OBUF PhaseB_High_6_OBUF_1569 (
    .I(PhaseB_High_6_OBUF),
    .O(PhaseB_High_6)
  );
  OBUF PhaseB_High_7_OBUF_1570 (
    .I(PhaseB_High_7_OBUF),
    .O(PhaseB_High_7)
  );
  OBUF PhaseB_High_8_OBUF_1571 (
    .I(PhaseB_High_8_OBUF),
    .O(PhaseB_High_8)
  );
  OBUF Motor3_Phase_A_LIN_OBUF_1572 (
    .I(Motor3_Phase_A_LIN_OBUF),
    .O(Motor3_Phase_A_LIN)
  );
  OBUF Motor4_Phase_B_HIN_OBUF_1573 (
    .I(Motor4_Phase_B_HIN_OBUF),
    .O(Motor4_Phase_B_HIN)
  );
  OBUF Motor1_Phase_B_HIN_OBUF_1574 (
    .I(Motor1_Phase_B_HIN_OBUF),
    .O(Motor1_Phase_B_HIN)
  );
  OBUF PhaseA_High_1_OBUF_1575 (
    .I(PhaseA_High_1_OBUF),
    .O(PhaseA_High_1)
  );
  OBUF PhaseA_High_2_OBUF_1576 (
    .I(PhaseA_High_2_OBUF),
    .O(PhaseA_High_2)
  );
  OBUF PhaseA_High_3_OBUF_1577 (
    .I(PhaseA_High_3_OBUF),
    .O(PhaseA_High_3)
  );
  OBUF PhaseA_High_4_OBUF_1578 (
    .I(PhaseA_High_4_OBUF),
    .O(PhaseA_High_4)
  );
  OBUF Motor2_Phase_A_HIN_OBUF_1579 (
    .I(Motor2_Phase_A_HIN_OBUF),
    .O(Motor2_Phase_A_HIN)
  );
  OBUF PhaseA_High_5_OBUF_1580 (
    .I(PhaseA_High_5_OBUF),
    .O(PhaseA_High_5)
  );
  OBUF PhaseA_High_6_OBUF_1581 (
    .I(PhaseA_High_6_OBUF),
    .O(PhaseA_High_6)
  );
  OBUF PhaseA_High_7_OBUF_1582 (
    .I(PhaseA_High_7_OBUF),
    .O(PhaseA_High_7)
  );
  OBUF Heater_Control_OBUF_1583 (
    .I(Heater_Control_OBUF),
    .O(Heater_Control)
  );
  OBUF PhaseA_High_8_OBUF_1584 (
    .I(PhaseA_High_8_OBUF),
    .O(PhaseA_High_8)
  );
  OBUF R3enable_OBUF_1585 (
    .I(R3enable_OBUF),
    .O(R3enable)
  );
  OBUF R2enable_OBUF_1586 (
    .I(R2enable_OBUF),
    .O(R2enable)
  );
  OBUF Motor3_Phase_B_LIN_OBUF_1587 (
    .I(Motor3_Phase_B_LIN_OBUF),
    .O(Motor3_Phase_B_LIN)
  );
  OBUF R1enable_OBUF_1588 (
    .I(R1enable_OBUF),
    .O(R1enable)
  );
  OBUF R0enable_OBUF_1589 (
    .I(R0enable_OBUF),
    .O(R0enable)
  );
  OBUF AS0_OBUF_1590 (
    .I(AS0_OBUF),
    .O(AS0)
  );
  OBUF AS1_OBUF_1591 (
    .I(AS1_OBUF),
    .O(AS1)
  );
  OBUF Motor4_Phase_A_LIN_OBUF_1592 (
    .I(Motor4_Phase_A_LIN_OBUF),
    .O(Motor4_Phase_A_LIN)
  );
  OBUF AS2_OBUF_1593 (
    .I(AS2_OBUF),
    .O(AS2)
  );
  OBUF Motor1_Phase_A_LIN_OBUF_1594 (
    .I(Motor1_Phase_A_LIN_OBUF),
    .O(Motor1_Phase_A_LIN)
  );
  OBUF Motor2_Phase_B_HIN_OBUF_1595 (
    .I(Motor2_Phase_B_HIN_OBUF),
    .O(Motor2_Phase_B_HIN)
  );
  OBUF Motor_Power_OBUF_1596 (
    .I(Motor_Power_OBUF),
    .O(Motor_Power)
  );
endmodule