Implement Log
Created on 06:33:31 04/01/05
InputFile = c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/implement/xie0.ini
Executing C:\Xilinx\bin\nt\ngdbuild.exe -p R3384XLTQ144-7 -sd "c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\synthesis" -sd "c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\compile" -sd "c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src" -sd "C:\Program Files\Aldec\Active-HDL 6.2\vlib\XC9500\compile" -uc "SleepyPLD.ucf" "SleepyPLD.ngc" "SleepyPLD.ngd"
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set PATH=C:\Xilinx\bin\nt
Release 6.1i - ngdbuild G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p R3384XLTQ144-7 -sd
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\synthesis -sd
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\compile -sd
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src -sd "C:\Program
Files\Aldec\Active-HDL 6.2\vlib\XC9500\compile" -uc SleepyPLD.ucf SleepyPLD.ngc
SleepyPLD.ngd
Reading NGO file
"c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/implement/ver0/bringup0/Sleepy
PLD.ngc" ...
Reading component libraries for design expansion...
Annotating constraints to design from file "SleepyPLD.ucf" ...
Checking timing specifications ...
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 36476 kilobytes
Writing NGD file "SleepyPLD.ngd" ...
Writing NGDBUILD log file "SleepyPLD.bld"...
NGDBUILD done.
Executing C:\Xilinx\bin\nt\cpldfit.exe -p XCR3384XL-7-TQ144 -loc on -slew slow -init low -unused pullup -terminate float -optimize density -nofbnand -inputs 32 -pterms 28 -inreg on -blkfanin 38 "SleepyPLD.ngd"
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set PATH=C:\Xilinx\bin\nt
Release 6.1i - CPLD Optimizer/Partitioner G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:1007 - Removing unused input(s) 'PC104_RESET'. The input(s) are
unused after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<0>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<1>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<2>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<3>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<4>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<5>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<6>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Cpld:1007 - Removing unused input(s) 'SA<7>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Considering device XCR3384XL-7-TQ144.
Re-checking device resources ...
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Synthesizing and Optimizing...
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Fitting...
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Cpld:829 - Signal 'IOCHCHK_MC.TRST' has been minimized to 'GND'.
Cpld:829 - Signal 'ENDXFR_MC.TRST' has been minimized to 'GND'.
Design SleepyPLD has been optimized and fit into device XCR3384XL-7-TQ144.
Executing C:\Xilinx\bin\nt\tsim.exe "SleepyPLD.vm6" "SleepyPLD.nga"
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set PATH=C:\Xilinx\bin\nt
Release 6.1i - CPLD Timing Simulation Interface G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Creating NGA for simulation.
Speed File: Version 6.0
Executing C:\Xilinx\bin\nt\netgen.exe -sim -ofmt verilog -sdf_path c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement "SleepyPLD.nga" "c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0\time_sim.v"
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set PATH=C:\Xilinx\bin\nt
Release 6.1i - netgen G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Reading design SleepyPLD.nga ...
Flattening design ...
Flattening design completed.
Specializing design ...
Specializing design completed.
Preping physical only global signals ...
Preping design's networks ...
Preping design's macros ...
Writing Verilog SDF file
c:\projects\genosensor\2g\cplds\sleepy\sleepypld\implement\time_sim.sdf ...
Writing Verilog netlist file
c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/implement/ver0/bringup0/time_si
m.v ...
INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
simulator compile and invocation commands in order to allow proper
initialization of the design. If simulation is performed within Project
Navigator, this will be taken care of automatically. For more information on
compiling and performing Xilinx simulation, consult the online Synthesis and
Simulation Design Guide:
http://support.xilinx.com/support/software_manuals.htm
Total memory usage is 35760 kilobytes
Created netgen log file
'c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0\t
ime_s
im.nlf'.
Executing C:\Xilinx\bin\nt\hprep6.exe -i "SleepyPLD" -r jed -a -l "SleepyPLD.log" -n "SleepyPLD"
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\implement\ver0\bringup0>set PATH=C:\Xilinx\bin\nt
Release 6.1i - Programming File Generator G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Implementation ver0->bringup0: 0 error(s), 43 warning(s)
Implementation ended with warning(s).