//--------------------------------------------------------------------------------------------------
//
// Title       : SleepyPLD
// Design      : SleepyPLD
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\compile\SleepyPLD.v
// Generated   : Fri Apr  1 07:10:28 2005
// From        : C:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\SleepyPLD.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps

module SleepyPLD (AEN,AM0Status,AM1Status,AM2Status,AS,Bus_Select,CPLD_Reset,CameraStatus,ExternalStatus,IORD,
IOWR,ModemStatus,PC104_RESET,RD,SCLinc,SCLreset,SMCLK,SystemStatus,UINT,WR,
SA,AM0EN,AM1EN,AM2EN,CONcon0,CONcon1,CONcon2,CONextr,CONmodem,CameraEN,
DwarfEN,ENDXFR,ExternalEN,INT,IOCHCHK,IRQ,LOOPcon0,LOOPcon1,LOOPcon2,LOOPextr,
LOOPmodem,ModemEN,SYSPWR,SystemEN,UCS,UIOR,UIOW,EN,PD,UAD,
SCL,AD,SD,UD) ;

// ------------ Port declarations --------- //
input AEN;
wire AEN;
input AM0Status;
wire AM0Status;
input AM1Status;
wire AM1Status;
input AM2Status;
wire AM2Status;
input AS;
wire AS;
input Bus_Select;
wire Bus_Select;
input CPLD_Reset;
wire CPLD_Reset;
input CameraStatus;
wire CameraStatus;
input ExternalStatus;
wire ExternalStatus;
input IORD;
wire IORD;
input IOWR;
wire IOWR;
input ModemStatus;
wire ModemStatus;
input PC104_RESET;
wire PC104_RESET;
input RD;
wire RD;
input SCLinc;
wire SCLinc;
input SCLreset;
wire SCLreset;
input SMCLK;
wire SMCLK;
input SystemStatus;
wire SystemStatus;
input UINT;
wire UINT;
input WR;
wire WR;
input [15:0] SA;
wire [15:0] SA;
output AM0EN;
wire AM0EN;
output AM1EN;
wire AM1EN;
output AM2EN;
wire AM2EN;
output CONcon0;
wire CONcon0;
output CONcon1;
wire CONcon1;
output CONcon2;
wire CONcon2;
output CONextr;
wire CONextr;
output CONmodem;
wire CONmodem;
output CameraEN;
wire CameraEN;
output DwarfEN;
wire DwarfEN;
output ENDXFR;
wire ENDXFR;
output ExternalEN;
wire ExternalEN;
output INT;
wire INT;
output IOCHCHK;
wire IOCHCHK;
output IRQ;
wire IRQ;
output LOOPcon0;
wire LOOPcon0;
output LOOPcon1;
wire LOOPcon1;
output LOOPcon2;
wire LOOPcon2;
output LOOPextr;
wire LOOPextr;
output LOOPmodem;
wire LOOPmodem;
output ModemEN;
wire ModemEN;
output SYSPWR;
wire SYSPWR;
output SystemEN;
wire SystemEN;
output UCS;
wire UCS;
output UIOR;
wire UIOR;
output UIOW;
wire UIOW;
output [7:0] EN;
wire [7:0] EN;
output [7:0] PD;
wire [7:0] PD;
output [7:0] UAD;
wire [7:0] UAD;
inout SCL;
wire SCL;
inout [7:0] AD;
wire [7:0] AD;
inout [7:0] SD;
wire [7:0] SD;
inout [7:0] UD;
wire [7:0] UD;

// ----------- Signal declarations -------- //
wire MCLK;
wire NET1432;
wire NET1440;
wire NET1448;
wire NET1456;
wire NET1474;
wire NET1523;
wire NET1535;
wire NET1764;
wire NET2480;
wire NET2533;
wire NET3560;
wire NET4340;
wire Reset;
wire [7:0] ADDR;
wire [7:0] inDATA;
wire [7:0] outDATA;

// -------- Component instantiations -------//

AddDecode U1
(
	.ADDR(ADDR),
	.AS(AS),
	.RD(RD),
	.Rslct0(NET1535),
	.Rslct1(NET2533),
	.Rslct6(NET1523),
	.WR(WR),
	.Wslct0(NET2480),
	.Wslct2(NET1432),
	.Wslct3(NET1440),
	.Wslct4(NET1456),
	.Wslct5(NET1474),
	.Wslct6(NET1448),
	.Wslct7(NET3560),
	.Wslct8(NET4340)
);



assign Reset = ~(CPLD_Reset);


assign MCLK = SMCLK;


Interface U2
(
	.AD(AD),
	.ADDR(ADDR),
	.AS(AS),
	.MCLK(MCLK),
	.RD(RD),
	.Reset(Reset),
	.WR(WR),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



UARTaddr U3
(
	.ADDR(ADDR),
	.AEN(AEN),
	.Bus_Select(Bus_Select),
	.IORD(IORD),
	.IOWR(IOWR),
	.IRQ(IRQ),
	.MCLK(MCLK),
	.RD(RD),
	.Reset(Reset),
	.SA(SA),
	.SD(SD),
	.SLPYPCADDR(NET4340),
	.UARTaddr(UAD),
	.UARTcs(UCS),
	.UDATA(UD),
	.UINT(UINT),
	.UIOR(UIOR),
	.UIOW(UIOW),
	.WR(WR),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



GalvRelay U4
(
	.CONcon0(CONcon0),
	.CONcon1(CONcon1),
	.CONcon2(CONcon2),
	.CONextr(CONextr),
	.CONmodem(CONmodem),
	.LOOPcon0(LOOPcon0),
	.LOOPcon1(LOOPcon1),
	.LOOPcon2(LOOPcon2),
	.LOOPextr(LOOPextr),
	.LOOPmodem(LOOPmodem),
	.MCLK(MCLK),
	.Reset(Reset),
	.SLPYCON(NET1432),
	.SLPYLP(NET1440),
	.inDATA(inDATA)
);



TransceiverControl U5
(
	.Enable(EN),
	.MCLK(MCLK),
	.PwrDwn(PD),
	.Reset(Reset),
	.SLPYEN(NET1456),
	.SLPYPD(NET1474),
	.inDATA(inDATA)
);



PwrControl U6
(
	.AM0EN(AM0EN),
	.AM0Status(AM0Status),
	.AM1EN(AM1EN),
	.AM1Status(AM1Status),
	.AM2EN(AM2EN),
	.AM2Status(AM2Status),
	.CameraEN(CameraEN),
	.CameraStatus(CameraStatus),
	.DwarfEN(DwarfEN),
	.ExternalEN(ExternalEN),
	.ExternalStatus(ExternalStatus),
	.MCLK(MCLK),
	.ModemEN(ModemEN),
	.ModemStatus(ModemStatus),
	.Reset(Reset),
	.SLPYPWR(NET1448),
	.SLPYSTATUS(NET1523),
	.SLPYSYSEN(NET3560),
	.SYSPWR(SYSPWR),
	.SystemEN(SystemEN),
	.SystemStatus(SystemStatus),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



I2Cfix U7
(
	.Inc(SCLinc),
	.MCLK(MCLK),
	.SCL(SCL),
	.SCLint(NET1764),
	.SCLreset(SCLreset),
	.SLPYI2CCNTr(NET1535),
	.outDATA(outDATA)
);



Interrupt U8
(
	.AM0Status(AM0Status),
	.AM1Status(AM1Status),
	.AM2Status(AM2Status),
	.CameraStatus(CameraStatus),
	.ExternalStatus(ExternalStatus),
	.INT(INT),
	.MCLK(MCLK),
	.ModemStatus(ModemStatus),
	.Reset(Reset),
	.SCLint(NET1764),
	.SLPYIEw(NET2480),
	.SLPYIFGr(NET2533),
	.SystemEN(SystemEN),
	.SystemStatus(SystemStatus),
	.UARTint(UINT),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



UnusedPins U9
(
	.ENDXFR(ENDXFR),
	.IOCHCHK(IOCHCHK)
);



endmodule