 
cpldfit:  version G.26                              Xilinx Inc.
                                  Fitter Report
Design Name: SleepyPLD                           Date:  4- 1-2005,  5:15PM
Device Used: XCR3384XL-7-TQ144
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
116/384 ( 30%) 336 /1344 ( 25%) 69 /384 ( 18%) 110/114 ( 96%) 412/960 ( 43%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   34          34    |  I/O              :   109        1
Output        :   50          50    |  GCK/IO           :     1        3
Bidirectional :   25          25    |  
GCK           :    1           1    |  
                 ----        ----
        Total      110         110

MACROCELL RESOURCES:

Total Macrocells Available                   384
Registered Macrocells                         69
Non-registered Macrocell driving I/O          39

GLOBAL RESOURCES:

Signal 'SMCLK' mapped onto global clock net GCK3.
Universal Control Terms (Used/Total)                      : 1/4

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Total)     : 1/192
Total Foldback NANDs (Used/Total)                         : 0/192

End of Resource Summary
****************************  Errors and Warnings  *************************

WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:1007 - Removing unused input(s) 'PC104_RESET'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:829 - Signal 'IOCHCHK_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'ENDXFR_MC.TRST' has been minimized to 'GND'.
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg Init
Name                Pt    Used            Rate #    Type      Use     State
AD<0>               5       18    FB6_16  SLOW 69   I/O       I/O     
AD<1>               4       23    FB15_5  SLOW 56   I/O       I/O     
AD<2>               5       17    FB15_13 SLOW 55   I/O       I/O     
AD<3>               5       17    FB15_16 SLOW 54   I/O       I/O     
AD<4>               5       17    FB16_16 SLOW 53   I/O       I/O     
AD<5>               5       17    FB16_4  SLOW 49   I/O       I/O     
AD<6>               4       16    FB16_2  SLOW 48   I/O       I/O     
AD<7>               10      22    FB14_2  SLOW 47   I/O       I/O     
AM0EN               3       13    FB7_15  SLOW 75   I/O       O       RESET
AM1EN               3       13    FB8_16  SLOW 74   I/O       O       RESET
AM2EN               3       13    FB8_3   SLOW 72   I/O       O       RESET
CONcon0             3       13    FB4_5   SLOW 111  I/O       O       RESET
CONcon1             3       13    FB4_4   SLOW 110  I/O       O       RESET
CONcon2             3       13    FB4_3   SLOW 107  I/O       O       RESET
CONextr             3       13    FB4_2   SLOW 106  I/O       O       RESET
CONmodem            3       13    FB4_1   SLOW 104  I/O       O       RESET
CameraEN            3       13    FB7_3   SLOW 78   I/O       O       RESET
DwarfEN             3       13    FB8_1   SLOW 70   I/O       O       RESET
EN<0>               3       13    FB2_4   SLOW 98   I/O       O       RESET
EN<1>               3       13    FB2_3   SLOW 97   I/O       O       RESET
EN<2>               3       13    FB2_2   SLOW 96   I/O       O       RESET
EN<3>               3       13    FB1_1   SLOW 94   I/O       O       RESET
EN<4>               3       13    FB1_5   SLOW 93   I/O       O       RESET
EN<5>               3       13    FB1_13  SLOW 92   I/O       O       RESET
EN<6>               3       13    FB1_16  SLOW 91   I/O       O       RESET
EN<7>               3       13    FB3_4   SLOW 90   I/O       O       RESET
ENDXFR              0       0     FB21_16 SLOW 37   I/O       O       
ExternalEN          3       13    FB8_2   SLOW 71   I/O       O       RESET
INT                 9       18    FB14_3  SLOW 46   I/O       O       
IOCHCHK             0       0     FB23_14 SLOW 35   I/O       O       
IRQ                 1       2     FB21_14 SLOW 39   I/O       O       
LOOPcon0            3       13    FB2_16  SLOW 103  I/O       O       RESET
LOOPcon1            3       13    FB2_15  SLOW 102  I/O       O       RESET
LOOPcon2            3       13    FB2_14  SLOW 101  I/O       O       RESET
LOOPextr            3       13    FB2_13  SLOW 100  I/O       O       RESET
LOOPmodem           3       13    FB2_5   SLOW 99   I/O       O       RESET
ModemEN             3       13    FB7_4   SLOW 77   I/O       O       RESET
N_PZ_409            1       2     FB1_2             (b)       (b)     
N_PZ_508            1       3     FB4_9             (b)       (b)     
N_PZ_514            1       3     FB4_8             (b)       (b)     
N_PZ_522            2       5     FB3_11            (b)       (b)     
N_PZ_539            2       4     FB4_10            (b)       (b)     
PD<0>               3       13    FB3_5   SLOW 89   I/O       O       RESET
PD<1>               3       13    FB3_14  SLOW 88   I/O       O       RESET
PD<2>               3       13    FB3_16  SLOW 87   I/O       O       RESET
PD<3>               3       13    FB5_5   SLOW 84   I/O       O       RESET
PD<4>               3       13    FB5_14  SLOW 83   I/O       O       RESET
PD<5>               3       13    FB5_15  SLOW 82   I/O       O       RESET
PD<6>               3       13    FB5_16  SLOW 81   I/O       O       RESET
PD<7>               3       13    FB7_1   SLOW 80   I/O       O       RESET
SCL                 1       6     FB21_4  SLOW 41   I/O       I/O     RESET
SD<0>               2       5     FB22_3  SLOW 20   I/O       I/O     
SD<1>               2       5     FB22_4  SLOW 21   I/O       I/O     
SD<2>               2       5     FB22_13 SLOW 23   I/O       I/O     
SD<3>               2       5     FB22_16 SLOW 25   I/O       I/O     
SD<4>               2       5     FB24_1  SLOW 26   I/O       I/O     
SD<5>               2       5     FB24_2  SLOW 27   I/O       I/O     
SD<6>               2       5     FB24_3  SLOW 28   I/O       I/O     
SD<7>               2       5     FB24_4  SLOW 29   I/O       I/O     
SYSPWR              3       13    FB23_1  SLOW 36   I/O       O       RESET
SystemEN            3       13    FB7_2   SLOW 79   I/O       O       RESET
U2_ADDR_reg<0>      4       7     FB3_13            (b)       (b)     RESET
U2_ADDR_reg<1>      4       8     FB3_15            (b)       (b)     RESET
U2_ADDR_reg<2>      4       9     FB2_8             (b)       (b)     RESET
U2_ADDR_reg<3>      4       10    FB2_7             (b)       (b)     RESET
U2_ADDR_reg<4>      4       11    FB2_9             (b)       (b)     RESET
U2_ADDR_reg<5>      4       12    FB2_10            (b)       (b)     RESET
U2_ADDR_reg<6>      4       13    FB2_11            (b)       (b)     RESET
U2_ADDR_reg<7>      4       14    FB2_12            (b)       (b)     RESET
U2_ASedge           0       0     FB14_13      45   I/O       I       RESET
U2_AutoInc          2       3     FB3_12            (b)       (b)     RESET
U2_Enable_AD        1       2     FB3_10            (b)       (b)     
U2_WRRDedge         1       1     FB3_9             (b)       (b)     RESET
U3_Mcompar__n0011__n0014
                    16      16    FB6_14            (b)       (b)     
U3_PC104reg<0>      3       13    FB1_10            (b)       (b)     RESET
U3_PC104reg<1>      3       13    FB1_8             (b)       (b)     RESET
U3_PC104reg<2>      3       13    FB1_6             (b)       (b)     RESET
U3_PC104reg<3>      3       13    FB1_15            (b)       (b)     RESET
U3_PC104reg<4>      3       13    FB1_14            (b)       (b)     RESET
U3_PC104reg<5>      3       13    FB1_12            (b)       (b)     RESET
U3_PC104reg<6>      3       13    FB1_11            (b)       (b)     RESET
U3_PC104reg<7>      3       13    FB1_4             (b)       (b)     RESET
U3__n0028           1       3     FB5_12            (b)       (b)     
U7_Incdetect        1       2     FB3_8             (b)       (b)     RESET
U7_ResetDetect      1       2     FB4_12            (b)       (b)     RESET
U7_SCLdetect        1       2     FB4_11            (b)       (b)     RESET
U7_U1/Line_last     0       0     FB15_3       60   I/O       I       RESET
U7_U3_counterr<0>   6       11    FB3_7             (b)       (b)     RESET
U7_U3_counterr<1>   8       12    FB5_13            (b)       (b)     RESET
U7_U3_counterr<2>   4       8     FB3_3             (b)       (b)     RESET
U7_U3_counterr<3>   6       9     FB3_6             (b)       (b)     RESET
U7_U3_counterr<4>   6       8     FB3_2             (b)       (b)     RESET
U7_U3_counterr<5>   5       8     FB5_2        86   TCK/I/O   (b)     RESET
U7_U4/Line_last     0       0     FB22_1       19   I/O       I       RESET
U8/SLPYIE<0>        3       13    FB1_9             (b)       (b)     RESET
U8/SLPYIE<1>        3       13    FB1_7             (b)       (b)     RESET
U8/SLPYIE<2>        3       13    FB1_3             (b)       (b)     RESET
UAD<0>              2       4     FB4_14  SLOW 113  I/O       O       
UAD<1>              2       4     FB4_15  SLOW 114  I/O       O       
UAD<2>              2       4     FB4_16  SLOW 116  I/O       O       
UAD<3>              2       4     FB11_5  SLOW 117  I/O       O       
UAD<4>              2       4     FB11_15 SLOW 118  I/O       O       
UAD<5>              3       5     FB11_16 SLOW 119  I/O       O       
UAD<6>              3       6     FB9_5   SLOW 120  I/O       O       
UAD<7>              3       7     FB9_1   SLOW 122  I/O       O       
UCS                 3       7     FB4_13  SLOW 112  I/O       O       
UD<0>               3       5     FB12_13 SLOW 136  I/O       I/O     
UD<1>               3       5     FB12_4  SLOW 137  I/O       I/O     
UD<2>               3       5     FB12_3  SLOW 138  I/O       I/O     
UD<3>               3       5     FB12_1  SLOW 139  I/O       I/O     
UD<4>               3       5     FB19_15 SLOW 140  I/O       I/O     
UD<5>               3       5     FB19_5  SLOW 141  I/O       I/O     
UD<6>               3       5     FB19_4  SLOW 142  I/O       I/O     
UD<7>               3       5     FB19_2  SLOW 143  I/O       I/O     
UIOR                2       4     FB10_4  SLOW 132  I/O       O       
UIOW                2       4     FB10_16 SLOW 134  I/O       O       

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
AEN                               FB21_13      40   I/O       I                  
AM0Status                         FB13_16      66   I/O       I                  
AM1Status                         FB13_14      65   I/O       I                  
AM2Status                         FB13_4       63   I/O       I                  
AS                                FB14_13      45   I/O       I                  
Bus_Select                        FB21_3       42   I/O       I                  
CPLD_Reset                        FB20_16      18   I/O       I                  
CameraStatus                      FB6_1        67   I/O       I                  
ExternalStatus                    FB13_1       61   I/O       I                  
IORD                              FB24_14      32   I/O       I                  
IOWR                              FB24_16      34   I/O       I                  
ModemStatus                       FB13_3       62   I/O       I                  
RD                                FB14_16      43   I/O       I                  
SA<0>                             FB17_16      1    I/O       I                  
SA<10>                            FB18_16      12   I/O       I                  
SA<11>                            FB20_1       14   I/O       I                  
SA<12>                            FB20_4       15   I/O       I                  
SA<13>                            FB20_14      16   I/O       I                  
SA<14>                            FB24_5       30   I/O       I                  
SA<15>                            FB24_13      31   I/O       I                  
SA<1>                             FB17_15      2    I/O       I                  
SA<2>                             FB17_5       4    I/O       I                  
SA<3>                             FB17_4       5    I/O       I                  
SA<4>                             FB17_3       6    I/O       I                  
SA<5>                             FB18_1       7    I/O       I                  
SA<6>                             FB18_2       8    I/O       I                  
SA<7>                             FB18_3       9    I/O       I                  
SA<8>                             FB18_4       10   I/O       I                  
SA<9>                             FB18_15      11   I/O       I                  
SCLinc                            FB15_3       60   I/O       I                  
SCLreset                          FB22_1       19   I/O       I                  
SMCLK                                          125  GCK/I     GCK                
SystemStatus                      FB6_15       68   I/O       I                  
UINT                              FB10_15      133  I/O       I                  
WR                                FB14_14      44   I/O       I                  

End of Resources

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          16          34          34           47         4/0        4   
FB2          14          31          31           48         8/0        8   
FB3          15          38          38           48         4/0        4   
FB4          14          37          37           30         9/0        9   
FB5           7          36          36           26         4/0        4   
FB6           2          34          34           21         0/1        3   
FB7           5          20          20           15         5/0        5   
FB8           4          19          19           12         4/0        4   
FB9           2           8           8            6         2/0        2   
FB10          2           6           6            4         2/0        3   
FB11          3           8           8            7         3/0        3   
FB12          4          11          11            8         0/4        4   
FB13          0           0           0            0         0/0        5   
FB14          3          33          33           19         1/1        5   
FB15          4          27          27           11         0/3        4   
FB16          3          22          22           11         0/3        3   
FB17          0           0           0            0         0/0        5   
FB18          0           0           0            0         0/0        6   
FB19          4          11          11            8         0/4        4   
FB20          0           0           0            0         0/0        4   
FB21          3           8           8            2         2/1        5   
FB22          5           8           8            5         0/4        5   
FB23          2          13          13            3         2/0        2   
FB24          4           8           8            5         0/4        8   
            ----                                -----       -----     ----- 
            116                                  336        50/25     109   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  34
Number of function block inputs used/remaining:               34/6
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   47/1
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
EN<3>                               3    FB1_1      94   I/O     O
N_PZ_409                            1    FB1_2           (b)   (b)
U8/SLPYIE<2>                        3    FB1_3           (b)   (b)
U3_PC104reg<7>                      3    FB1_4           (b)   (b)
EN<4>                               3    FB1_5      93   I/O     O
U3_PC104reg<2>                      3    FB1_6           (b)   (b)
U8/SLPYIE<1>                        3    FB1_7           (b)   (b)
U3_PC104reg<1>                      3    FB1_8           (b)   (b)
U8/SLPYIE<0>                        3    FB1_9           (b)   (b)
U3_PC104reg<0>                      3    FB1_10          (b)   (b)
U3_PC104reg<6>                      3    FB1_11          (b)   (b)
U3_PC104reg<5>                      3    FB1_12          (b)   (b)
EN<5>                               3    FB1_13     92   I/O     O
U3_PC104reg<4>                      3    FB1_14          (b)   (b)
U3_PC104reg<3>                      3    FB1_15          (b)   (b)
EN<6>                               3    FB1_16     91   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN         13: EN<6>             24: U3_PC104reg<1> 
  2: AD<1>.PIN         14: RD                25: U3_PC104reg<2> 
  3: AD<2>.PIN         15: U2_ADDR_reg<0>    26: U3_PC104reg<3> 
  4: AD<3>.PIN         16: U2_ADDR_reg<1>    27: U3_PC104reg<4> 
  5: AD<4>.PIN         17: U2_ADDR_reg<2>    28: U3_PC104reg<5> 
  6: AD<5>.PIN         18: U2_ADDR_reg<3>    29: U3_PC104reg<6> 
  7: AD<6>.PIN         19: U2_ADDR_reg<4>    30: U3_PC104reg<7> 
  8: AD<7>.PIN         20: U2_ADDR_reg<5>    31: U8/SLPYIE<0> 
  9: CPLD_Reset        21: U2_ADDR_reg<6>    32: U8/SLPYIE<1> 
 10: EN<3>             22: U2_ADDR_reg<7>    33: U8/SLPYIE<2> 
 11: EN<4>             23: U3_PC104reg<0>    34: WR 
 12: EN<5>            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
EN<3>             ...X....XX...XXXXXXXXX...........X...... 13      13
N_PZ_409          .............X...................X...... 2       2
U8/SLPYIE<2>      .......XX....XXXXXXXXX..........XX...... 13      13
U3_PC104reg<7>    .......XX....XXXXXXXXX.......X...X...... 13      13
EN<4>             ....X...X.X..XXXXXXXXX...........X...... 13      13
U3_PC104reg<2>    ..X.....X....XXXXXXXXX..X........X...... 13      13
U8/SLPYIE<1>      .X......X....XXXXXXXXX.........X.X...... 13      13
U3_PC104reg<1>    .X......X....XXXXXXXXX.X.........X...... 13      13
U8/SLPYIE<0>      X.......X....XXXXXXXXX........X..X...... 13      13
U3_PC104reg<0>    X.......X....XXXXXXXXXX..........X...... 13      13
U3_PC104reg<6>    ......X.X....XXXXXXXXX......X....X...... 13      13
U3_PC104reg<5>    .....X..X....XXXXXXXXX.....X.....X...... 13      13
EN<5>             .....X..X..X.XXXXXXXXX...........X...... 13      13
U3_PC104reg<4>    ....X...X....XXXXXXXXX....X......X...... 13      13
U3_PC104reg<3>    ...X....X....XXXXXXXXX...X.......X...... 13      13
EN<6>             ......X.X...XXXXXXXXXX...........X...... 13      13
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  31
Number of function block inputs used/remaining:               31/9
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   48/0
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB2_1           (b)      
EN<2>                               3    FB2_2      96   I/O     O
EN<1>                               3    FB2_3      97   I/O     O
EN<0>                               3    FB2_4      98   I/O     O
LOOPmodem                           3    FB2_5      99   I/O     O
(unused)                            0    FB2_6           (b)      
U2_ADDR_reg<3>                      4    FB2_7           (b)   (b)
U2_ADDR_reg<2>                      4    FB2_8           (b)   (b)
U2_ADDR_reg<4>                      4    FB2_9           (b)   (b)
U2_ADDR_reg<5>                      4    FB2_10          (b)   (b)
U2_ADDR_reg<6>                      4    FB2_11          (b)   (b)
U2_ADDR_reg<7>                      4    FB2_12          (b)   (b)
LOOPextr                            3    FB2_13    100   I/O     O
LOOPcon2                            3    FB2_14    101   I/O     O
LOOPcon1                            3    FB2_15    102   I/O     O
LOOPcon0                            3    FB2_16    103   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN         12: EN<1>             22: U2_ADDR_reg<0> 
  2: AD<1>.PIN         13: EN<2>             23: U2_ADDR_reg<1> 
  3: AD<2>.PIN         14: LOOPcon0          24: U2_ADDR_reg<2> 
  4: AD<3>.PIN         15: LOOPcon1          25: U2_ADDR_reg<3> 
  5: AD<4>.PIN         16: LOOPcon2          26: U2_ADDR_reg<4> 
  6: AD<5>.PIN         17: LOOPextr          27: U2_ADDR_reg<5> 
  7: AD<6>.PIN         18: LOOPmodem         28: U2_ADDR_reg<6> 
  8: AD<7>.PIN         19: N_PZ_409          29: U2_ADDR_reg<7> 
  9: AS                20: N_PZ_522          30: U2_ASedge 
 10: CPLD_Reset        21: RD                31: WR 
 11: EN<0>            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
EN<2>             ..X......X..X.......XXXXXXXXX.X......... 13      13
EN<1>             .X.......X.X........XXXXXXXXX.X......... 13      13
EN<0>             X........XX.........XXXXXXXXX.X......... 13      13
LOOPmodem         .......X.X.......X..XXXXXXXXX.X......... 13      13
U2_ADDR_reg<3>    ...X....XX........XX.XXXX....X.......... 10      10
U2_ADDR_reg<2>    ..X.....XX........XX.XXX.....X.......... 9       9
U2_ADDR_reg<4>    ....X...XX........XX.XXXXX...X.......... 11      11
U2_ADDR_reg<5>    .....X..XX........XX.XXXXXX..X.......... 12      12
U2_ADDR_reg<6>    ......X.XX........XX.XXXXXXX.X.......... 13      13
U2_ADDR_reg<7>    .......XXX........XX.XXXXXXXXX.......... 14      14
LOOPextr          ......X..X......X...XXXXXXXXX.X......... 13      13
LOOPcon2          ..X......X.....X....XXXXXXXXX.X......... 13      13
LOOPcon1          .X.......X....X.....XXXXXXXXX.X......... 13      13
LOOPcon0          X........X...X......XXXXXXXXX.X......... 13      13
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  38
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   48/0
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB3_1           (b)      
U7_U3_counterr<4>                   6    FB3_2           (b)   (b)
U7_U3_counterr<2>                   4    FB3_3           (b)   (b)
EN<7>                               3    FB3_4      90   I/O     O
PD<0>                               3    FB3_5      89   I/O     O
U7_U3_counterr<3>                   6    FB3_6           (b)   (b)
U7_U3_counterr<0>                   6    FB3_7           (b)   (b)
U7_Incdetect                        1    FB3_8           (b)   (b)
U2_WRRDedge                         1    FB3_9           (b)   (b)
U2_Enable_AD                        1    FB3_10          (b)   (b)
N_PZ_522                            2    FB3_11          (b)   (b)
U2_AutoInc                          2    FB3_12          (b)   (b)
U2_ADDR_reg<0>                      4    FB3_13          (b)   (b)
PD<1>                               3    FB3_14     88   I/O     O
U2_ADDR_reg<1>                      4    FB3_15          (b)   (b)
PD<2>                               3    FB3_16     87   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN         14: PD<1>             27: U2_ASedge 
  2: AD<1>.PIN         15: PD<2>             28: U2_AutoInc 
  3: AD<2>.PIN         16: RD                29: U2_WRRDedge 
  4: AD<7>.PIN         17: SCLinc            30: U7_Incdetect 
  5: AS                18: SCLreset          31: U7_SCLdetect 
  6: CPLD_Reset        19: U2_ADDR_reg<0>    32: U7_U1/Line_last 
  7: EN<7>             20: U2_ADDR_reg<1>    33: U7_U3_counterr<0> 
  8: N_PZ_409          21: U2_ADDR_reg<2>    34: U7_U3_counterr<2> 
  9: N_PZ_508          22: U2_ADDR_reg<3>    35: U7_U3_counterr<3> 
 10: N_PZ_514          23: U2_ADDR_reg<4>    36: U7_U3_counterr<4> 
 11: N_PZ_522          24: U2_ADDR_reg<5>    37: U7_U3_counterr<5> 
 12: N_PZ_539          25: U2_ADDR_reg<6>    38: WR 
 13: PD<0>             26: U2_ADDR_reg<7>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
U7_U3_counterr<4> 
                  ........XX.X.................X...XXXX... 8       8
U7_U3_counterr<2> 
                  ........XX.X.................X...XXXX... 8       8
EN<7>             ...X.XX........X..XXXXXXXX...........X.. 13      13
PD<0>             X....X......X..X..XXXXXXXX...........X.. 13      13
U7_U3_counterr<3> 
                  ........XX.X.....X...........X...XXXX... 9       9
U7_U3_counterr<0> 
                  .........X.X....XX...........XX.XXXXX... 11      11
U7_Incdetect      ................X..............X........ 2       2
U2_WRRDedge       .......X................................ 1       1
U2_Enable_AD      ...............X.....................X.. 2       2
N_PZ_522          ....X..X..................XXX........... 5       5
U2_AutoInc        ....X..X....................X........... 3       3
U2_ADDR_reg<0>    X...XX.X..X.......X.......X............. 7       7
PD<1>             .X...X.......X.X..XXXXXXXX...........X.. 13      13
U2_ADDR_reg<1>    .X..XX.X..X.......XX......X............. 8       8
PD<2>             ..X..X........XX..XXXXXXXX...........X.. 13      13
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  37
Number of function block inputs used/remaining:               37/3
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   30/18
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
CONmodem                            3    FB4_1     104   I/O     O
CONextr                             3    FB4_2     106   I/O     O
CONcon2                             3    FB4_3     107   I/O     O
CONcon1                             3    FB4_4     110   I/O     O
CONcon0                             3    FB4_5     111   I/O     O
(unused)                            0    FB4_6           (b)      
(unused)                            0    FB4_7           (b)      
N_PZ_514                            1    FB4_8           (b)   (b)
N_PZ_508                            1    FB4_9           (b)   (b)
N_PZ_539                            2    FB4_10          (b)   (b)
U7_SCLdetect                        1    FB4_11          (b)   (b)
U7_ResetDetect                      1    FB4_12          (b)   (b)
UCS                                 3    FB4_13    112   I/O     O
UAD<0>                              2    FB4_14    113   I/O     O
UAD<1>                              2    FB4_15    114   I/O     O
UAD<2>                              2    FB4_16    116   I/O     O

Signals Used by Logic in Function Block
  1: AD<0>.PIN         14: RD                26: U2_ADDR_reg<4> 
  2: AD<1>.PIN         15: SA<0>             27: U2_ADDR_reg<5> 
  3: AD<2>.PIN         16: SA<1>             28: U2_ADDR_reg<6> 
  4: AD<6>.PIN         17: SA<2>             29: U2_ADDR_reg<7> 
  5: AD<7>.PIN         18: SCL               30: U3_Mcompar__n0011__n0014 
  6: AEN               19: SCL.PIN           31: U7_Incdetect 
  7: Bus_Select        20: SCLinc            32: U7_ResetDetect 
  8: CONcon0           21: SCLreset          33: U7_SCLdetect 
  9: CONcon1           22: U2_ADDR_reg<0>    34: U7_U3_counterr<0> 
 10: CONcon2           23: U2_ADDR_reg<1>    35: U7_U3_counterr<1> 
 11: CONextr           24: U2_ADDR_reg<2>    36: U7_U4/Line_last 
 12: CONmodem          25: U2_ADDR_reg<3>    37: WR 
 13: CPLD_Reset       

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
CONmodem          ....X......XXX.......XXXXXXXX.......X... 13      13
CONextr           ...X......X.XX.......XXXXXXXX.......X... 13      13
CONcon2           ..X......X..XX.......XXXXXXXX.......X... 13      13
CONcon1           .X......X...XX.......XXXXXXXX.......X... 13      13
CONcon0           X......X....XX.......XXXXXXXX.......X... 13      13
N_PZ_514          ................................XXX..... 3       3
N_PZ_508          ................................XXX..... 3       3
N_PZ_539          ...................XX.........XX........ 4       4
U7_SCLdetect      .................XX..................... 2       2
U7_ResetDetect    ....................X..............X.... 2       2
UCS               .....XX..................XXXXX.......... 7       7
UAD<0>            ......X.......X......X.......X.......... 4       4
UAD<1>            ......X........X......X......X.......... 4       4
UAD<2>            ......X.........X......X.....X.......... 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block:  36
Number of function block inputs used/remaining:               36/4
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   26/22
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB5_1           (b)      
U7_U3_counterr<5>                   5    FB5_2      86TCK/I/O   (b)
(unused)                            0    FB5_3           (b)      
(unused)                            0    FB5_4           (b)      
PD<3>                               3    FB5_5      84   I/O     O
(unused)                            0    FB5_6           (b)      
(unused)                            0    FB5_7           (b)      
(unused)                            0    FB5_8           (b)      
(unused)                            0    FB5_9           (b)      
(unused)                            0    FB5_10          (b)      
(unused)                            0    FB5_11          (b)      
U3__n0028                           1    FB5_12          (b)   (b)
U7_U3_counterr<1>                   8    FB5_13          (b)   (b)
PD<4>                               3    FB5_14     83   I/O     O
PD<5>                               3    FB5_15     82   I/O     O
PD<6>                               3    FB5_16     81   I/O     O

Signals Used by Logic in Function Block
  1: AD<3>.PIN         13: RD                25: U7_ResetDetect 
  2: AD<4>.PIN         14: SCLinc            26: U7_SCLdetect 
  3: AD<5>.PIN         15: SCLreset          27: U7_U3_counterr<0> 
  4: AD<6>.PIN         16: U2_ADDR_reg<0>    28: U7_U3_counterr<1> 
  5: CPLD_Reset        17: U2_ADDR_reg<1>    29: U7_U3_counterr<2> 
  6: N_PZ_508          18: U2_ADDR_reg<2>    30: U7_U3_counterr<3> 
  7: N_PZ_514          19: U2_ADDR_reg<3>    31: U7_U3_counterr<4> 
  8: N_PZ_539          20: U2_ADDR_reg<4>    32: U7_U3_counterr<5> 
  9: PD<3>             21: U2_ADDR_reg<5>    33: UCS 
 10: PD<4>             22: U2_ADDR_reg<6>    34: UIOR 
 11: PD<5>             23: U2_ADDR_reg<7>    35: UIOW 
 12: PD<6>             24: U7_Incdetect      36: WR 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
U7_U3_counterr<5> 
                  .....XXX...............X....XXXX........ 8       8
PD<3>             X...X...X...X..XXXXXXXX............X.... 13      13
U3__n0028         ................................XXX..... 3       3
U7_U3_counterr<1> 
                  .....X.......XX........XXXXXXXXX........ 12      12
PD<4>             .X..X....X..X..XXXXXXXX............X.... 13      13
PD<5>             ..X.X.....X.X..XXXXXXXX............X.... 13      13
PD<6>             ...XX......XX..XXXXXXXX............X.... 13      13
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block:  34
Number of function block inputs used/remaining:               34/6
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   21/27
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB6_1      67   I/O     I
(unused)                            0    FB6_2           (b)      
(unused)                            0    FB6_3           (b)      
(unused)                            0    FB6_4           (b)      
(unused)                            0    FB6_5           (b)      
(unused)                            0    FB6_6           (b)      
(unused)                            0    FB6_7           (b)      
(unused)                            0    FB6_8           (b)      
(unused)                            0    FB6_9           (b)      
(unused)                            0    FB6_10          (b)      
(unused)                            0    FB6_11          (b)      
(unused)                            0    FB6_12          (b)      
(unused)                            0    FB6_13          (b)      
U3_Mcompar__n0011__n0014           16    FB6_14          (b)   (b)
(unused)                            0    FB6_15     68   I/O     I
AD<0>                               5    FB6_16     69   I/O   I/O

Signals Used by Logic in Function Block
  1: Bus_Select        13: U2_ADDR_reg<1>    24: U3_PC104reg<3> 
  2: RD                14: U2_ADDR_reg<2>    25: U3_PC104reg<4> 
  3: SA<10>            15: U2_ADDR_reg<3>    26: U3_PC104reg<5> 
  4: SA<11>            16: U2_ADDR_reg<4>    27: U3_PC104reg<6> 
  5: SA<12>            17: U2_ADDR_reg<5>    28: U3_PC104reg<7> 
  6: SA<13>            18: U2_ADDR_reg<6>    29: U7_U3_counterr<0> 
  7: SA<14>            19: U2_ADDR_reg<7>    30: UCS 
  8: SA<15>            20: U2_Enable_AD      31: UD<0>.PIN 
  9: SA<8>             21: U3_PC104reg<0>    32: UINT 
 10: SA<9>             22: U3_PC104reg<1>    33: UIOR 
 11: SystemStatus      23: U3_PC104reg<2>    34: WR 
 12: U2_ADDR_reg<0>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
U3_Mcompar__n0011__n0014 
                  ..XXXXXXXX..........XXXXXXXX............ 16      16
AD<0>             XX........XXXXXXXXXX........XXXXXX...... 18      18
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block:  20
Number of function block inputs used/remaining:               20/20
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   15/33
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
PD<7>                               3    FB7_1      80   I/O     O
SystemEN                            3    FB7_2      79   I/O     O
CameraEN                            3    FB7_3      78   I/O     O
ModemEN                             3    FB7_4      77   I/O     O
(unused)                            0    FB7_5           (b)      
(unused)                            0    FB7_6           (b)      
(unused)                            0    FB7_7           (b)      
(unused)                            0    FB7_8           (b)      
(unused)                            0    FB7_9           (b)      
(unused)                            0    FB7_10          (b)      
(unused)                            0    FB7_11          (b)      
(unused)                            0    FB7_12          (b)      
(unused)                            0    FB7_13          (b)      
(unused)                            0    FB7_14          (b)      
AM0EN                               3    FB7_15     75   I/O     O
(unused)                            0    FB7_16          (b)      

Signals Used by Logic in Function Block
  1: AD<0>.PIN          8: ModemEN           15: U2_ADDR_reg<3> 
  2: AD<2>.PIN          9: PD<7>             16: U2_ADDR_reg<4> 
  3: AD<3>.PIN         10: RD                17: U2_ADDR_reg<5> 
  4: AD<7>.PIN         11: SystemEN          18: U2_ADDR_reg<6> 
  5: AM0EN             12: U2_ADDR_reg<0>    19: U2_ADDR_reg<7> 
  6: CPLD_Reset        13: U2_ADDR_reg<1>    20: WR 
  7: CameraEN          14: U2_ADDR_reg<2>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
PD<7>             ...X.X..XX.XXXXXXXXX.................... 13      13
SystemEN          X....X...XXXXXXXXXXX.................... 13      13
CameraEN          .X...XX..X.XXXXXXXXX.................... 13      13
ModemEN           ...X.X.X.X.XXXXXXXXX.................... 13      13
AM0EN             ..X.XX...X.XXXXXXXXX.................... 13      13
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block:  19
Number of function block inputs used/remaining:               19/21
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   12/36
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
DwarfEN                             3    FB8_1      70   I/O     O
ExternalEN                          3    FB8_2      71   I/O     O
AM2EN                               3    FB8_3      72   I/O     O
(unused)                            0    FB8_4           (b)      
(unused)                            0    FB8_5           (b)      
(unused)                            0    FB8_6           (b)      
(unused)                            0    FB8_7           (b)      
(unused)                            0    FB8_8           (b)      
(unused)                            0    FB8_9           (b)      
(unused)                            0    FB8_10          (b)      
(unused)                            0    FB8_11          (b)      
(unused)                            0    FB8_12          (b)      
(unused)                            0    FB8_13          (b)      
(unused)                            0    FB8_14          (b)      
(unused)                            0    FB8_15          (b)      
AM1EN                               3    FB8_16     74   I/O     O

Signals Used by Logic in Function Block
  1: AD<1>.PIN          8: DwarfEN           14: U2_ADDR_reg<3> 
  2: AD<4>.PIN          9: ExternalEN        15: U2_ADDR_reg<4> 
  3: AD<5>.PIN         10: RD                16: U2_ADDR_reg<5> 
  4: AD<6>.PIN         11: U2_ADDR_reg<0>    17: U2_ADDR_reg<6> 
  5: AM1EN             12: U2_ADDR_reg<1>    18: U2_ADDR_reg<7> 
  6: AM2EN             13: U2_ADDR_reg<2>    19: WR 
  7: CPLD_Reset       

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
DwarfEN           X.....XX.XXXXXXXXXX..................... 13      13
ExternalEN        ...X..X.XXXXXXXXXXX..................... 13      13
AM2EN             ..X..XX..XXXXXXXXXX..................... 13      13
AM1EN             .X..X.X..XXXXXXXXXX..................... 13      13
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB9 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   6/42
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
UAD<7>                              3    FB9_1     122   I/O     O
(unused)                            0    FB9_2           (b)      
(unused)                            0    FB9_3     121TDO/I/O      
(unused)                            0    FB9_4           (b)      
UAD<6>                              3    FB9_5     120   I/O     O
(unused)                            0    FB9_6           (b)      
(unused)                            0    FB9_7           (b)      
(unused)                            0    FB9_8           (b)      
(unused)                            0    FB9_9           (b)      
(unused)                            0    FB9_10          (b)      
(unused)                            0    FB9_11          (b)      
(unused)                            0    FB9_12          (b)      
(unused)                            0    FB9_13          (b)      
(unused)                            0    FB9_14          (b)      
(unused)                            0    FB9_15          (b)      
(unused)                            0    FB9_16          (b)      

Signals Used by Logic in Function Block
  1: Bus_Select         4: U2_ADDR_reg<4>     7: U2_ADDR_reg<7> 
  2: SA<6>              5: U2_ADDR_reg<5>     8: U3_Mcompar__n0011__n0014 
  3: SA<7>              6: U2_ADDR_reg<6>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
UAD<7>            X.XXXXXX................................ 7       7
UAD<6>            XX.XXX.X................................ 6       6
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB10 ***********************************
Number of signals used by logic mapping into function block:  6
Number of function block inputs used/remaining:               6/34
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   4/44
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB10_1          (b)      
(unused)                            0    FB10_2          (b)      
(unused)                            0    FB10_3    131TDI/I/O      
UIOR                                2    FB10_4    132   I/O     O
(unused)                            0    FB10_5          (b)      
(unused)                            0    FB10_6          (b)      
(unused)                            0    FB10_7          (b)      
(unused)                            0    FB10_8          (b)      
(unused)                            0    FB10_9          (b)      
(unused)                            0    FB10_10         (b)      
(unused)                            0    FB10_11         (b)      
(unused)                            0    FB10_12         (b)      
(unused)                            0    FB10_13         (b)      
(unused)                            0    FB10_14         (b)      
(unused)                            0    FB10_15   133   I/O     I
UIOW                                2    FB10_16   134   I/O     O

Signals Used by Logic in Function Block
  1: Bus_Select         3: IOWR               5: UCS 
  2: IORD               4: RD                 6: WR 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
UIOR              XX.XX................................... 4       4
UIOW              X.X.XX.................................. 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB11 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   7/41
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB11_1          (b)      
(unused)                            0    FB11_2          (b)      
(unused)                            0    FB11_3          (b)      
(unused)                            0    FB11_4          (b)      
UAD<3>                              2    FB11_5    117   I/O     O
(unused)                            0    FB11_6          (b)      
(unused)                            0    FB11_7          (b)      
(unused)                            0    FB11_8          (b)      
(unused)                            0    FB11_9          (b)      
(unused)                            0    FB11_10         (b)      
(unused)                            0    FB11_11         (b)      
(unused)                            0    FB11_12         (b)      
(unused)                            0    FB11_13         (b)      
(unused)                            0    FB11_14         (b)      
UAD<4>                              2    FB11_15   118   I/O     O
UAD<5>                              3    FB11_16   119   I/O     O

Signals Used by Logic in Function Block
  1: Bus_Select         4: SA<5>              7: U2_ADDR_reg<5> 
  2: SA<3>              5: U2_ADDR_reg<3>     8: U3_Mcompar__n0011__n0014 
  3: SA<4>              6: U2_ADDR_reg<4>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
UAD<3>            XX..X..X................................ 4       4
UAD<4>            X.X..X.X................................ 4       4
UAD<5>            X..X.XXX................................ 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB12 ***********************************
Number of signals used by logic mapping into function block:  11
Number of function block inputs used/remaining:               11/29
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   8/40
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
UD<3>                               3    FB12_1    139   I/O   I/O
(unused)                            0    FB12_2          (b)      
UD<2>                               3    FB12_3    138   I/O   I/O
UD<1>                               3    FB12_4    137   I/O   I/O
(unused)                            0    FB12_5          (b)      
(unused)                            0    FB12_6          (b)      
(unused)                            0    FB12_7          (b)      
(unused)                            0    FB12_8          (b)      
(unused)                            0    FB12_9          (b)      
(unused)                            0    FB12_10         (b)      
(unused)                            0    FB12_11         (b)      
(unused)                            0    FB12_12         (b)      
UD<0>                               3    FB12_13   136   I/O   I/O
(unused)                            0    FB12_14         (b)      
(unused)                            0    FB12_15         (b)      
(unused)                            0    FB12_16         (b)      

Signals Used by Logic in Function Block
  1: AD<0>.PIN          5: Bus_Select         9: SD<3>.PIN 
  2: AD<1>.PIN          6: SD<0>.PIN         10: UCS 
  3: AD<2>.PIN          7: SD<1>.PIN         11: UIOW 
  4: AD<3>.PIN          8: SD<2>.PIN        

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
UD<3>             ...XX...XXX............................. 5       5
UD<2>             ..X.X..X.XX............................. 5       5
UD<1>             .X..X.X..XX............................. 5       5
UD<0>             X...XX...XX............................. 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB13 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB13_1     61   I/O     I
(unused)                            0    FB13_2          (b)      
(unused)                            0    FB13_3     62   I/O     I
(unused)                            0    FB13_4     63   I/O     I
(unused)                            0    FB13_5          (b)      
(unused)                            0    FB13_6          (b)      
(unused)                            0    FB13_7          (b)      
(unused)                            0    FB13_8          (b)      
(unused)                            0    FB13_9          (b)      
(unused)                            0    FB13_10         (b)      
(unused)                            0    FB13_11         (b)      
(unused)                            0    FB13_12         (b)      
(unused)                            0    FB13_13         (b)      
(unused)                            0    FB13_14    65   I/O     I
(unused)                            0    FB13_15         (b)      
(unused)                            0    FB13_16    66   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB14 ***********************************
Number of signals used by logic mapping into function block:  33
Number of function block inputs used/remaining:               33/7
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   19/29
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB14_1          (b)      
AD<7>                              10    FB14_2     47   I/O   I/O
INT                                 9    FB14_3     46   I/O     O
(unused)                            0    FB14_4          (b)      
(unused)                            0    FB14_5          (b)      
(unused)                            0    FB14_6          (b)      
(unused)                            0    FB14_7          (b)      
(unused)                            0    FB14_8          (b)      
(unused)                            0    FB14_9          (b)      
(unused)                            0    FB14_10         (b)      
(unused)                            0    FB14_11         (b)      
(unused)                            0    FB14_12         (b)      
U2_ASedge                           0    FB14_13    45   I/O     I
(unused)                            0    FB14_14    44   I/O     I
(unused)                            0    FB14_15         (b)      
(unused)                            0    FB14_16    43   I/O     I

Signals Used by Logic in Function Block
  1: AM0Status         12: U2_ADDR_reg<1>    23: U7_U3_counterr<3> 
  2: AM1Status         13: U2_ADDR_reg<2>    24: U7_U3_counterr<4> 
  3: AM2Status         14: U2_ADDR_reg<3>    25: U7_U3_counterr<5> 
  4: Bus_Select        15: U2_ADDR_reg<4>    26: U8/SLPYIE<0> 
  5: CameraStatus      16: U2_ADDR_reg<5>    27: U8/SLPYIE<1> 
  6: ExternalStatus    17: U2_ADDR_reg<6>    28: U8/SLPYIE<2> 
  7: ModemStatus       18: U2_ADDR_reg<7>    29: UCS 
  8: RD                19: U2_Enable_AD      30: UD<7>.PIN 
  9: SystemEN          20: U7_U3_counterr<0> 31: UINT 
 10: SystemStatus      21: U7_U3_counterr<1> 32: UIOR 
 11: U2_ADDR_reg<0>    22: U7_U3_counterr<2> 33: WR 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
AD<7>             ...X..XX..XXXXXXXXXXXXXXX...XX.XX....... 22      22
INT               XXX.XXX.XX.........XXXXXXXXX..X......... 18      18
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB15 ***********************************
Number of signals used by logic mapping into function block:  27
Number of function block inputs used/remaining:               27/13
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   11/37
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB15_1          (b)      
(unused)                            0    FB15_2          (b)      
U7_U1/Line_last                     0    FB15_3     60   I/O     I
(unused)                            0    FB15_4          (b)      
AD<1>                               4    FB15_5     56   I/O   I/O
(unused)                            0    FB15_6          (b)      
(unused)                            0    FB15_7          (b)      
(unused)                            0    FB15_8          (b)      
(unused)                            0    FB15_9          (b)      
(unused)                            0    FB15_10         (b)      
(unused)                            0    FB15_11         (b)      
(unused)                            0    FB15_12         (b)      
AD<2>                               5    FB15_13    55   I/O   I/O
(unused)                            0    FB15_14         (b)      
(unused)                            0    FB15_15         (b)      
AD<3>                               5    FB15_16    54   I/O   I/O

Signals Used by Logic in Function Block
  1: AM0Status         10: U2_ADDR_reg<0>    19: U7_U3_counterr<1> 
  2: AM1Status         11: U2_ADDR_reg<1>    20: U7_U3_counterr<2> 
  3: AM2Status         12: U2_ADDR_reg<2>    21: U7_U3_counterr<3> 
  4: Bus_Select        13: U2_ADDR_reg<3>    22: UCS 
  5: CameraStatus      14: U2_ADDR_reg<4>    23: UD<1>.PIN 
  6: ExternalStatus    15: U2_ADDR_reg<5>    24: UD<2>.PIN 
  7: ModemStatus       16: U2_ADDR_reg<6>    25: UD<3>.PIN 
  8: RD                17: U2_ADDR_reg<7>    26: UIOR 
  9: SystemStatus      18: U2_Enable_AD      27: WR 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
AD<1>             XXXXXXXXXXXXXXXXXXX..XX..XX............. 23      23
AD<2>             ...XX..X.XXXXXXXXX.X.X.X.XX............. 17      17
AD<3>             X..X...X.XXXXXXXXX..XX..XXX............. 17      17
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB16 ***********************************
Number of signals used by logic mapping into function block:  22
Number of function block inputs used/remaining:               22/18
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   11/37
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB16_1          (b)      
AD<6>                               4    FB16_2     48   I/O   I/O
(unused)                            0    FB16_3          (b)      
AD<5>                               5    FB16_4     49   I/O   I/O
(unused)                            0    FB16_5          (b)      
(unused)                            0    FB16_6          (b)      
(unused)                            0    FB16_7          (b)      
(unused)                            0    FB16_8          (b)      
(unused)                            0    FB16_9          (b)      
(unused)                            0    FB16_10         (b)      
(unused)                            0    FB16_11         (b)      
(unused)                            0    FB16_12         (b)      
(unused)                            0    FB16_13         (b)      
(unused)                            0    FB16_14         (b)      
(unused)                            0    FB16_15         (b)      
AD<4>                               5    FB16_16    53   I/O   I/O

Signals Used by Logic in Function Block
  1: AM1Status          9: U2_ADDR_reg<3>    16: U7_U3_counterr<5> 
  2: AM2Status         10: U2_ADDR_reg<4>    17: UCS 
  3: Bus_Select        11: U2_ADDR_reg<5>    18: UD<4>.PIN 
  4: ExternalStatus    12: U2_ADDR_reg<6>    19: UD<5>.PIN 
  5: RD                13: U2_ADDR_reg<7>    20: UD<6>.PIN 
  6: U2_ADDR_reg<0>    14: U2_Enable_AD      21: UIOR 
  7: U2_ADDR_reg<1>    15: U7_U3_counterr<4> 22: WR 
  8: U2_ADDR_reg<2>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
AD<6>             ..XXXXXXXXXXXX..X..XXX.................. 16      16
AD<5>             .XX.XXXXXXXXXX.XX.X.XX.................. 17      17
AD<4>             X.X.XXXXXXXXXXX.XX..XX.................. 17      17
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB17 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB17_1          (b)      
(unused)                            0    FB17_2          (b)      
(unused)                            0    FB17_3      6   I/O     I
(unused)                            0    FB17_4      5   I/O     I
(unused)                            0    FB17_5      4   I/O     I
(unused)                            0    FB17_6          (b)      
(unused)                            0    FB17_7          (b)      
(unused)                            0    FB17_8          (b)      
(unused)                            0    FB17_9          (b)      
(unused)                            0    FB17_10         (b)      
(unused)                            0    FB17_11         (b)      
(unused)                            0    FB17_12         (b)      
(unused)                            0    FB17_13         (b)      
(unused)                            0    FB17_14         (b)      
(unused)                            0    FB17_15     2   I/O     I
(unused)                            0    FB17_16     1   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB18 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB18_1      7   I/O     I
(unused)                            0    FB18_2      8   I/O     I
(unused)                            0    FB18_3      9   I/O     I
(unused)                            0    FB18_4     10   I/O     I
(unused)                            0    FB18_5          (b)      
(unused)                            0    FB18_6          (b)      
(unused)                            0    FB18_7          (b)      
(unused)                            0    FB18_8          (b)      
(unused)                            0    FB18_9          (b)      
(unused)                            0    FB18_10         (b)      
(unused)                            0    FB18_11         (b)      
(unused)                            0    FB18_12         (b)      
(unused)                            0    FB18_13         (b)      
(unused)                            0    FB18_14         (b)      
(unused)                            0    FB18_15    11   I/O     I
(unused)                            0    FB18_16    12   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB19 ***********************************
Number of signals used by logic mapping into function block:  11
Number of function block inputs used/remaining:               11/29
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   8/40
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB19_1          (b)      
UD<7>                               3    FB19_2    143   I/O   I/O
(unused)                            0    FB19_3          (b)      
UD<6>                               3    FB19_4    142   I/O   I/O
UD<5>                               3    FB19_5    141   I/O   I/O
(unused)                            0    FB19_6          (b)      
(unused)                            0    FB19_7          (b)      
(unused)                            0    FB19_8          (b)      
(unused)                            0    FB19_9          (b)      
(unused)                            0    FB19_10         (b)      
(unused)                            0    FB19_11         (b)      
(unused)                            0    FB19_12         (b)      
(unused)                            0    FB19_13         (b)      
(unused)                            0    FB19_14         (b)      
UD<4>                               3    FB19_15   140   I/O   I/O
(unused)                            0    FB19_16         (b)      

Signals Used by Logic in Function Block
  1: AD<4>.PIN          5: Bus_Select         9: SD<7>.PIN 
  2: AD<5>.PIN          6: SD<4>.PIN         10: UCS 
  3: AD<6>.PIN          7: SD<5>.PIN         11: UIOW 
  4: AD<7>.PIN          8: SD<6>.PIN        

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
UD<7>             ...XX...XXX............................. 5       5
UD<6>             ..X.X..X.XX............................. 5       5
UD<5>             .X..X.X..XX............................. 5       5
UD<4>             X...XX...XX............................. 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB20 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB20_1     14   I/O     I
(unused)                            0    FB20_2          (b)      
(unused)                            0    FB20_3          (b)      
(unused)                            0    FB20_4     15   I/O     I
(unused)                            0    FB20_5          (b)      
(unused)                            0    FB20_6          (b)      
(unused)                            0    FB20_7          (b)      
(unused)                            0    FB20_8          (b)      
(unused)                            0    FB20_9          (b)      
(unused)                            0    FB20_10         (b)      
(unused)                            0    FB20_11         (b)      
(unused)                            0    FB20_12         (b)      
(unused)                            0    FB20_13         (b)      
(unused)                            0    FB20_14    16   I/O     I
(unused)                            0    FB20_15         (b)      
(unused)                            0    FB20_16    18   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB21 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   2/46
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB21_1          (b)      
(unused)                            0    FB21_2          (b)      
(unused)                            0    FB21_3     42   I/O     I
SCL                                 1    FB21_4     41   I/O   I/O
(unused)                            0    FB21_5          (b)      
(unused)                            0    FB21_6          (b)      
(unused)                            0    FB21_7          (b)      
(unused)                            0    FB21_8          (b)      
(unused)                            0    FB21_9          (b)      
(unused)                            0    FB21_10         (b)      
(unused)                            0    FB21_11         (b)      
(unused)                            0    FB21_12         (b)      
(unused)                            0    FB21_13    40   I/O     I
IRQ                                 1    FB21_14    39   I/O     O
(unused)                            0    FB21_15         (b)      
ENDXFR                              0    FB21_16    37   I/O     O

Signals Used by Logic in Function Block
  1: Bus_Select         4: U7_U3_counterr<2>  7: U7_U3_counterr<5> 
  2: U7_U3_counterr<0>  5: U7_U3_counterr<3>  8: UINT 
  3: U7_U3_counterr<1>  6: U7_U3_counterr<4>

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
SCL               .XXXXXX................................. 6       6
IRQ               X......X................................ 2       2
ENDXFR            ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB22 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
U7_U4/Line_last                     0    FB22_1     19   I/O     I
(unused)                            0    FB22_2          (b)      
SD<0>                               2    FB22_3     20   I/O   I/O
SD<1>                               2    FB22_4     21   I/O   I/O
(unused)                            0    FB22_5     22TMS/I/O      
(unused)                            0    FB22_6          (b)      
(unused)                            0    FB22_7          (b)      
(unused)                            0    FB22_8          (b)      
(unused)                            0    FB22_9          (b)      
(unused)                            0    FB22_10         (b)      
(unused)                            0    FB22_11         (b)      
(unused)                            0    FB22_12         (b)      
SD<2>                               2    FB22_13    23   I/O   I/O
(unused)                            0    FB22_14         (b)      
(unused)                            0    FB22_15         (b)      
SD<3>                               2    FB22_16    25   I/O   I/O

Signals Used by Logic in Function Block
  1: AEN                4: U3_Mcompar__n0011__n0014 
                                              7: UD<2>.PIN 
  2: Bus_Select         5: UD<0>.PIN          8: UD<3>.PIN 
  3: IORD               6: UD<1>.PIN        

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
SD<0>             XXXXX................................... 5       5
SD<1>             XXXX.X.................................. 5       5
SD<2>             XXXX..X................................. 5       5
SD<3>             XXXX...X................................ 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB23 ***********************************
Number of signals used by logic mapping into function block:  13
Number of function block inputs used/remaining:               13/27
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   3/45
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
SYSPWR                              3    FB23_1     36   I/O     O
(unused)                            0    FB23_2          (b)      
(unused)                            0    FB23_3          (b)      
(unused)                            0    FB23_4          (b)      
(unused)                            0    FB23_5          (b)      
(unused)                            0    FB23_6          (b)      
(unused)                            0    FB23_7          (b)      
(unused)                            0    FB23_8          (b)      
(unused)                            0    FB23_9          (b)      
(unused)                            0    FB23_10         (b)      
(unused)                            0    FB23_11         (b)      
(unused)                            0    FB23_12         (b)      
(unused)                            0    FB23_13         (b)      
IOCHCHK                             0    FB23_14    35   I/O     O
(unused)                            0    FB23_15         (b)      
(unused)                            0    FB23_16         (b)      

Signals Used by Logic in Function Block
  1: AD<0>.PIN          6: U2_ADDR_reg<1>    10: U2_ADDR_reg<5> 
  2: CPLD_Reset         7: U2_ADDR_reg<2>    11: U2_ADDR_reg<6> 
  3: RD                 8: U2_ADDR_reg<3>    12: U2_ADDR_reg<7> 
  4: SYSPWR             9: U2_ADDR_reg<4>    13: WR 
  5: U2_ADDR_reg<0>   

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
SYSPWR            XXXXXXXXXXXXX........................... 13      13
IOCHCHK           ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB24 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
SD<4>                               2    FB24_1     26   I/O   I/O
SD<5>                               2    FB24_2     27   I/O   I/O
SD<6>                               2    FB24_3     28   I/O   I/O
SD<7>                               2    FB24_4     29   I/O   I/O
(unused)                            0    FB24_5     30   I/O     I
(unused)                            0    FB24_6          (b)      
(unused)                            0    FB24_7          (b)      
(unused)                            0    FB24_8          (b)      
(unused)                            0    FB24_9          (b)      
(unused)                            0    FB24_10         (b)      
(unused)                            0    FB24_11         (b)      
(unused)                            0    FB24_12         (b)      
(unused)                            0    FB24_13    31   I/O     I
(unused)                            0    FB24_14    32   I/O     I
(unused)                            0    FB24_15         (b)      
(unused)                            0    FB24_16    34   I/O     I

Signals Used by Logic in Function Block
  1: AEN                4: U3_Mcompar__n0011__n0014 
                                              7: UD<6>.PIN 
  2: Bus_Select         5: UD<4>.PIN          8: UD<7>.PIN 
  3: IORD               6: UD<5>.PIN        

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
SD<4>             XXXXX................................... 5       5
SD<5>             XXXX.X.................................. 5       5
SD<6>             XXXX..X................................. 5       5
SD<7>             XXXX...X................................ 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.

!AD<0> = !Bus_Select * !UD<0>.PIN * !UCS * !UIOR
	# !SystemStatus * WR * !RD * !U2_ADDR_reg<0> * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7>
	# WR * !RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * UINT
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !U7_U3_counterr<0>;
    AD<0>.OE = U2_Enable_AD;

U2_ADDR_reg<0>.T := U2_ADDR_reg<0> * !CPLD_Reset
	# CPLD_Reset * N_PZ_522
	# U2_ADDR_reg<0> * !AD<0>.PIN * !AS * U2_ASedge * 
	N_PZ_409
	# !U2_ADDR_reg<0> * CPLD_Reset * AD<0>.PIN * !AS * 
	U2_ASedge * N_PZ_409;
   U2_ADDR_reg<0>.CLK  =  !SMCLK;	// GCK


// Fast Input Register
U2_ASedge := AS;
   U2_ASedge.CLK  =  !SMCLK;	// GCK

N_PZ_409 = WR * RD;

N_PZ_522 = AS * N_PZ_409 * U2_AutoInc * !U2_WRRDedge
	# !U2_ASedge * N_PZ_409 * U2_AutoInc * !U2_WRRDedge;

!U2_AutoInc := AS;
   U2_AutoInc.CLK  =  !SMCLK;	// GCK
    U2_AutoInc.CE = !N_PZ_409 * U2_WRRDedge;

U2_WRRDedge := N_PZ_409;
   U2_WRRDedge.CLK  =  !SMCLK;	// GCK

U2_ADDR_reg<4>.T := !CPLD_Reset * U2_ADDR_reg<4>
	# !AS * U2_ASedge * N_PZ_409 * U2_ADDR_reg<4> * 
	!AD<4>.PIN
	# U2_ADDR_reg<0> * CPLD_Reset * N_PZ_522 * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * U2_ADDR_reg<3>
	# CPLD_Reset * !AS * U2_ASedge * N_PZ_409 * 
	!U2_ADDR_reg<4> * AD<4>.PIN;
   U2_ADDR_reg<4>.CLK  =  !SMCLK;	// GCK

U2_ADDR_reg<2>.T := !CPLD_Reset * U2_ADDR_reg<2>
	# U2_ADDR_reg<0> * CPLD_Reset * N_PZ_522 * 
	U2_ADDR_reg<1>
	# !AS * U2_ASedge * N_PZ_409 * U2_ADDR_reg<2> * 
	!AD<2>.PIN
	# CPLD_Reset * !AS * U2_ASedge * N_PZ_409 * 
	!U2_ADDR_reg<2> * AD<2>.PIN;
   U2_ADDR_reg<2>.CLK  =  !SMCLK;	// GCK

U2_ADDR_reg<1>.T := !CPLD_Reset * U2_ADDR_reg<1>
	# U2_ADDR_reg<0> * CPLD_Reset * N_PZ_522
	# !AS * U2_ASedge * N_PZ_409 * U2_ADDR_reg<1> * 
	!AD<1>.PIN
	# CPLD_Reset * !AS * U2_ASedge * N_PZ_409 * 
	!U2_ADDR_reg<1> * AD<1>.PIN;
   U2_ADDR_reg<1>.CLK  =  !SMCLK;	// GCK

U2_ADDR_reg<3>.T := !CPLD_Reset * U2_ADDR_reg<3>
	# U2_ADDR_reg<0> * CPLD_Reset * N_PZ_522 * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1>
	# !AS * U2_ASedge * N_PZ_409 * U2_ADDR_reg<3> * 
	!AD<3>.PIN
	# CPLD_Reset * !AS * U2_ASedge * N_PZ_409 * 
	!U2_ADDR_reg<3> * AD<3>.PIN;
   U2_ADDR_reg<3>.CLK  =  !SMCLK;	// GCK

U2_ADDR_reg<5>.T := !CPLD_Reset * U2_ADDR_reg<5>
	# !AS * U2_ASedge * N_PZ_409 * U2_ADDR_reg<5> * 
	!AD<5>.PIN
	# CPLD_Reset * !AS * U2_ASedge * N_PZ_409 * 
	!U2_ADDR_reg<5> * AD<5>.PIN
	# U2_ADDR_reg<0> * CPLD_Reset * N_PZ_522 * 
	U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * U2_ADDR_reg<3>;
   U2_ADDR_reg<5>.CLK  =  !SMCLK;	// GCK

U2_ADDR_reg<6>.T := !CPLD_Reset * U2_ADDR_reg<6>
	# !AS * U2_ASedge * N_PZ_409 * U2_ADDR_reg<6> * 
	!AD<6>.PIN
	# CPLD_Reset * !AS * U2_ASedge * N_PZ_409 * 
	!U2_ADDR_reg<6> * AD<6>.PIN
	# U2_ADDR_reg<0> * CPLD_Reset * N_PZ_522 * 
	U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	U2_ADDR_reg<5>;
   U2_ADDR_reg<6>.CLK  =  !SMCLK;	// GCK

U2_ADDR_reg<7>.T := !CPLD_Reset * U2_ADDR_reg<7>
	# !AS * U2_ASedge * N_PZ_409 * U2_ADDR_reg<7> * 
	!AD<7>.PIN
	# CPLD_Reset * !AS * U2_ASedge * N_PZ_409 * 
	!U2_ADDR_reg<7> * AD<7>.PIN
	# U2_ADDR_reg<0> * CPLD_Reset * N_PZ_522 * 
	U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	U2_ADDR_reg<5> * U2_ADDR_reg<6>;
   U2_ADDR_reg<7>.CLK  =  !SMCLK;	// GCK

!U7_U3_counterr<0>.T := U7_U3_counterr<0> * !SCLreset * N_PZ_539
	# U7_U3_counterr<0> * SCLinc * N_PZ_539
	# !U7_U3_counterr<0> * SCLreset * !SCLinc
	# !N_PZ_539 * U7_Incdetect * U7_SCLdetect
	# !N_PZ_539 * !U7_Incdetect * !U7_SCLdetect
	# !N_PZ_539 * !U7_U3_counterr<3> * !U7_U3_counterr<2> * 
	!U7_U3_counterr<4> * N_PZ_514 * !U7_U3_counterr<5>;
   U7_U3_counterr<0>.CLK  =  !SMCLK;	// GCK

N_PZ_539 = SCLreset
	# !SCLinc * U7_Incdetect * U7_ResetDetect;

U7_Incdetect := !SCLinc * U7_U1/Line_last;
   U7_Incdetect.CLK  =  !SMCLK;	// GCK


// Fast Input Register
U7_U1/Line_last := SCLinc;
   U7_U1/Line_last.CLK  =  !SMCLK;	// GCK

U7_ResetDetect := !SCLreset * U7_U4/Line_last;
   U7_ResetDetect.CLK  =  !SMCLK;	// GCK


// Fast Input Register
U7_U4/Line_last := SCLreset;
   U7_U4/Line_last.CLK  =  !SMCLK;	// GCK

U7_SCLdetect := !SCL.PIN * U7_U2/Line_last;
   U7_SCLdetect.CLK  =  !SMCLK;	// GCK

SCL =  Gnd;
    SCL.OE = !U7_U3_counterr<0> * !U7_U3_counterr<3> * 
	!U7_U3_counterr<2> * !U7_U3_counterr<4> * !U7_U3_counterr<1> * 
	!U7_U3_counterr<5>;
// Fast Input Register
U7_U2/Line_last := SCL.PIN;
   U7_U2/Line_last.CLK  =  !SMCLK;	// GCK

!U7_U3_counterr<3>.T := SCLreset * U7_U3_counterr<3>
	# !SCLreset * N_PZ_539 * !U7_U3_counterr<3>
	# !N_PZ_539 * !U7_Incdetect * U7_U3_counterr<2>
	# !N_PZ_539 * !U7_Incdetect * !N_PZ_514
	# !N_PZ_539 * U7_U3_counterr<2> * N_PZ_508
	# !N_PZ_539 * !U7_Incdetect * !U7_U3_counterr<3> * 
	!U7_U3_counterr<4> * !U7_U3_counterr<5>;
   U7_U3_counterr<3>.CLK  =  !SMCLK;	// GCK

!U7_U3_counterr<2>.T := N_PZ_539 * !U7_U3_counterr<2>
	# !N_PZ_539 * U7_Incdetect * !N_PZ_508
	# !N_PZ_539 * !U7_Incdetect * !N_PZ_514
	# !U7_Incdetect * !U7_U3_counterr<3> * 
	!U7_U3_counterr<2> * !U7_U3_counterr<4> * !U7_U3_counterr<5>;
   U7_U3_counterr<2>.CLK  =  !SMCLK;	// GCK

U7_U3_counterr<4>.T := N_PZ_539 * U7_U3_counterr<4>
	# !N_PZ_539 * U7_Incdetect * U7_U3_counterr<3>
	# !N_PZ_539 * U7_Incdetect * U7_U3_counterr<2> * 
	N_PZ_508
	# !U7_Incdetect * !U7_U3_counterr<3> * 
	!U7_U3_counterr<2> * U7_U3_counterr<4> * N_PZ_514
	# !N_PZ_539 * !U7_Incdetect * !U7_U3_counterr<3> * 
	!U7_U3_counterr<2> * N_PZ_514 * U7_U3_counterr<5>
	# !N_PZ_539 * !U7_U3_counterr<3> * !U7_U3_counterr<2> * 
	!U7_U3_counterr<4> * N_PZ_514 * U7_U3_counterr<5> * N_PZ_508;
   U7_U3_counterr<4>.CLK  =  !SMCLK;	// GCK

N_PZ_514 = !U7_U3_counterr<0> * U7_SCLdetect * 
	!U7_U3_counterr<1>;

!U7_U3_counterr<1> := SCLreset * SCLinc
	# !SCLreset * U7_Incdetect * N_PZ_508
	# U7_U3_counterr<0> * !SCLreset * U7_SCLdetect * 
	!U7_U3_counterr<1>
	# !U7_U3_counterr<0> * !SCLreset * U7_Incdetect * 
	!U7_U3_counterr<1>
	# !SCLreset * !SCLinc * U7_Incdetect * 
	U7_ResetDetect
	# !SCLreset * !U7_Incdetect * !U7_SCLdetect * 
	!U7_U3_counterr<1>
	# !U7_U3_counterr<0> * !SCLreset * !U7_Incdetect * 
	U7_SCLdetect * U7_U3_counterr<1>
	# !SCLreset * U7_SCLdetect * !U7_U3_counterr<3> * 
	!U7_U3_counterr<2> * !U7_U3_counterr<4> * !U7_U3_counterr<1> * 
	!U7_U3_counterr<5>;
   U7_U3_counterr<1>.CLK  =  !SMCLK;	// GCK

U7_U3_counterr<5> := U7_U3_counterr<5>
	$ N_PZ_539 * U7_U3_counterr<5>
	# !N_PZ_539 * U7_Incdetect * U7_U3_counterr<3> * 
	U7_U3_counterr<4>
	# !N_PZ_539 * U7_Incdetect * U7_U3_counterr<2> * 
	U7_U3_counterr<4> * N_PZ_508
	# !U7_Incdetect * !U7_U3_counterr<3> * 
	!U7_U3_counterr<2> * !U7_U3_counterr<4> * N_PZ_514 * U7_U3_counterr<5>;
   U7_U3_counterr<5>.CLK  =  !SMCLK;	// GCK

N_PZ_508 = U7_U3_counterr<0> * !U7_SCLdetect * 
	U7_U3_counterr<1>;

!UCS = U2_ADDR_reg<7> * !Bus_Select
	# Bus_Select * !AEN * !U3_Mcompar__n0011__n0014
	# U2_ADDR_reg<4> * U2_ADDR_reg<5> * U2_ADDR_reg<6> * 
	!Bus_Select;

U3_Mcompar__n0011__n0014 = SA<8> * !U3_PC104reg<0>
	# !SA<8> * U3_PC104reg<0>
	# SA<9> * !U3_PC104reg<1>
	# !SA<9> * U3_PC104reg<1>
	# SA<10> * !U3_PC104reg<2>
	# !SA<10> * U3_PC104reg<2>
	# SA<11> * !U3_PC104reg<3>
	# !SA<11> * U3_PC104reg<3>
	# SA<12> * !U3_PC104reg<4>
	# !SA<12> * U3_PC104reg<4>
	# SA<13> * !U3_PC104reg<5>
	# !SA<13> * U3_PC104reg<5>
	# SA<14> * !U3_PC104reg<6>
	# !SA<14> * U3_PC104reg<6>
	# SA<15> * !U3_PC104reg<7>
	# !SA<15> * U3_PC104reg<7>;

U3_PC104reg<0>.T := !CPLD_Reset * U3_PC104reg<0>
	# !WR * RD * !U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U3_PC104reg<0>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * 
	U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U3_PC104reg<0>;
   U3_PC104reg<0>.CLK  =  !SMCLK;	// GCK

U3_PC104reg<1>.T := !CPLD_Reset * U3_PC104reg<1>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !AD<1>.PIN * U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U3_PC104reg<1>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * AD<1>.PIN * 
	U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U3_PC104reg<1>;
   U3_PC104reg<1>.CLK  =  !SMCLK;	// GCK

U3_PC104reg<2>.T := !CPLD_Reset * U3_PC104reg<2>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !AD<2>.PIN * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U3_PC104reg<2>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * AD<2>.PIN * !U2_ADDR_reg<1> * 
	U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U3_PC104reg<2>;
   U3_PC104reg<2>.CLK  =  !SMCLK;	// GCK

U3_PC104reg<3>.T := !CPLD_Reset * U3_PC104reg<3>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * !AD<3>.PIN * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U3_PC104reg<3>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	AD<3>.PIN * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U3_PC104reg<3>;
   U3_PC104reg<3>.CLK  =  !SMCLK;	// GCK

U3_PC104reg<4>.T := !CPLD_Reset * U3_PC104reg<4>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!AD<4>.PIN * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U3_PC104reg<4>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * AD<4>.PIN * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * 
	U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U3_PC104reg<4>;
   U3_PC104reg<4>.CLK  =  !SMCLK;	// GCK

U3_PC104reg<5>.T := !CPLD_Reset * U3_PC104reg<5>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U3_PC104reg<5>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U3_PC104reg<5>;
   U3_PC104reg<5>.CLK  =  !SMCLK;	// GCK

U3_PC104reg<6>.T := !CPLD_Reset * U3_PC104reg<6>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !AD<6>.PIN * !U2_ADDR_reg<7> * U3_PC104reg<6>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * AD<6>.PIN * !U2_ADDR_reg<7> * 
	!U3_PC104reg<6>;
   U3_PC104reg<6>.CLK  =  !SMCLK;	// GCK

U3_PC104reg<7>.T := !CPLD_Reset * U3_PC104reg<7>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AD<7>.PIN * U3_PC104reg<7>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AD<7>.PIN * 
	!U3_PC104reg<7>;
   U3_PC104reg<7>.CLK  =  !SMCLK;	// GCK

!UIOR = !RD * !Bus_Select * !UCS
	# Bus_Select * !UCS * !IORD;

U2_Enable_AD = WR * !RD;

!AD<1> = !Bus_Select * !UCS * !UIOR * !UD<1>.PIN
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !U7_U3_counterr<1>
	# SystemStatus * WR * !RD * U2_ADDR_reg<0> * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * ModemStatus * 
	ExternalStatus * CameraStatus * AM2Status * AM1Status * 
	AM0Status;
    AD<1>.OE = U2_Enable_AD;

!AD<2> = !Bus_Select * !UCS * !UIOR * !UD<2>.PIN
	# WR * !RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * !U7_U3_counterr<2>
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !CameraStatus;
    AD<2>.OE = U2_Enable_AD;

!AD<3> = !Bus_Select * !UCS * !UIOR * !UD<3>.PIN
	# WR * !RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * !U7_U3_counterr<3>
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AM0Status;
    AD<3>.OE = U2_Enable_AD;

!AD<4> = !Bus_Select * !UCS * !UIOR * !UD<4>.PIN
	# WR * !RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * !U7_U3_counterr<4>
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AM1Status;
    AD<4>.OE = U2_Enable_AD;

!AD<5> = !Bus_Select * !UCS * !UIOR * !UD<5>.PIN
	# WR * !RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * !U7_U3_counterr<5>
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AM2Status;
    AD<5>.OE = U2_Enable_AD;

!AD<6> = !Bus_Select * !UCS * !UIOR * !UD<6>.PIN
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7>
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !ExternalStatus;
    AD<6>.OE = U2_Enable_AD;

!AD<7> = !Bus_Select * !UCS * !UIOR * !UD<7>.PIN
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * U7_U3_counterr<0>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * U7_U3_counterr<3>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * U7_U3_counterr<2>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * U7_U3_counterr<4>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * U7_U3_counterr<1>
	# WR * !RD * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * 
	!U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * 
	!U2_ADDR_reg<7> * U7_U3_counterr<5>
	# WR * !RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !ModemStatus;
    AD<7>.OE = U2_Enable_AD;

AM0EN.T := !CPLD_Reset * AM0EN
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !AD<3>.PIN * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AM0EN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	AD<3>.PIN * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!AM0EN;
   AM0EN.CLK  =  !SMCLK;	// GCK

AM1EN.T := !CPLD_Reset * AM1EN
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!AD<4>.PIN * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AM1EN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * AD<4>.PIN * U2_ADDR_reg<2> * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!AM1EN;
   AM1EN.CLK  =  !SMCLK;	// GCK

AM2EN.T := !CPLD_Reset * AM2EN
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AM2EN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!AM2EN;
   AM2EN.CLK  =  !SMCLK;	// GCK

CONcon0.T := !CPLD_Reset * CONcon0
	# !WR * RD * !U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * CONcon0
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!CONcon0;
   CONcon0.CLK  =  !SMCLK;	// GCK

CONcon1.T := !CPLD_Reset * CONcon1
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * U2_ADDR_reg<1> * !AD<1>.PIN * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * CONcon1
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * AD<1>.PIN * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!CONcon1;
   CONcon1.CLK  =  !SMCLK;	// GCK

CONcon2.T := !CPLD_Reset * CONcon2
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !AD<2>.PIN * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * CONcon2
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * AD<2>.PIN * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!CONcon2;
   CONcon2.CLK  =  !SMCLK;	// GCK

CONextr.T := !CPLD_Reset * CONextr
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !AD<6>.PIN * !U2_ADDR_reg<7> * CONextr
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * AD<6>.PIN * !U2_ADDR_reg<7> * 
	!CONextr;
   CONextr.CLK  =  !SMCLK;	// GCK

CONmodem.T := !CPLD_Reset * CONmodem
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AD<7>.PIN * CONmodem
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AD<7>.PIN * 
	!CONmodem;
   CONmodem.CLK  =  !SMCLK;	// GCK

CameraEN.T := !CPLD_Reset * CameraEN
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !AD<2>.PIN * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * CameraEN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * AD<2>.PIN * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!CameraEN;
   CameraEN.CLK  =  !SMCLK;	// GCK

DwarfEN.T := !CPLD_Reset * DwarfEN
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !AD<1>.PIN * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * DwarfEN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * AD<1>.PIN * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!DwarfEN;
   DwarfEN.CLK  =  !SMCLK;	// GCK

EN<0>.T := !CPLD_Reset * EN<0>
	# !WR * RD * !U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * EN<0>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!EN<0>;
   EN<0>.CLK  =  !SMCLK;	// GCK

EN<1>.T := !CPLD_Reset * EN<1>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !AD<1>.PIN * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * EN<1>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * AD<1>.PIN * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!EN<1>;
   EN<1>.CLK  =  !SMCLK;	// GCK

EN<2>.T := !CPLD_Reset * EN<2>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !AD<2>.PIN * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * EN<2>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * AD<2>.PIN * !U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!EN<2>;
   EN<2>.CLK  =  !SMCLK;	// GCK

EN<3>.T := !CPLD_Reset * EN<3>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !AD<3>.PIN * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * EN<3>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	AD<3>.PIN * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!EN<3>;
   EN<3>.CLK  =  !SMCLK;	// GCK

EN<4>.T := !CPLD_Reset * EN<4>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!AD<4>.PIN * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * EN<4>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * AD<4>.PIN * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!EN<4>;
   EN<4>.CLK  =  !SMCLK;	// GCK

EN<5>.T := !CPLD_Reset * EN<5>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * EN<5>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!EN<5>;
   EN<5>.CLK  =  !SMCLK;	// GCK

EN<6>.T := !CPLD_Reset * EN<6>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !AD<6>.PIN * !U2_ADDR_reg<7> * EN<6>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * AD<6>.PIN * !U2_ADDR_reg<7> * 
	!EN<6>;
   EN<6>.CLK  =  !SMCLK;	// GCK

EN<7>.T := !CPLD_Reset * EN<7>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AD<7>.PIN * EN<7>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AD<7>.PIN * 
	!EN<7>;
   EN<7>.CLK  =  !SMCLK;	// GCK

ENDXFR = Gnd;
    ENDXFR.OE = Gnd;

ExternalEN.T := !CPLD_Reset * ExternalEN
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !AD<6>.PIN * !U2_ADDR_reg<7> * ExternalEN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * AD<6>.PIN * !U2_ADDR_reg<7> * 
	!ExternalEN;
   ExternalEN.CLK  =  !SMCLK;	// GCK

INT = !SystemStatus * U8/SLPYIE<1>
	# !ModemStatus * U8/SLPYIE<1>
	# !ExternalStatus * U8/SLPYIE<1>
	# !CameraStatus * U8/SLPYIE<1>
	# !AM2Status * U8/SLPYIE<1>
	# !AM1Status * U8/SLPYIE<1>
	# !AM0Status * U8/SLPYIE<1>
	# !UINT * !SystemEN * U8/SLPYIE<0>
	# !U7_U3_counterr<0> * !U7_U3_counterr<3> * 
	!U7_U3_counterr<2> * !U7_U3_counterr<4> * !U7_U3_counterr<1> * 
	!U7_U3_counterr<5> * U8/SLPYIE<2>;

SystemEN.T := !CPLD_Reset * SystemEN
	# !WR * RD * !U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * SystemEN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!SystemEN;
   SystemEN.CLK  =  !SMCLK;	// GCK

U8/SLPYIE<0>.T := !CPLD_Reset * U8/SLPYIE<0>
	# !WR * RD * !U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U8/SLPYIE<0>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U8/SLPYIE<0>;
   U8/SLPYIE<0>.CLK  =  !SMCLK;	// GCK

U8/SLPYIE<1>.T := !CPLD_Reset * U8/SLPYIE<1>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !AD<1>.PIN * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * U8/SLPYIE<1>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * AD<1>.PIN * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!U8/SLPYIE<1>;
   U8/SLPYIE<1>.CLK  =  !SMCLK;	// GCK

U8/SLPYIE<2>.T := !CPLD_Reset * U8/SLPYIE<2>
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AD<7>.PIN * U8/SLPYIE<2>
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AD<7>.PIN * 
	!U8/SLPYIE<2>;
   U8/SLPYIE<2>.CLK  =  !SMCLK;	// GCK

IOCHCHK = Gnd;
    IOCHCHK.OE = Gnd;

IRQ = !UINT * Bus_Select;

LOOPcon0.T := !CPLD_Reset * LOOPcon0
	# !WR * RD * U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * LOOPcon0
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!LOOPcon0;
   LOOPcon0.CLK  =  !SMCLK;	// GCK

LOOPcon1.T := !CPLD_Reset * LOOPcon1
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * U2_ADDR_reg<1> * !AD<1>.PIN * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * LOOPcon1
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * AD<1>.PIN * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!LOOPcon1;
   LOOPcon1.CLK  =  !SMCLK;	// GCK

LOOPcon2.T := !CPLD_Reset * LOOPcon2
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * !AD<2>.PIN * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * LOOPcon2
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * AD<2>.PIN * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!LOOPcon2;
   LOOPcon2.CLK  =  !SMCLK;	// GCK

LOOPextr.T := !CPLD_Reset * LOOPextr
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !AD<6>.PIN * !U2_ADDR_reg<7> * LOOPextr
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * AD<6>.PIN * !U2_ADDR_reg<7> * 
	!LOOPextr;
   LOOPextr.CLK  =  !SMCLK;	// GCK

LOOPmodem.T := !CPLD_Reset * LOOPmodem
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AD<7>.PIN * LOOPmodem
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * !U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AD<7>.PIN * 
	!LOOPmodem;
   LOOPmodem.CLK  =  !SMCLK;	// GCK

ModemEN.T := !CPLD_Reset * ModemEN
	# !WR * RD * !U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AD<7>.PIN * ModemEN
	# !WR * RD * !U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AD<7>.PIN * 
	!ModemEN;
   ModemEN.CLK  =  !SMCLK;	// GCK

PD<0>.T := !CPLD_Reset * PD<0>
	# !WR * RD * U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * PD<0>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!PD<0>;
   PD<0>.CLK  =  !SMCLK;	// GCK

PD<1>.T := !CPLD_Reset * PD<1>
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !AD<1>.PIN * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * PD<1>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * AD<1>.PIN * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!PD<1>;
   PD<1>.CLK  =  !SMCLK;	// GCK

PD<2>.T := !CPLD_Reset * PD<2>
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !AD<2>.PIN * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * PD<2>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * AD<2>.PIN * !U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!PD<2>;
   PD<2>.CLK  =  !SMCLK;	// GCK

PD<3>.T := !CPLD_Reset * PD<3>
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !AD<3>.PIN * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * PD<3>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	AD<3>.PIN * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!PD<3>;
   PD<3>.CLK  =  !SMCLK;	// GCK

PD<4>.T := !CPLD_Reset * PD<4>
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	!AD<4>.PIN * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * PD<4>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * AD<4>.PIN * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!PD<4>;
   PD<4>.CLK  =  !SMCLK;	// GCK

PD<5>.T := !CPLD_Reset * PD<5>
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * PD<5>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * AD<5>.PIN * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!PD<5>;
   PD<5>.CLK  =  !SMCLK;	// GCK

PD<6>.T := !CPLD_Reset * PD<6>
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !AD<6>.PIN * !U2_ADDR_reg<7> * PD<6>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * AD<6>.PIN * !U2_ADDR_reg<7> * 
	!PD<6>;
   PD<6>.CLK  =  !SMCLK;	// GCK

PD<7>.T := !CPLD_Reset * PD<7>
	# !WR * RD * U2_ADDR_reg<0> * !U2_ADDR_reg<4> * 
	U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * !U2_ADDR_reg<5> * 
	!U2_ADDR_reg<6> * !U2_ADDR_reg<7> * !AD<7>.PIN * PD<7>
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * !U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * AD<7>.PIN * 
	!PD<7>;
   PD<7>.CLK  =  !SMCLK;	// GCK

SD<0> = UD<0>.PIN;
    SD<0>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SD<1> = UD<1>.PIN;
    SD<1>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SD<2> = UD<2>.PIN;
    SD<2>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SD<3> = UD<3>.PIN;
    SD<3>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SD<4> = UD<4>.PIN;
    SD<4>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SD<5> = UD<5>.PIN;
    SD<5>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SD<6> = UD<6>.PIN;
    SD<6>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SD<7> = UD<7>.PIN;
    SD<7>.OE = Bus_Select * !AEN * !U3_Mcompar__n0011__n0014 * 
	!IORD;

SYSPWR.T := !CPLD_Reset * SYSPWR
	# !WR * RD * U2_ADDR_reg<0> * !AD<0>.PIN * 
	!U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * !U2_ADDR_reg<3> * 
	!U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * SYSPWR
	# !WR * RD * U2_ADDR_reg<0> * CPLD_Reset * 
	AD<0>.PIN * !U2_ADDR_reg<4> * U2_ADDR_reg<2> * U2_ADDR_reg<1> * 
	!U2_ADDR_reg<3> * !U2_ADDR_reg<5> * !U2_ADDR_reg<6> * !U2_ADDR_reg<7> * 
	!SYSPWR;
   SYSPWR.CLK  =  !SMCLK;	// GCK

UAD<0> = U2_ADDR_reg<0> * !Bus_Select
	# Bus_Select * !U3_Mcompar__n0011__n0014 * SA<0>;

UAD<1> = U2_ADDR_reg<1> * !Bus_Select
	# Bus_Select * !U3_Mcompar__n0011__n0014 * SA<1>;

UAD<2> = U2_ADDR_reg<2> * !Bus_Select
	# Bus_Select * !U3_Mcompar__n0011__n0014 * SA<2>;

UAD<3> = U2_ADDR_reg<3> * !Bus_Select
	# Bus_Select * !U3_Mcompar__n0011__n0014 * SA<3>;

UAD<4> = !U2_ADDR_reg<4> * !Bus_Select
	# Bus_Select * !U3_Mcompar__n0011__n0014 * SA<4>;

UAD<5> = U2_ADDR_reg<4> * !U2_ADDR_reg<5> * !Bus_Select
	# !U2_ADDR_reg<4> * U2_ADDR_reg<5> * !Bus_Select
	# Bus_Select * !U3_Mcompar__n0011__n0014 * SA<5>;

UAD<6> = U2_ADDR_reg<6> * !Bus_Select
	$ U2_ADDR_reg<4> * U2_ADDR_reg<5> * !Bus_Select
	# Bus_Select * !U3_Mcompar__n0011__n0014 * SA<6>;

UAD<7> = !U2_ADDR_reg<7> * !Bus_Select
	$ Bus_Select * !U3_Mcompar__n0011__n0014 * SA<7>
	# U2_ADDR_reg<4> * U2_ADDR_reg<5> * U2_ADDR_reg<6> * 
	!Bus_Select;

UD<0> = AD<0>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<0>.PIN;
   !UD<0>.OE = U3__n0028;

!UIOW = !WR * !Bus_Select * !UCS
	# Bus_Select * !UCS * !IOWR;

U3__n0028 = !UCS * !UIOR * UIOW;

UD<1> = AD<1>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<1>.PIN;
   !UD<1>.OE = U3__n0028;

UD<2> = AD<2>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<2>.PIN;
   !UD<2>.OE = U3__n0028;

UD<3> = AD<3>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<3>.PIN;
   !UD<3>.OE = U3__n0028;

UD<4> = AD<4>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<4>.PIN;
   !UD<4>.OE = U3__n0028;

UD<5> = AD<5>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<5>.PIN;
   !UD<5>.OE = U3__n0028;

UD<6> = AD<6>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<6>.PIN;
   !UD<6>.OE = U3__n0028;

UD<7> = AD<7>.PIN * !Bus_Select * !UCS * !UIOW
	# Bus_Select * !UCS * !UIOW * SD<7>.PIN;
   !UD<7>.OE = U3__n0028;



Legend:  <signame>.COMB = combinational node mapped to the same physical macrocell
                          as the FastInput "signal" (not logically related)
****************************  Device Pin Out ****************************

Device : XCR3384XL-7-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 SA<0>                            73 VCC                           
  2 SA<1>                            74 AM1EN                         
  3 GND                              75 AM0EN                         
  4 SA<2>                            76 VCC                           
  5 SA<3>                            77 ModemEN                       
  6 SA<4>                            78 CameraEN                      
  7 SA<5>                            79 SystemEN                      
  8 SA<6>                            80 PD<7>                         
  9 SA<7>                            81 PD<6>                         
 10 SA<8>                            82 PD<5>                         
 11 SA<9>                            83 PD<4>                         
 12 SA<10>                           84 PD<3>                         
 13 GND                              85 GND                           
 14 SA<11>                           86 TCK                           
 15 SA<12>                           87 PD<2>                         
 16 SA<13>                           88 PD<1>                         
 17 GND                              89 PD<0>                         
 18 CPLD_Reset                       90 EN<7>                         
 19 SCLreset                         91 EN<6>                         
 20 SD<0>                            92 EN<5>                         
 21 SD<1>                            93 EN<4>                         
 22 TMS                              94 EN<3>                         
 23 SD<2>                            95 VCC                           
 24 VCC                              96 EN<2>                         
 25 SD<3>                            97 EN<1>                         
 26 SD<4>                            98 EN<0>                         
 27 SD<5>                            99 LOOPmodem                     
 28 SD<6>                           100 LOOPextr                      
 29 SD<7>                           101 LOOPcon2                      
 30 SA<14>                          102 LOOPcon1                      
 31 SA<15>                          103 LOOPcon0                      
 32 IORD                            104 CONmodem                      
 33 PE                              105 GND                           
 34 IOWR                            106 CONextr                       
 35 IOCHCHK                         107 CONcon2                       
 36 SYSPWR                          108 NC                            
 37 ENDXFR                          109 NC                            
 38 PROHIBITED                      110 CONcon1                       
 39 IRQ                             111 CONcon0                       
 40 AEN                             112 UCS                           
 41 SCL                             113 UAD<0>                        
 42 Bus_Select                      114 UAD<1>                        
 43 RD                              115 VCC                           
 44 WR                              116 UAD<2>                        
 45 AS                              117 UAD<3>                        
 46 INT                             118 UAD<4>                        
 47 AD<7>                           119 UAD<5>                        
 48 AD<6>                           120 UAD<6>                        
 49 AD<5>                           121 TDO                           
 50 VCC                             122 UAD<7>                        
 51 VCC                             123 VCC                           
 52 GND                             124 GND                           
 53 AD<4>                           125 SMCLK                         
 54 AD<3>                           126 TIE                           
 55 AD<2>                           127 TIE                           
 56 AD<1>                           128 TIE                           
 57 GND                             129 GND                           
 58 VCC                             130 VCC                           
 59 GND                             131 TDI                           
 60 SCLinc                          132 UIOR                          
 61 ExternalStatus                  133 UINT                          
 62 ModemStatus                     134 UIOW                          
 63 AM2Status                       135 GND                           
 64 GND                             136 UD<0>                         
 65 AM1Status                       137 UD<1>                         
 66 AM0Status                       138 UD<2>                         
 67 CameraStatus                    139 UD<3>                         
 68 SystemStatus                    140 UD<4>                         
 69 AD<0>                           141 UD<5>                         
 70 DwarfEN                         142 UD<6>                         
 71 ExternalEN                      143 UD<7>                         
 72 AM2EN                           144 VCC                           


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XCR3384XL-7-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : OFF
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Input Limit                                 : 32
Pterm Limit                                 : 28
