Design notes for SLeepy
Created 30-Aug-04 SJensen
 
07-APR-05 SJensen
	Changed the power control registers to Async reset.  Also added interlock on Raw bat
	 power enable based on System power and Dwarf power on.	  An idea is to have a reset 
     register that is put into reset Async and then taken out Sych Set = Reset and D= Reset...
     Made v0r7 fbac

04-Jan-05 SJensen
   Going to add a register in sleepy side to set the block adderess off the UART on the
   PC104 side  
   v0r3

15-Dec-04 SJensen
   Need to redifine the Sleepy_PLD_Range to be 0 - ff in the interface module.
   this is to access the UART.
   Made v0r2 dd1d

14-Dec-04 SJensen
  Needed to move from MCLK to SMCLK.  That made the gateway work. 
currently v0r1 e48d

13-Dec-04 SJensen
Made Ver0 Rev1 with the Ivert reset and Bus_selct fixes.

10-Dec-04 SJensen
Rev 0.0.6 has been fabricated.  Starting to populate, this version flashed into part.

* Need to invert CPLD_Reset
* Change the UART select to use the BUS_Select pin not system enable

30-Aug-04 SJensen
Put all the major modules in.  Need to connect and start simulating