//--------------------------------------------------------------------------------------------------
//
// Title       : TransceiverControl
// Design      : SleepyPLD
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\TransceiverControl.v
// Generated   : Fri Aug 27 13:16:33 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {TransceiverControl}}
module TransceiverControl ( inDATA ,PwrDwn ,Reset ,SLPYEN ,SLPYPD ,Enable ,MCLK );

input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input SLPYEN ;
wire SLPYEN ;
input SLPYPD ;
wire SLPYPD ;
input MCLK ;
wire MCLK ;

output [7:0] PwrDwn ;
wire [7:0] PwrDwn ;
output [7:0] Enable ;
wire [7:0] Enable ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [7:0] en;
reg [7:0] pd;

assign PwrDwn = pd;
assign Enable = en;

always @ (negedge MCLK)
	begin
		if (Reset) 
			begin
				pd <= 8'b0;
				en <= 8'b0;
			end					
		else
			begin
				if (SLPYPD) pd <= inDATA[7:0];
				if (SLPYEN) en <= inDATA[7:0];
			end
	end
endmodule