//--------------------------------------------------------------------------------------------------
//
// Title       : UARTaddr
// Design      : SleepyPLD
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\UARTaddr.v
// Generated   : Fri Aug 27 10:59:11 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {UARTaddr}}
module UARTaddr ( UINT ,IOWR ,Reset ,UIOW ,MCLK ,WR ,Bus_Select ,IRQ ,IORD ,UDATA ,inDATA ,outDATA ,UARTcs ,SA ,AEN ,RD ,SLPYPCADDR ,SD ,UARTaddr ,ADDR ,UIOR );

parameter HIGHUART =  8'b0 ;

input UINT ;
wire UINT ;
input IOWR ;
wire IOWR ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input AEN ;
wire AEN ;
input [15:0] SA ;
wire [15:0] SA ;
input SLPYPCADDR ;
wire SLPYPCADDR ;
input RD ;
wire RD ;
input MCLK ;
wire MCLK ;
input WR ;
wire WR ;
input Bus_Select ;
wire Bus_Select ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input IORD ;
wire IORD ;

output [7:0] outDATA ;
wire [7:0] outDATA ;
output UARTcs ;
wire UARTcs ;
output IRQ ;
wire IRQ ;
output UIOW ;
wire UIOW ;
output UIOR ;
wire UIOR ;
output [7:0] UARTaddr ;
wire [7:0] UARTaddr ;

inout [7:0] SD ;
wire [7:0] SD ;
inout [7:0] UDATA ;
wire [7:0] UDATA ;

//}} End of automatically maintained section

// -- Enter your statements here -- //		 	 

reg [7:0] PC104reg;

//The purpose of this module is to traslate the sleepy bus address space of the UART down to the address
//space that the UART uses.  This translate the UART to sleepy address 70 - ff.
assign UARTaddr[7:4] = (Bus_Select) ?  ((SA[15:8] == PC104reg) ? SA[7:4] : 4'b0) : ADDR[7:4] + 4'h9;
assign UARTaddr[3:0] = (Bus_Select) ?  ((SA[15:8] == PC104reg) ? SA[3:0] : 4'b0) : ADDR[3:0];
	
//CS should only begin active while initial the region of the UART
assign UARTcs = (Bus_Select) ?  (((SA[15:8] == PC104reg) & !AEN) ? 1'b0 : 1'b1) : ((ADDR[7:4] >= 4'H7) ? 1'b0 : 1'b1);

//Lock output based on UARTcs.  Pass through the read and write signals
assign UIOR = (Bus_Select) ? UARTcs | IORD : RD | UARTcs;
assign UIOW = (Bus_Select) ? UARTcs | IOWR : WR | UARTcs;

//define the the UARTs data bus, driven while writing, floating while reading and 0 when nothing
assign UDATA = (!UARTcs & !UIOW) ? ((Bus_Select) ? SD : inDATA) : 
			   (!UARTcs & !UIOR) ? 8'bz : 8'b0;
assign outDATA = (!UARTcs & !UIOR & !Bus_Select) ? UDATA : 8'bz;
assign SD =  (!UARTcs & !UIOR & Bus_Select) ? UDATA : 8'bz;	  

assign IRQ = (Bus_Select & !UINT) ? 1'b1 : 1'b0;
 
always @ (negedge MCLK)
	begin
		if (Reset) 
			begin
				PC104reg <= HIGHUART;
			end					
		else
			begin
				if (SLPYPCADDR) PC104reg <= inDATA[7:0];
			end
	end
	
endmodule