//--------------------------------------------------------------------------------------------------
//
// Title       : AddDecode
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\AddDecode.v
// Generated   : Fri Jan 23 09:20:32 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {AddDecode}}
module AddDecode ( Wslct3 ,Wslct4 ,Wslct5 ,Wslct6 ,Wslct7 ,AS ,Wslct8 ,RD ,Rslct0 ,WR ,Rslct1 ,ADDR ,Wslct0 ,Rslct6 ,Wslct2 );

input WR ;
wire WR ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input AS ;
wire AS ;
input RD ;
wire RD ;

output Wslct3 ;
wire Wslct3 ;
output Wslct4 ;
wire Wslct4 ;
output Wslct5 ;
wire Wslct5 ;
output Wslct6 ;
wire Wslct6 ;
output Wslct7 ;
wire Wslct7 ;
output Wslct8 ;
wire Wslct8 ;
output Rslct0 ;
wire Rslct0 ;
output Rslct1 ;
wire Rslct1 ;
output Wslct0 ;
wire Wslct0 ;
output Rslct6 ;
wire Rslct6 ;
output Wslct2 ;
wire Wslct2 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //
//All of these select signals should have a matching
//keep statement for synthesis
	
`define READ 1
`define WRITE 0

function Select;
input [7:0] Address;
input [7:0] Location;
input RD, WR;
input RorW;
 Select =  (RorW == `WRITE) ? (RD & !WR & (ADDR == Location)) :  (!RD & WR & (ADDR ==  Location)) ;
endfunction								   

//s-ynthesis attribute KEEP of DCORr is TRUE;
//assign  DCORr = Select(ADDR, `DCOR1, RD, WR, `READ);

//synthesis attribute KEEP of Wslct0 is TRUE;
assign  Wslct0 = Select(ADDR, 8'h00, RD, WR, `WRITE);
//s ynthesis attribute KEEP of Wslct1 is TRUE;
//assign  Wslct1 = Select(ADDR, 8'h01, RD, WR, `WRITE);
//synthesis attribute KEEP of Wslct2 is TRUE;
assign  Wslct2 = Select(ADDR, 8'h02, RD, WR, `WRITE);
//synthesis attribute KEEP of Wslct3 is TRUE;
assign  Wslct3 = Select(ADDR, 8'h03, RD, WR, `WRITE);
//synthesis attribute KEEP of Wslct4 is TRUE;
assign  Wslct4 = Select(ADDR, 8'h04, RD, WR, `WRITE);
//synthesis attribute KEEP of Wslct5 is TRUE;
assign  Wslct5 = Select(ADDR, 8'h05, RD, WR, `WRITE);
//synthesis attribute KEEP of Wslct6 is TRUE;
assign  Wslct6 = Select(ADDR, 8'h06, RD, WR, `WRITE);
//synthesis attribute KEEP of Wslct7 is TRUE;
assign  Wslct7 = Select(ADDR, 8'h07, RD, WR, `WRITE);
//synthesis attribute KEEP of Wslct8 is TRUE;
assign  Wslct8 = Select(ADDR, 8'h08, RD, WR, `WRITE);

//synthesis attribute KEEP of Rslct0 is TRUE;
assign  Rslct0 = Select(ADDR, 8'h00, RD, WR, `READ);
//synthesis attribute KEEP of Rslct1 is TRUE;
assign  Rslct1 = Select(ADDR, 8'h01, RD, WR, `READ);
//synthesis attribute KEEP of Rslct6 is TRUE;
assign  Rslct6 = Select(ADDR, 8'h06, RD, WR, `READ);

endmodule