//--------------------------------------------------------------------------------------------------
//
// Title       : GalvRelay
// Design      : SleepyPLD
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\GalvRelay.v
// Generated   : Fri Aug 27 12:49:50 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {GalvRelay}}
module GalvRelay ( CONcon0 ,CONcon1 ,inDATA ,CONmodem ,CONcon2 ,CONextr ,Reset ,SLPYLP ,MCLK ,SLPYCON ,LOOPcon0 ,LOOPcon1 ,LOOPmodem ,LOOPcon2 ,LOOPextr );

input SLPYCON ;
wire SLPYCON ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input SLPYLP ;
wire SLPYLP ;
input MCLK ;
wire MCLK ;

output CONcon0 ;
wire CONcon0 ;
output CONcon1 ;
wire CONcon1 ;
output CONmodem ;
wire CONmodem ;
output CONcon2 ;
wire CONcon2 ;
output CONextr ;
wire CONextr ;
output LOOPcon0 ;
wire LOOPcon0 ;
output LOOPcon1 ;
wire LOOPcon1 ;
output LOOPmodem ;
wire LOOPmodem ;
output LOOPcon2 ;
wire LOOPcon2 ;
output LOOPextr ;
wire LOOPextr ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [4:0]  connect;
reg [4:0] loop;

assign {CONmodem, CONextr,CONcon2,CONcon1,CONcon0} = connect;
assign {LOOPmodem, LOOPextr, LOOPcon2, LOOPcon1, LOOPcon0} = loop;

always @ (negedge MCLK)
	begin
		if (Reset) 
			begin
				connect <= 5'b0;
				loop <= 5'b0;
			end					
		else
			begin
				if (SLPYCON) connect <= {inDATA[7:6],inDATA[2:0]};
				if (SLPYLP) loop <= {inDATA[7:6],inDATA[2:0]};
			end
	end
endmodule