//--------------------------------------------------------------------------------------------------
//
// Title       : Interrupt
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U21\src\Interrupt.v
// Generated   : Thu Mar  4 06:27:20 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {Interrupt}}
module Interrupt ( AM0Status ,AM1Status ,Reset ,AM2Status ,ExternalStatus ,MCLK ,UARTint ,SystemStatus ,INT ,SCLint ,SLPYIEw ,CameraStatus ,SLPYIFGr ,inDATA ,outDATA ,ModemStatus ,SystemEN );

input SLPYIFGr ;
wire SLPYIFGr ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input AM0Status ;
wire AM0Status ;
input AM1Status ;
wire AM1Status ;
input Reset ;
wire Reset ;
input AM2Status ;
wire AM2Status ;
input ModemStatus ;
wire ModemStatus ;
input ExternalStatus ;
wire ExternalStatus ;
input MCLK ;
wire MCLK ;
input UARTint ;
wire UARTint ;
input SystemEN ;
wire SystemEN ;
input SystemStatus ;
wire SystemStatus ;
input SCLint ;
wire SCLint ;
input SLPYIEw ;
wire SLPYIEw ;
input CameraStatus ;
wire CameraStatus ;

output [7:0] outDATA ;
wire [7:0] outDATA ;
output INT ;
wire INT ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

wire PWRFlgs;

reg [2:0] SLPYIE;	  

assign PWRFlgs = (!SystemStatus | !CameraStatus | !ExternalStatus | !AM2Status | !AM1Status | !AM0Status | !ModemStatus)	;
assign outDATA = (SLPYIFGr) ? {SCLint, 5'b0,PWRFlgs,!UARTint} : 8'bz;

assign INT =    ((SLPYIE[2] & SCLint) | 
				(SLPYIE[1] & PWRFlgs)| 
				(SLPYIE[0] & (!UARTint) & (!SystemEN)));

always @ (negedge MCLK)
	begin
		if (Reset) SLPYIE <= 3'b0;
		else if (SLPYIEw) SLPYIE <= {inDATA[7],inDATA[1],inDATA[0]};
	end

endmodule