# Wed Sep 08 08:10:07 2004
# XST6 Synthesis
################################################################################
package require ::aldec::scripter 1.0 
set aldec [::aldec::scripter::GetVariable "aldec"]
set dsn [::aldec::scripter::GetVariable "dsn"]
set scr_pth [file join $aldec tcl lib aldec templates mv_xst6 xst.tcl]
namespace eval ::mv_xst6 {
	variable priv_data	
	set priv_data(language) "VHDL"
}
source "$scr_pth"
################################################################################
# following line disables showing log file after synthesis
set show_log 0
################################################################################

# list of files for top-level synthesis
lappend files [file join $dsn src SleepyPLD.bde]
lappend files [file join $dsn src adddecode.v]
lappend files [file join $dsn src interface.v]
lappend files [file join $dsn src UARTaddr.v]
lappend files [file join $dsn src GalvRelay.v]
lappend files [file join $dsn src TransceiverControl.v]
lappend files [file join $dsn src PwrControl.v]
lappend files [file join $dsn src I2Cfix.bde]
lappend files [file join $dsn src negdetect.v]
lappend files [file join $dsn src bitcounter.v]
lappend files [file join $dsn src interrupt.v]
lappend files [file join $dsn src interface.v]
lappend files [file join $dsn src adddecode.v]
lappend files [file join $dsn src galvrelay.v]
lappend files [file join $dsn src TransceiverControl.v]
lappend files [file join $dsn src PwrControl.v]
lappend files [file join $dsn src I2Cfix.bde]
lappend files [file join $dsn src interrupt.v]
lappend files [file join $dsn src uartaddr.v]
# list of macros for macro synthesis
set macros {}
set ::mv_xst6::priv_data(additional_files) ""
set ::mv_xst6::priv_data(alias) ""

set ::mv_xst6::priv_data(family) "Xilinx6x COOLRUNNER"
set ::mv_xst6::priv_data(device) "r3384xlTQ144"
set ::mv_xst6::priv_data(speed) "-7"
set ::mv_xst6::priv_data(_netlist_format) 	"2"
set ::mv_xst6::priv_data(_opt_goal) 	"Speed"
set ::mv_xst6::priv_data(_opt_effort) 	"Normal"
set ::mv_xst6::priv_data(_use_synth_constr) 	"1"
set ::mv_xst6::priv_data(GenerateRtlSchematic) 	"Yes"
set ::mv_xst6::priv_data(Verilog2001) 	"1"
set ::mv_xst6::priv_data(_keep_hierCPLD) 	"Yes"
set ::mv_xst6::priv_data(HierarchySeparator) 	"_"
set ::mv_xst6::priv_data(BusDelimiter) 	"<>"
set ::mv_xst6::priv_data(CaseVhdl) 	"Maintain"
set ::mv_xst6::priv_data(_fsm_encode) 	"Auto"
set ::mv_xst6::priv_data(_mux_extract) 	"Yes"
set ::mv_xst6::priv_data(_impl_style) 	"None"
set ::mv_xst6::priv_data(_rshare) 	"1"
set ::mv_xst6::priv_data(_iobuf) 	"1"
set ::mv_xst6::priv_data(_eq_reg_rem) 	"1"
set ::mv_xst6::priv_data(_clk_en) 	"1"
set ::mv_xst6::priv_data(_mac_pr) 	"1"
set ::mv_xst6::priv_data(_xor_pr) 	"1"
set ::mv_xst6::priv_data(_wysiwyg) 	"None"
set ::mv_xst6::priv_data(_job_desc) 	"JobDesc1"
set ::mv_xst6::priv_data(_incl_inp_files) 	"*.*"
set ::mv_xst6::priv_data(_excl_inp_files) 	"log*.*:implement*.*"

# performs synthesis
::mv_xst6::Run_Synthesis $files $macros
exit