// Xilinx Verilog produced by program ngc2hdl G.26
// Command: -ofmt verilog -intstyle silent -w SleepyPLD.ngc SleepyPLD.v 
// Input file: SleepyPLD.ngc
// Output file: SleepyPLD.v
// Design name: SleepyPLD
// Xilinx: C:/Xilinx

// The output of ngc2hdl is a simulation model. This file cannot be synthesized,
// or used in any other manner other than simulation. This netlist uses simulation
// primitives which may not represent the true implementation of the device, however
// the netlist is functionally correct. Do not modify this file.

`timescale 1 ns/10 ps

module NegDetect (
  Line, MCLK, Ndetect
);
  input Line;
  input MCLK;
  output Ndetect;
  wire Line_last;
  wire _n0001;
  wire Ndetectr__n0002;
  wire _n00011;
  FD Ndetectr (
    .D(_n0001),
    .C(Ndetectr__n0002),
    .Q(Ndetect)
  );
  INV _n00011_2 (
    .I(Line),
    .O(_n00011)
  );
  INV Ndetectr__n00021 (
    .I(MCLK),
    .O(Ndetectr__n0002)
  );
  AND2 _n00012 (
    .I0(Line_last),
    .I1(_n00011),
    .O(_n0001)
  );
  FD Line_last_3 (
    .D(Line),
    .C(Ndetectr__n0002),
    .Q(Line_last)
  );
endmodule

module LPM_XOR2_1 (
  Data_0_, Data_1_, Result
);
  input Data_0_;
  input Data_1_;
  output Result;
  XOR2 Xo_0_1 (
    .I0(Data_0_),
    .I1(Data_1_),
    .O(Result)
  );
endmodule

module Interrupt (
  SCLint, AM2Status, AM1Status, Reset, AM0Status, SystemStatus, ExternalStatus, ModemStatus, SLPYIEw, CameraStatus, UARTint, SLPYIFGr, SystemEN, MCLK
, INT, inDATA, outDATA
);
  input SCLint;
  input AM2Status;
  input AM1Status;
  input Reset;
  input AM0Status;
  input SystemStatus;
  input ExternalStatus;
  input ModemStatus;
  input SLPYIEw;
  input CameraStatus;
  input UARTint;
  input SLPYIFGr;
  input SystemEN;
  input MCLK;
  output INT;
  input [7 : 0] inDATA;
  output [7 : 0] outDATA;
  wire _n0001;
  wire _n0002;
  wire _n0003;
  wire N637;
  wire PWRFlgs;
  wire SLPYIE_0__n0002;
  wire SLPYIE_2__n0003;
  wire SLPYIE_2__n0000;
  wire SLPYIE_1__n0000;
  wire SLPYIE_0__n0000;
  wire SLPYIE_0__n00021;
  wire SLPYIE_0__n00022;
  wire SLPYIE_0__n00023;
  wire INT1;
  wire INT2;
  wire INT3;
  wire INT4;
  wire PWRFlgs1;
  wire _n00031;
  wire _n00032;
  wire SLPYIE_1__n00001;
  wire SLPYIE_2__n00001;
  wire SLPYIE_0__n00001;
  wire [2 : 0] SLPYIE;
  wire [0 : 0] _n0005;
  INV _n00121 (
    .I(UARTint),
    .O(_n0005[0])
  );
  GND XST_GND (
    .G(N637)
  );
  BUFE I1_7 (
    .E(SLPYIFGr),
    .I(SCLint),
    .O(outDATA[7])
  );
  INV SLPYIE_0__n00024 (
    .I(SLPYIE_0__n00023),
    .O(SLPYIE_0__n0002)
  );
  INV INT5 (
    .I(INT4),
    .O(INT)
  );
  INV PWRFlgs2 (
    .I(PWRFlgs1),
    .O(PWRFlgs)
  );
  AND3 _n00033 (
    .I0(_n00031),
    .I1(SLPYIE[0]),
    .I2(_n00032),
    .O(_n0003)
  );
  AND2 _n00021 (
    .I0(SLPYIE[1]),
    .I1(PWRFlgs),
    .O(_n0002)
  );
  AND2 _n00011 (
    .I0(SLPYIE[2]),
    .I1(SCLint),
    .O(_n0001)
  );
  BUFE I1_0 (
    .E(SLPYIFGr),
    .I(_n0005[0]),
    .O(outDATA[0])
  );
  BUFE I1_1 (
    .E(SLPYIFGr),
    .I(PWRFlgs),
    .O(outDATA[1])
  );
  BUFE I1_2 (
    .E(SLPYIFGr),
    .I(N637),
    .O(outDATA[2])
  );
  BUFE I1_3 (
    .E(SLPYIFGr),
    .I(N637),
    .O(outDATA[3])
  );
  BUFE I1_4 (
    .E(SLPYIFGr),
    .I(N637),
    .O(outDATA[4])
  );
  BUFE I1_5 (
    .E(SLPYIFGr),
    .I(N637),
    .O(outDATA[5])
  );
  BUFE I1_6 (
    .E(SLPYIFGr),
    .I(N637),
    .O(outDATA[6])
  );
  FDCE SLPYIE_2 (
    .D(SLPYIE_2__n0000),
    .CE(SLPYIE_0__n0002),
    .CLR(N637),
    .C(SLPYIE_2__n0003),
    .Q(SLPYIE[2])
  );
  FDCE SLPYIE_1 (
    .D(SLPYIE_1__n0000),
    .CE(SLPYIE_0__n0002),
    .CLR(N637),
    .C(SLPYIE_2__n0003),
    .Q(SLPYIE[1])
  );
  FDCE SLPYIE_0 (
    .D(SLPYIE_0__n0000),
    .CE(SLPYIE_0__n0002),
    .CLR(N637),
    .C(SLPYIE_2__n0003),
    .Q(SLPYIE[0])
  );
  INV SLPYIE_2__n00031 (
    .I(MCLK),
    .O(SLPYIE_2__n0003)
  );
  AND2 SLPYIE_1__n00002 (
    .I0(inDATA[1]),
    .I1(SLPYIE_1__n00001),
    .O(SLPYIE_1__n0000)
  );
  AND2 SLPYIE_2__n00002 (
    .I0(inDATA[7]),
    .I1(SLPYIE_2__n00001),
    .O(SLPYIE_2__n0000)
  );
  AND2 SLPYIE_0__n00002 (
    .I0(inDATA[0]),
    .I1(SLPYIE_0__n00001),
    .O(SLPYIE_0__n0000)
  );
  INV SLPYIE_0__n00021_41 (
    .I(SLPYIEw),
    .O(SLPYIE_0__n00021)
  );
  INV SLPYIE_0__n00022_42 (
    .I(Reset),
    .O(SLPYIE_0__n00022)
  );
  AND2 SLPYIE_0__n00023_43 (
    .I0(SLPYIE_0__n00021),
    .I1(SLPYIE_0__n00022),
    .O(SLPYIE_0__n00023)
  );
  INV INT1_44 (
    .I(_n0003),
    .O(INT1)
  );
  INV INT2_45 (
    .I(_n0002),
    .O(INT2)
  );
  INV INT3_46 (
    .I(_n0001),
    .O(INT3)
  );
  AND3 INT4_47 (
    .I0(INT2),
    .I1(INT1),
    .I2(INT3),
    .O(INT4)
  );
  AND7 PWRFlgs1_48 (
    .I0(CameraStatus),
    .I1(ExternalStatus),
    .I2(AM2Status),
    .I3(AM1Status),
    .I4(AM0Status),
    .I5(ModemStatus),
    .I6(SystemStatus),
    .O(PWRFlgs1)
  );
  INV _n00031_49 (
    .I(UARTint),
    .O(_n00031)
  );
  INV _n00032_50 (
    .I(SystemEN),
    .O(_n00032)
  );
  INV SLPYIE_1__n00001_51 (
    .I(Reset),
    .O(SLPYIE_1__n00001)
  );
  INV SLPYIE_2__n00001_52 (
    .I(Reset),
    .O(SLPYIE_2__n00001)
  );
  INV SLPYIE_0__n00001_53 (
    .I(Reset),
    .O(SLPYIE_0__n00001)
  );
endmodule

module PwrControl (
  AM2Status, AM1Status, Reset, AM0Status, SLPYSYSEN, SystemStatus, ExternalStatus, ModemStatus, SLPYSTATUS, CameraStatus, SLPYPWR, MCLK, ModemEN, 
AM2EN, CameraEN, ExternalEN, DwarfEN, AM0EN, SystemEN, AM1EN, SYSPWR, inDATA, outDATA
);
  input AM2Status;
  input AM1Status;
  input Reset;
  input AM0Status;
  input SLPYSYSEN;
  input SystemStatus;
  input ExternalStatus;
  input ModemStatus;
  input SLPYSTATUS;
  input CameraStatus;
  input SLPYPWR;
  input MCLK;
  output ModemEN;
  output AM2EN;
  output CameraEN;
  output ExternalEN;
  output DwarfEN;
  output AM0EN;
  output SystemEN;
  output AM1EN;
  output SYSPWR;
  input [7 : 0] inDATA;
  output [7 : 0] outDATA;
  wire NlwRenamedSig_OI_DwarfEN;
  wire NlwRenamedSig_OI_SystemEN;
  wire _n0000;
  wire N635;
  wire Enable_7_N649;
  assign
    DwarfEN = NlwRenamedSig_OI_DwarfEN,
    SystemEN = NlwRenamedSig_OI_SystemEN;
  BUFE I2_7 (
    .E(SLPYSTATUS),
    .I(ModemStatus),
    .O(outDATA[7])
  );
  VCC XST_VCC (
    .P(N635)
  );
  AND3 _n00001 (
    .I0(inDATA[0]),
    .I1(NlwRenamedSig_OI_DwarfEN),
    .I2(NlwRenamedSig_OI_SystemEN),
    .O(_n0000)
  );
  FDCE SysEn (
    .D(_n0000),
    .CE(SLPYSYSEN),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(SYSPWR)
  );
  INV Enable_7_N6491 (
    .I(MCLK),
    .O(Enable_7_N649)
  );
  FDCE Enable_5 (
    .D(inDATA[5]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(AM2EN)
  );
  BUFE I2_0 (
    .E(SLPYSTATUS),
    .I(SystemStatus),
    .O(outDATA[0])
  );
  BUFE I2_1 (
    .E(SLPYSTATUS),
    .I(N635),
    .O(outDATA[1])
  );
  BUFE I2_2 (
    .E(SLPYSTATUS),
    .I(CameraStatus),
    .O(outDATA[2])
  );
  BUFE I2_3 (
    .E(SLPYSTATUS),
    .I(AM0Status),
    .O(outDATA[3])
  );
  BUFE I2_4 (
    .E(SLPYSTATUS),
    .I(AM1Status),
    .O(outDATA[4])
  );
  BUFE I2_5 (
    .E(SLPYSTATUS),
    .I(AM2Status),
    .O(outDATA[5])
  );
  BUFE I2_6 (
    .E(SLPYSTATUS),
    .I(ExternalStatus),
    .O(outDATA[6])
  );
  FDCE Enable_7 (
    .D(inDATA[7]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(ModemEN)
  );
  FDCE Enable_6 (
    .D(inDATA[6]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(ExternalEN)
  );
  FDCE Enable_0 (
    .D(inDATA[0]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(NlwRenamedSig_OI_SystemEN)
  );
  FDCE Enable_1 (
    .D(inDATA[1]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(NlwRenamedSig_OI_DwarfEN)
  );
  FDCE Enable_2 (
    .D(inDATA[2]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(CameraEN)
  );
  FDCE Enable_3 (
    .D(inDATA[3]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(AM0EN)
  );
  FDCE Enable_4 (
    .D(inDATA[4]),
    .CE(SLPYPWR),
    .CLR(Reset),
    .C(Enable_7_N649),
    .Q(AM1EN)
  );
endmodule

module TransceiverControl (
  Reset, SLPYEN, SLPYPD, MCLK, inDATA, PwrDwn, Enable
);
  input Reset;
  input SLPYEN;
  input SLPYPD;
  input MCLK;
  input [7 : 0] inDATA;
  output [7 : 0] PwrDwn;
  output [7 : 0] Enable;
  wire en_3__n0000;
  wire en_1__n0000;
  wire en_7__n0003;
  wire en_2__n0000;
  wire en_0__n0000;
  wire en_5__n0000;
  wire en_4__n0000;
  wire en_6__n0000;
  wire en_7__n0002;
  wire pd_0__n0002;
  wire N5001;
  wire en_7__n0000;
  wire en_0__n00001;
  wire pd_0__n00021;
  wire pd_0__n00022;
  wire pd_0__n00023;
  wire en_7__n00021;
  wire en_7__n00022;
  wire en_7__n00023;
  wire en_7__n00001;
  wire en_6__n00001;
  wire en_5__n00001;
  wire en_1__n00001;
  wire en_4__n00001;
  wire en_2__n00001;
  wire en_3__n00001;
  AND2 en_0__n00002 (
    .I0(inDATA[0]),
    .I1(en_0__n00001),
    .O(en_0__n0000)
  );
  INV pd_0__n00024 (
    .I(pd_0__n00023),
    .O(pd_0__n0002)
  );
  FDCE en_7 (
    .D(en_7__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[7])
  );
  FDCE en_6 (
    .D(en_6__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[6])
  );
  FDCE en_0 (
    .D(en_0__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[0])
  );
  FDCE en_1 (
    .D(en_1__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[1])
  );
  FDCE en_2 (
    .D(en_2__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[2])
  );
  FDCE en_3 (
    .D(en_3__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[3])
  );
  FDCE en_4 (
    .D(en_4__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[4])
  );
  FDCE en_5 (
    .D(en_5__n0000),
    .CE(en_7__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(Enable[5])
  );
  INV en_7__n00031 (
    .I(MCLK),
    .O(en_7__n0003)
  );
  INV en_7__n00024 (
    .I(en_7__n00023),
    .O(en_7__n0002)
  );
  AND2 en_7__n00002 (
    .I0(inDATA[7]),
    .I1(en_7__n00001),
    .O(en_7__n0000)
  );
  GND XST_GND (
    .G(N5001)
  );
  FDCE pd_5 (
    .D(en_5__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[5])
  );
  FDCE pd_3 (
    .D(en_3__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[3])
  );
  AND2 en_6__n00002 (
    .I0(inDATA[6]),
    .I1(en_6__n00001),
    .O(en_6__n0000)
  );
  FDCE pd_7 (
    .D(en_7__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[7])
  );
  FDCE pd_2 (
    .D(en_2__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[2])
  );
  AND2 en_5__n00002 (
    .I0(inDATA[5]),
    .I1(en_5__n00001),
    .O(en_5__n0000)
  );
  AND2 en_1__n00002 (
    .I0(inDATA[1]),
    .I1(en_1__n00001),
    .O(en_1__n0000)
  );
  FDCE pd_1 (
    .D(en_1__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[1])
  );
  AND2 en_4__n00002 (
    .I0(inDATA[4]),
    .I1(en_4__n00001),
    .O(en_4__n0000)
  );
  AND2 en_2__n00002 (
    .I0(inDATA[2]),
    .I1(en_2__n00001),
    .O(en_2__n0000)
  );
  FDCE pd_0 (
    .D(en_0__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[0])
  );
  AND2 en_3__n00002 (
    .I0(inDATA[3]),
    .I1(en_3__n00001),
    .O(en_3__n0000)
  );
  FDCE pd_4 (
    .D(en_4__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[4])
  );
  FDCE pd_6 (
    .D(en_6__n0000),
    .CE(pd_0__n0002),
    .CLR(N5001),
    .C(en_7__n0003),
    .Q(PwrDwn[6])
  );
  INV en_0__n00001_107 (
    .I(Reset),
    .O(en_0__n00001)
  );
  INV pd_0__n00021_108 (
    .I(SLPYPD),
    .O(pd_0__n00021)
  );
  INV pd_0__n00022_109 (
    .I(Reset),
    .O(pd_0__n00022)
  );
  AND2 pd_0__n00023_110 (
    .I0(pd_0__n00021),
    .I1(pd_0__n00022),
    .O(pd_0__n00023)
  );
  INV en_7__n00021_111 (
    .I(SLPYEN),
    .O(en_7__n00021)
  );
  INV en_7__n00022_112 (
    .I(Reset),
    .O(en_7__n00022)
  );
  AND2 en_7__n00023_113 (
    .I0(en_7__n00021),
    .I1(en_7__n00022),
    .O(en_7__n00023)
  );
  INV en_7__n00001_114 (
    .I(Reset),
    .O(en_7__n00001)
  );
  INV en_6__n00001_115 (
    .I(Reset),
    .O(en_6__n00001)
  );
  INV en_5__n00001_116 (
    .I(Reset),
    .O(en_5__n00001)
  );
  INV en_1__n00001_117 (
    .I(Reset),
    .O(en_1__n00001)
  );
  INV en_4__n00001_118 (
    .I(Reset),
    .O(en_4__n00001)
  );
  INV en_2__n00001_119 (
    .I(Reset),
    .O(en_2__n00001)
  );
  INV en_3__n00001_120 (
    .I(Reset),
    .O(en_3__n00001)
  );
endmodule

module GalvRelay (
  Reset, SLPYLP, MCLK, SLPYCON, LOOPcon0, LOOPcon1, LOOPcon2, CONmodem, LOOPmodem, CONextr, CONcon0, CONcon1, CONcon2, LOOPextr, inDATA
);
  input Reset;
  input SLPYLP;
  input MCLK;
  input SLPYCON;
  output LOOPcon0;
  output LOOPcon1;
  output LOOPcon2;
  output CONmodem;
  output LOOPmodem;
  output CONextr;
  output CONcon0;
  output CONcon1;
  output CONcon2;
  output LOOPextr;
  input [7 : 0] inDATA;
  wire loop_4__n0002;
  wire loop_2__n0000;
  wire N4889;
  wire loop_4__n0003;
  wire loop_0__n0000;
  wire loop_3__n0000;
  wire connect_0__n0002;
  wire loop_4__n0000;
  wire loop_1__n0000;
  wire loop_0__n00001;
  wire connect_0__n00021;
  wire connect_0__n00022;
  wire connect_0__n00023;
  wire loop_4__n00021;
  wire loop_4__n00022;
  wire loop_4__n00023;
  wire loop_4__n00001;
  wire loop_1__n00001;
  wire loop_3__n00001;
  wire loop_2__n00001;
  AND2 loop_0__n00002 (
    .I0(inDATA[0]),
    .I1(loop_0__n00001),
    .O(loop_0__n0000)
  );
  INV connect_0__n00024 (
    .I(connect_0__n00023),
    .O(connect_0__n0002)
  );
  FDCE loop_4 (
    .D(loop_4__n0000),
    .CE(loop_4__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(LOOPmodem)
  );
  FDCE loop_3 (
    .D(loop_3__n0000),
    .CE(loop_4__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(LOOPextr)
  );
  FDCE loop_0 (
    .D(loop_0__n0000),
    .CE(loop_4__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(LOOPcon0)
  );
  FDCE loop_1 (
    .D(loop_1__n0000),
    .CE(loop_4__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(LOOPcon1)
  );
  FDCE loop_2 (
    .D(loop_2__n0000),
    .CE(loop_4__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(LOOPcon2)
  );
  INV loop_4__n00031 (
    .I(MCLK),
    .O(loop_4__n0003)
  );
  INV loop_4__n00024 (
    .I(loop_4__n00023),
    .O(loop_4__n0002)
  );
  AND2 loop_4__n00002 (
    .I0(inDATA[7]),
    .I1(loop_4__n00001),
    .O(loop_4__n0000)
  );
  GND XST_GND (
    .G(N4889)
  );
  AND2 loop_1__n00002 (
    .I0(inDATA[1]),
    .I1(loop_1__n00001),
    .O(loop_1__n0000)
  );
  FDCE connect_0 (
    .D(loop_0__n0000),
    .CE(connect_0__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(CONcon0)
  );
  AND2 loop_3__n00002 (
    .I0(inDATA[6]),
    .I1(loop_3__n00001),
    .O(loop_3__n0000)
  );
  FDCE connect_1 (
    .D(loop_1__n0000),
    .CE(connect_0__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(CONcon1)
  );
  FDCE connect_3 (
    .D(loop_3__n0000),
    .CE(connect_0__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(CONextr)
  );
  AND2 loop_2__n00002 (
    .I0(inDATA[2]),
    .I1(loop_2__n00001),
    .O(loop_2__n0000)
  );
  FDCE connect_4 (
    .D(loop_4__n0000),
    .CE(connect_0__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(CONmodem)
  );
  FDCE connect_2 (
    .D(loop_2__n0000),
    .CE(connect_0__n0002),
    .CLR(N4889),
    .C(loop_4__n0003),
    .Q(CONcon2)
  );
  INV loop_0__n00001_147 (
    .I(Reset),
    .O(loop_0__n00001)
  );
  INV connect_0__n00021_148 (
    .I(SLPYCON),
    .O(connect_0__n00021)
  );
  INV connect_0__n00022_149 (
    .I(Reset),
    .O(connect_0__n00022)
  );
  AND2 connect_0__n00023_150 (
    .I0(connect_0__n00021),
    .I1(connect_0__n00022),
    .O(connect_0__n00023)
  );
  INV loop_4__n00021_151 (
    .I(SLPYLP),
    .O(loop_4__n00021)
  );
  INV loop_4__n00022_152 (
    .I(Reset),
    .O(loop_4__n00022)
  );
  AND2 loop_4__n00023_153 (
    .I0(loop_4__n00021),
    .I1(loop_4__n00022),
    .O(loop_4__n00023)
  );
  INV loop_4__n00001_154 (
    .I(Reset),
    .O(loop_4__n00001)
  );
  INV loop_1__n00001_155 (
    .I(Reset),
    .O(loop_1__n00001)
  );
  INV loop_3__n00001_156 (
    .I(Reset),
    .O(loop_3__n00001)
  );
  INV loop_2__n00001_157 (
    .I(Reset),
    .O(loop_2__n00001)
  );
endmodule

module AddDecode (
  AS, RD, WR, Wslct0, Wslct2, Wslct3, Wslct4, Wslct5, Wslct6, Wslct7, Rslct0, Wslct8, Rslct1, Rslct6, ADDR
);
  input AS;
  input RD;
  input WR;
  output Wslct0;
  output Wslct2;
  output Wslct3;
  output Wslct4;
  output Wslct5;
  output Wslct6;
  output Wslct7;
  output Rslct0;
  output Wslct8;
  output Rslct1;
  output Rslct6;
  input [7 : 0] ADDR;
  wire SF7730;
  wire SF7734;
  wire SF7749;
  wire SF7745;
  wire SF7741;
  wire SF7739;
  wire SF77301;
  wire SF77302;
  wire SF77303;
  wire SF77304;
  wire Select_1_Select;
  wire Select_1_Select1;
  wire Select_1_Select2;
  wire Select_1_Select3;
  wire SF77411;
  wire SF77412;
  wire SF77413;
  wire SF77491;
  wire SF77492;
  wire SF77493;
  wire SF77494;
  wire Select_10_Select;
  wire Select_10_Select1;
  wire Select_10_Select2;
  wire Select_10_Select3;
  wire Select_7_Select;
  wire Select_7_Select1;
  wire Select_7_Select2;
  wire SF77451;
  wire SF77452;
  wire SF77453;
  wire SF77454;
  wire Select_9_Select;
  wire Select_9_Select1;
  wire Select_9_Select2;
  wire Select_8_Select;
  wire Select_8_Select1;
  wire Select_8_Select2;
  wire Select_8_Select3;
  wire SF77391;
  wire SF77392;
  wire SF77393;
  wire Select_2_Select;
  wire Select_2_Select1;
  wire Select_2_Select2;
  wire Select_11_Select;
  wire Select_11_Select1;
  wire Select_11_Select2;
  wire Select_11_Select3;
  wire Select_6_Select;
  wire Select_6_Select1;
  wire Select_6_Select2;
  wire Select_6_Select3;
  wire SF77341;
  wire SF77342;
  wire SF77343;
  wire Select_3_Select;
  wire Select_3_Select1;
  wire Select_3_Select2;
  wire Select_3_Select3;
  wire Select_4_Select;
  wire Select_4_Select1;
  wire Select_4_Select2;
  wire Select_4_Select3;
  wire Select_4_Select4;
  wire Select_4_Select5;
  wire Select_4_Select6;
  wire Select_5_Select;
  wire Select_5_Select1;
  wire Select_5_Select2;
  AND4 SF77305 (
    .I0(SF77301),
    .I1(SF77302),
    .I2(SF77303),
    .I3(SF77304),
    .O(SF7730)
  );
  AND2 Select_1_Select5 (
    .I0(Select_1_Select),
    .I1(Select_1_Select3),
    .O(Rslct6)
  );
  AND4 SF77414 (
    .I0(SF7739),
    .I1(SF77411),
    .I2(SF77412),
    .I3(SF77413),
    .O(SF7741)
  );
  AND2 SF77495 (
    .I0(SF77491),
    .I1(SF77494),
    .O(SF7749)
  );
  AND2 Select_10_Select5 (
    .I0(Select_10_Select),
    .I1(Select_10_Select3),
    .O(Wslct2)
  );
  AND2 Select_7_Select4 (
    .I0(Select_7_Select),
    .I1(Select_7_Select2),
    .O(Wslct5)
  );
  AND2 SF77455 (
    .I0(SF77451),
    .I1(SF77454),
    .O(SF7745)
  );
  AND2 Select_9_Select4 (
    .I0(Select_9_Select),
    .I1(Select_9_Select2),
    .O(Wslct3)
  );
  AND2 Select_8_Select5 (
    .I0(Select_8_Select),
    .I1(Select_8_Select3),
    .O(Wslct4)
  );
  AND4 SF77394 (
    .I0(ADDR[1]),
    .I1(SF77391),
    .I2(SF77392),
    .I3(SF77393),
    .O(SF7739)
  );
  AND2 Select_2_Select4 (
    .I0(Select_2_Select),
    .I1(Select_2_Select2),
    .O(Rslct1)
  );
  AND2 Select_11_Select5 (
    .I0(Select_11_Select),
    .I1(Select_11_Select3),
    .O(Wslct0)
  );
  AND2 Select_6_Select5 (
    .I0(Select_6_Select),
    .I1(Select_6_Select3),
    .O(Wslct6)
  );
  AND4 SF77344 (
    .I0(SF7730),
    .I1(SF77341),
    .I2(SF77342),
    .I3(SF77343),
    .O(SF7734)
  );
  AND2 Select_3_Select5 (
    .I0(Select_3_Select),
    .I1(Select_3_Select3),
    .O(Rslct0)
  );
  AND3 Select_4_Select8 (
    .I0(Select_4_Select5),
    .I1(Select_4_Select),
    .I2(Select_4_Select6),
    .O(Wslct8)
  );
  AND2 Select_5_Select4 (
    .I0(Select_5_Select),
    .I1(Select_5_Select2),
    .O(Wslct7)
  );
  INV SF77301_235 (
    .I(ADDR[5]),
    .O(SF77301)
  );
  INV SF77302_236 (
    .I(ADDR[1]),
    .O(SF77302)
  );
  INV SF77303_237 (
    .I(ADDR[7]),
    .O(SF77303)
  );
  INV SF77304_238 (
    .I(ADDR[6]),
    .O(SF77304)
  );
  AND2 Select_1_Select1_239 (
    .I0(WR),
    .I1(SF7749),
    .O(Select_1_Select)
  );
  INV Select_1_Select2_240 (
    .I(RD),
    .O(Select_1_Select1)
  );
  INV Select_1_Select3_241 (
    .I(ADDR[0]),
    .O(Select_1_Select2)
  );
  AND2 Select_1_Select4 (
    .I0(Select_1_Select1),
    .I1(Select_1_Select2),
    .O(Select_1_Select3)
  );
  INV SF77411_242 (
    .I(ADDR[4]),
    .O(SF77411)
  );
  INV SF77412_243 (
    .I(ADDR[3]),
    .O(SF77412)
  );
  INV SF77413_244 (
    .I(ADDR[2]),
    .O(SF77413)
  );
  AND2 SF77491_245 (
    .I0(ADDR[2]),
    .I1(SF7739),
    .O(SF77491)
  );
  INV SF77492_246 (
    .I(ADDR[4]),
    .O(SF77492)
  );
  INV SF77493_247 (
    .I(ADDR[3]),
    .O(SF77493)
  );
  AND2 SF77494_248 (
    .I0(SF77492),
    .I1(SF77493),
    .O(SF77494)
  );
  AND2 Select_10_Select1_249 (
    .I0(RD),
    .I1(SF7741),
    .O(Select_10_Select)
  );
  INV Select_10_Select2_250 (
    .I(WR),
    .O(Select_10_Select1)
  );
  INV Select_10_Select3_251 (
    .I(ADDR[0]),
    .O(Select_10_Select2)
  );
  AND2 Select_10_Select4 (
    .I0(Select_10_Select1),
    .I1(Select_10_Select2),
    .O(Select_10_Select3)
  );
  AND2 Select_7_Select1_252 (
    .I0(RD),
    .I1(ADDR[0]),
    .O(Select_7_Select)
  );
  INV Select_7_Select2_253 (
    .I(WR),
    .O(Select_7_Select1)
  );
  AND2 Select_7_Select3 (
    .I0(SF7745),
    .I1(Select_7_Select1),
    .O(Select_7_Select2)
  );
  AND2 SF77451_254 (
    .I0(ADDR[2]),
    .I1(SF7730),
    .O(SF77451)
  );
  INV SF77452_255 (
    .I(ADDR[4]),
    .O(SF77452)
  );
  INV SF77453_256 (
    .I(ADDR[3]),
    .O(SF77453)
  );
  AND2 SF77454_257 (
    .I0(SF77452),
    .I1(SF77453),
    .O(SF77454)
  );
  AND2 Select_9_Select1_258 (
    .I0(RD),
    .I1(ADDR[0]),
    .O(Select_9_Select)
  );
  INV Select_9_Select2_259 (
    .I(WR),
    .O(Select_9_Select1)
  );
  AND2 Select_9_Select3 (
    .I0(SF7741),
    .I1(Select_9_Select1),
    .O(Select_9_Select2)
  );
  AND2 Select_8_Select1_260 (
    .I0(RD),
    .I1(SF7745),
    .O(Select_8_Select)
  );
  INV Select_8_Select2_261 (
    .I(WR),
    .O(Select_8_Select1)
  );
  INV Select_8_Select3_262 (
    .I(ADDR[0]),
    .O(Select_8_Select2)
  );
  AND2 Select_8_Select4 (
    .I0(Select_8_Select1),
    .I1(Select_8_Select2),
    .O(Select_8_Select3)
  );
  INV SF77391_263 (
    .I(ADDR[5]),
    .O(SF77391)
  );
  INV SF77392_264 (
    .I(ADDR[7]),
    .O(SF77392)
  );
  INV SF77393_265 (
    .I(ADDR[6]),
    .O(SF77393)
  );
  AND2 Select_2_Select1_266 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_2_Select)
  );
  INV Select_2_Select2_267 (
    .I(RD),
    .O(Select_2_Select1)
  );
  AND2 Select_2_Select3 (
    .I0(SF7734),
    .I1(Select_2_Select1),
    .O(Select_2_Select2)
  );
  AND2 Select_11_Select1_268 (
    .I0(RD),
    .I1(SF7734),
    .O(Select_11_Select)
  );
  INV Select_11_Select2_269 (
    .I(WR),
    .O(Select_11_Select1)
  );
  INV Select_11_Select3_270 (
    .I(ADDR[0]),
    .O(Select_11_Select2)
  );
  AND2 Select_11_Select4 (
    .I0(Select_11_Select1),
    .I1(Select_11_Select2),
    .O(Select_11_Select3)
  );
  AND2 Select_6_Select1_271 (
    .I0(RD),
    .I1(SF7749),
    .O(Select_6_Select)
  );
  INV Select_6_Select2_272 (
    .I(WR),
    .O(Select_6_Select1)
  );
  INV Select_6_Select3_273 (
    .I(ADDR[0]),
    .O(Select_6_Select2)
  );
  AND2 Select_6_Select4 (
    .I0(Select_6_Select1),
    .I1(Select_6_Select2),
    .O(Select_6_Select3)
  );
  INV SF77341_274 (
    .I(ADDR[4]),
    .O(SF77341)
  );
  INV SF77342_275 (
    .I(ADDR[3]),
    .O(SF77342)
  );
  INV SF77343_276 (
    .I(ADDR[2]),
    .O(SF77343)
  );
  AND2 Select_3_Select1_277 (
    .I0(WR),
    .I1(SF7734),
    .O(Select_3_Select)
  );
  INV Select_3_Select2_278 (
    .I(RD),
    .O(Select_3_Select1)
  );
  INV Select_3_Select3_279 (
    .I(ADDR[0]),
    .O(Select_3_Select2)
  );
  AND2 Select_3_Select4 (
    .I0(Select_3_Select1),
    .I1(Select_3_Select2),
    .O(Select_3_Select3)
  );
  AND2 Select_4_Select1_280 (
    .I0(RD),
    .I1(SF7730),
    .O(Select_4_Select)
  );
  INV Select_4_Select2_281 (
    .I(WR),
    .O(Select_4_Select1)
  );
  INV Select_4_Select3_282 (
    .I(ADDR[0]),
    .O(Select_4_Select2)
  );
  INV Select_4_Select4_283 (
    .I(ADDR[4]),
    .O(Select_4_Select3)
  );
  INV Select_4_Select5_284 (
    .I(ADDR[2]),
    .O(Select_4_Select4)
  );
  AND2 Select_4_Select6_285 (
    .I0(ADDR[3]),
    .I1(Select_4_Select1),
    .O(Select_4_Select5)
  );
  AND3 Select_4_Select7 (
    .I0(Select_4_Select3),
    .I1(Select_4_Select2),
    .I2(Select_4_Select4),
    .O(Select_4_Select6)
  );
  AND2 Select_5_Select1_286 (
    .I0(RD),
    .I1(ADDR[0]),
    .O(Select_5_Select)
  );
  INV Select_5_Select2_287 (
    .I(WR),
    .O(Select_5_Select1)
  );
  AND2 Select_5_Select3 (
    .I0(SF7749),
    .I1(Select_5_Select1),
    .O(Select_5_Select2)
  );
endmodule

module SleepyPLD (
  AS, AM2Status, IOWR, AM1Status, AM0Status, SystemStatus, ExternalStatus, ModemStatus, RD, Bus_Select, AEN, WR, SMCLK, CameraStatus, SCLreset, 
CPLD_Reset, PC104_RESET, SCLinc, UINT, IORD, SCL, IRQ, UIOW, ModemEN, AM2EN, LOOPcon0, LOOPcon1, LOOPcon2, UCS, CONmodem, CameraEN, LOOPmodem, 
ExternalEN, ENDXFR, CONextr, IOCHCHK, DwarfEN, AM0EN, CONcon0, CONcon1, CONcon2, LOOPextr, SystemEN, AM1EN, INT, SYSPWR, UIOR, SA, AD, SD, UD, UAD, EN
, PD
);
  input AS;
  input AM2Status;
  input IOWR;
  input AM1Status;
  input AM0Status;
  input SystemStatus;
  input ExternalStatus;
  input ModemStatus;
  input RD;
  input Bus_Select;
  input AEN;
  input WR;
  input SMCLK;
  input CameraStatus;
  input SCLreset;
  input CPLD_Reset;
  input PC104_RESET;
  input SCLinc;
  input UINT;
  input IORD;
  inout SCL;
  output IRQ;
  output UIOW;
  output ModemEN;
  output AM2EN;
  output LOOPcon0;
  output LOOPcon1;
  output LOOPcon2;
  output UCS;
  output CONmodem;
  output CameraEN;
  output LOOPmodem;
  output ExternalEN;
  output ENDXFR;
  output CONextr;
  output IOCHCHK;
  output DwarfEN;
  output AM0EN;
  output CONcon0;
  output CONcon1;
  output CONcon2;
  output LOOPextr;
  output SystemEN;
  output AM1EN;
  output INT;
  output SYSPWR;
  output UIOR;
  input [15 : 0] SA;
  inout [7 : 0] AD;
  inout [7 : 0] SD;
  inout [7 : 0] UD;
  output [7 : 0] UAD;
  output [7 : 0] EN;
  output [7 : 0] PD;
  wire IRQ_OBUF;
  wire UIOW_OBUF;
  wire ModemEN_OBUF;
  wire AM2EN_OBUF;
  wire U2_ADDR_reg_0__n0000;
  wire LOOPcon0_OBUF;
  wire LOOPcon1_OBUF;
  wire LOOPcon2_OBUF;
  wire AS_IBUF;
  wire AM2Status_IBUF;
  wire UCS_OBUF;
  wire IOWR_IBUF;
  wire AM1Status_IBUF;
  wire AM0Status_IBUF;
  wire CONmodem_OBUF;
  wire CameraEN_OBUF;
  wire SystemStatus_IBUF;
  wire U2_ADDR_reg_0__n0002;
  wire ExternalStatus_IBUF;
  wire ModemStatus_IBUF;
  wire LOOPmodem_OBUF;
  wire ExternalEN_OBUF;
  wire RD_IBUF;
  wire Bus_Select_IBUF;
  wire AEN_IBUF;
  wire CONextr_OBUF;
  wire WR_IBUF;
  wire SMCLK_IBUF;
  wire CameraStatus_IBUF;
  wire DwarfEN_OBUF;
  wire AM0EN_OBUF;
  wire SCLreset_IBUF;
  wire CPLD_Reset_IBUF;
  wire NET2480;
  wire CONcon0_OBUF;
  wire CONcon1_OBUF;
  wire CONcon2_OBUF;
  wire LOOPextr_OBUF;
  wire SystemEN_OBUF;
  wire AM1EN_OBUF;
  wire INT_OBUF;
  wire SYSPWR_OBUF;
  wire SCLinc_IBUF;
  wire UINT_IBUF;
  wire UIOR_OBUF;
  wire IORD_IBUF;
  wire U3__n0032;
  wire NET2533;
  wire NET1432;
  wire NET1440;
  wire NET1448;
  wire NET1456;
  wire NET1523;
  wire NET1474;
  wire Reset;
  wire NET1535;
  wire NET1764;
  wire NET3560;
  wire U7_U3__n0042;
  wire NET4340;
  wire UAD_7_OBUF;
  wire UAD_6_OBUF;
  wire UAD_5_OBUF;
  wire UAD_4_OBUF;
  wire UAD_3_OBUF;
  wire UAD_2_OBUF;
  wire UAD_1_OBUF;
  wire UAD_0_OBUF;
  wire EN_7_OBUF;
  wire EN_6_OBUF;
  wire EN_5_OBUF;
  wire EN_4_OBUF;
  wire EN_3_OBUF;
  wire EN_2_OBUF;
  wire EN_1_OBUF;
  wire EN_0_OBUF;
  wire PD_7_OBUF;
  wire PD_6_OBUF;
  wire PD_5_OBUF;
  wire PD_4_OBUF;
  wire PD_3_OBUF;
  wire PD_2_OBUF;
  wire PD_1_OBUF;
  wire PD_0_OBUF;
  wire SA_15_IBUF;
  wire SA_14_IBUF;
  wire SA_13_IBUF;
  wire SA_12_IBUF;
  wire SA_11_IBUF;
  wire SA_10_IBUF;
  wire SA_9_IBUF;
  wire SA_8_IBUF;
  wire SA_7_IBUF;
  wire SA_6_IBUF;
  wire SA_5_IBUF;
  wire SA_4_IBUF;
  wire SA_3_IBUF;
  wire SA_2_IBUF;
  wire SA_1_IBUF;
  wire SA_0_IBUF;
  wire IOCHCHK_OBUFE;
  wire UD_6_IOBUFE;
  wire N6204;
  wire U2_ADDR_reg_6__n0000;
  wire U2_ADDR_reg_7__n0000;
  wire U2_WRRDedge;
  wire U2__n0000;
  wire U2__n0003;
  wire U2__n0005;
  wire U7_U3_Maddsub__n0002__n0020;
  wire U2__n0006;
  wire UD_1_IOBUFE;
  wire UD_2_IOBUFE;
  wire U2__n0018;
  wire U7_U3_Maddsub__n0002__n0018;
  wire U2_Enable_AD;
  wire U2_ASedge;
  wire U2_AutoInc;
  wire U2_ADDR_reg_4__n0000;
  wire U2_ADDR_reg_3__n0000;
  wire U2_ADDR_reg_5__n0000;
  wire U7_U3_Maddsub__n0002__n0019;
  wire U2_ADDR_reg_2__n0000;
  wire U2_ADDR_reg_1__n0000;
  wire U3_Mcompar__n0011__n0009;
  wire U7_U3__n0041;
  wire U3_Mcompar__n0011__n0011;
  wire U7_ResetDetect;
  wire UD_7_IOBUFE;
  wire U3_Mcompar__n0011__n0014;
  wire U3_PC104reg_0__n0003;
  wire U3_Mcompar__n0011__n0006;
  wire U3_Mcompar__n0011__n0008;
  wire U3_PC104reg_6__n0000;
  wire U3_PC104reg_7__n0000;
  wire U3_PC104reg_7__n0002;
  wire UD_4_IOBUFE;
  wire U3_PC104reg_2__n0000;
  wire U3_PC104reg_1__n0000;
  wire UD_0_IOBUFE;
  wire U3_PC104reg_4__n0000;
  wire U3_PC104reg_3__n0000;
  wire UD_5_IOBUFE;
  wire U7_U3_Maddsub__n0002__n0017;
  wire U3__n0002;
  wire U3__n0003;
  wire U3_Mcompar__n0011__n0013;
  wire U3__n0028;
  wire U3_Mcompar__n0011__n0012;
  wire U3_PC104reg_0__n0000;
  wire U3_Mcompar__n0011__n0010;
  wire U7_SCLdetect;
  wire U3__n0015;
  wire U7_U3__n0006;
  wire UD_3_IOBUFE;
  wire U3_Mcompar__n0011__n0007;
  wire U3_PC104reg_5__n0000;
  wire U7_Incdetect;
  wire U2_ADDR_reg_1__n00001;
  wire U2_ADDR_reg_1__n00002;
  wire U2_ADDR_reg_1__n00003;
  wire U2_ADDR_reg_1__n00004;
  wire U2_ADDR_reg_1__n00005;
  wire U2_ADDR_reg_2__n00001;
  wire U2_ADDR_reg_2__n00002;
  wire U2_ADDR_reg_2__n00003;
  wire U2_ADDR_reg_2__n00004;
  wire U2_ADDR_reg_2__n00005;
  wire U2_ADDR_reg_3__n00001;
  wire U2_ADDR_reg_3__n00002;
  wire U2_ADDR_reg_3__n00003;
  wire U2_ADDR_reg_3__n00004;
  wire U2_ADDR_reg_3__n00005;
  wire U2_ADDR_reg_4__n00001;
  wire U2_ADDR_reg_4__n00002;
  wire U2_ADDR_reg_4__n00003;
  wire U2_ADDR_reg_4__n00004;
  wire U2_ADDR_reg_4__n00005;
  wire U2_ADDR_reg_5__n00001;
  wire U2_ADDR_reg_5__n00002;
  wire U2_ADDR_reg_5__n00003;
  wire U2_ADDR_reg_5__n00004;
  wire U2_ADDR_reg_5__n00005;
  wire U2_ADDR_reg_6__n00001;
  wire U2_ADDR_reg_6__n00002;
  wire U2_ADDR_reg_6__n00003;
  wire U2_ADDR_reg_6__n00004;
  wire U2_ADDR_reg_6__n00005;
  wire U2_ADDR_reg_7__n00001;
  wire U2_ADDR_reg_7__n00002;
  wire U2_ADDR_reg_7__n00003;
  wire U2_ADDR_reg_7__n00004;
  wire U2_ADDR_reg_7__n00005;
  wire U7_U3__n00421;
  wire U7_U3__n00422;
  wire U7_U3__n00423;
  wire U7_U3__n00424;
  wire U7_U3__n00425;
  wire U7_U3__n00426;
  wire U7_U3__n00427;
  wire U2_ADDR_reg_0__n00021;
  wire U2_ADDR_reg_0__n00022;
  wire U2_ADDR_reg_0__n00023;
  wire U2_ADDR_reg_0__n00024;
  wire U2_ADDR_reg_0__n00025;
  wire U2_ADDR_reg_0__n00026;
  wire U2_ADDR_reg_0__n00027;
  wire U2_ADDR_reg_0__n00028;
  wire U7_U3__n0000_2_1;
  wire U7_U3__n0000_2_2;
  wire U7_U3__n0000_2_3;
  wire U7_U3__n0000_2_4;
  wire U7_U3__n0000_2_5;
  wire U7_U3__n0000_2_6;
  wire U7_U3__n0000_2_7;
  wire U7_U3__n0000_2_8;
  wire U7_U3__n0000_2_9;
  wire U7_U3__n0000_2_10;
  wire U2_ADDR_reg_0__n00001;
  wire U2_ADDR_reg_0__n00002;
  wire U2_ADDR_reg_0__n00003;
  wire U2_ADDR_reg_0__n00004;
  wire U2_ADDR_reg_0__n00005;
  wire U7_U3__n0000_0_1;
  wire U7_U3__n0000_0_2;
  wire U7_U3__n0000_0_3;
  wire U7_U3__n0000_0_4;
  wire U7_U3__n0000_0_5;
  wire U7_U3__n0000_0_6;
  wire U7_U3__n0000_0_7;
  wire U7_U3__n0000_0_8;
  wire U7_U3__n0000_0_9;
  wire U7_U3__n0000_0_10;
  wire U7_U3__n0000_0_11;
  wire U7_U3__n0000_0_12;
  wire U7_U3__n0000_0_13;
  wire U7_U3__n0000_0_14;
  wire U7_U3__n0000_0_15;
  wire U7_U3__n0000_0_16;
  wire U2__n00031;
  wire U2__n00051;
  wire U2__n00052;
  wire U2__n00053;
  wire U2_Enable_AD1;
  wire U7_U3_Maddsub__n0002__n0002;
  wire U7_U3_Maddsub__n0002__n00021;
  wire U7_U3_Maddsub__n0002__n00022;
  wire U7_U3_Maddsub__n0002__n00023;
  wire U7_U3_Maddsub__n0002__n00024;
  wire U7_U3_Maddsub__n0002__n00025;
  wire U7_U3_Maddsub__n0002__n0001;
  wire U7_U3_Maddsub__n0002__n00011;
  wire U7_U3_Maddsub__n0002__n00012;
  wire U7_U3_Maddsub__n0002__n00013;
  wire U7_U3_Maddsub__n0002__n00014;
  wire U7_U3_Maddsub__n0002__n00015;
  wire U7_U3__n00411;
  wire U7_U3__n00412;
  wire U7_U3__n00413;
  wire U7_U3__n00414;
  wire U7_U3__n00415;
  wire U7_U3__n00416;
  wire U7_U3_Maddsub__n0002__n0003;
  wire U7_U3_Maddsub__n0002__n00031;
  wire U7_U3_Maddsub__n0002__n00032;
  wire U7_U3_Maddsub__n0002__n00033;
  wire U7_U3_Maddsub__n0002__n00034;
  wire U7_U3_Maddsub__n0002__n00035;
  wire U7_U3__n0000_5_1;
  wire U7_U3__n0000_5_2;
  wire U7_U3__n0000_5_3;
  wire U7_U3__n0000_5_4;
  wire U7_U3__n0000_5_5;
  wire U7_U3__n0000_5_6;
  wire U7_U3__n0000_5_7;
  wire U7_U3__n0000_5_8;
  wire U7_U3__n0000_5_9;
  wire U7_U3__n00061;
  wire U7_U3__n00062;
  wire U7_U3__n0000_4_1;
  wire U7_U3__n0000_4_2;
  wire U7_U3__n0000_4_3;
  wire U7_U3__n0000_4_4;
  wire U7_U3__n0000_4_5;
  wire U7_U3__n0000_4_6;
  wire U7_U3__n0000_4_7;
  wire U7_U3__n0000_4_8;
  wire U7_U3__n0000_4_9;
  wire U3__n0061;
  wire U3__n00611;
  wire U3__n00612;
  wire U3__n00613;
  wire U3__n0058;
  wire U3__n00581;
  wire U3__n00582;
  wire U3__n0055;
  wire U3__n00551;
  wire U3__n00552;
  wire U3__n0052;
  wire U3__n00521;
  wire U3__n00522;
  wire U3__n0049;
  wire U3__n00491;
  wire U3__n00492;
  wire U3__n0046;
  wire U3__n00461;
  wire U3__n00462;
  wire U3__n0040;
  wire U3__n00401;
  wire U3__n00402;
  wire U3__n00281;
  wire U3__n00282;
  wire U7_U3_Maddsub__n0002__n0004;
  wire U7_U3_Maddsub__n0002__n00041;
  wire U7_U3_Maddsub__n0002__n00042;
  wire U7_U3_Maddsub__n0002__n00043;
  wire U7_U3__n0000_3_1;
  wire U7_U3__n0000_3_2;
  wire U7_U3__n0000_3_3;
  wire U7_U3__n0000_3_4;
  wire U7_U3__n0000_3_5;
  wire U7_U3__n0000_3_6;
  wire U7_U3__n0000_3_7;
  wire U7_U3__n0000_3_8;
  wire U7_U3__n0000_3_9;
  wire U7_U3__n0000_3_10;
  wire U3__n00151;
  wire U3__n00152;
  wire U3__n00153;
  wire U3__n00154;
  wire U3__n00155;
  wire U3__n00156;
  wire U3__n00157;
  wire U7_U3_Maddsub__n0002__n0000;
  wire U7_U3_Maddsub__n0002__n00001;
  wire U7_U3_Maddsub__n0002__n00002;
  wire U7_U3_Maddsub__n0002__n00003;
  wire U7_U3_Maddsub__n0002__n00004;
  wire U7_U3_Maddsub__n0002__n00005;
  wire U3__n0043;
  wire U3__n00431;
  wire U3__n00432;
  wire U3__n0004_7_1;
  wire U3__n0004_7_2;
  wire U3__n0004_7_3;
  wire U3__n0004_7_4;
  wire U3__n0004_7_5;
  wire U3_Mmux_UIOR_Result;
  wire U3_Mmux_UIOR_Result1;
  wire U3_Mmux_UIOR_Result2;
  wire U3_Mmux_UIOR_Result3;
  wire U3_Mmux_UIOW_Result;
  wire U3_Mmux_UIOW_Result1;
  wire U3_Mmux_UIOW_Result2;
  wire U3_Mmux_UIOW_Result3;
  wire U3__n0004_0_1;
  wire U3__n0004_0_2;
  wire U3__n0004_0_3;
  wire U3__n0004_0_4;
  wire U3__n0004_0_5;
  wire U3__n0004_1_1;
  wire U3__n0004_1_2;
  wire U3__n0004_1_3;
  wire U3__n0004_1_4;
  wire U3__n0004_1_5;
  wire U3__n0004_2_1;
  wire U3__n0004_2_2;
  wire U3__n0004_2_3;
  wire U3__n0004_2_4;
  wire U3__n0004_2_5;
  wire U3__n0004_3_1;
  wire U3__n0004_3_2;
  wire U3__n0004_3_3;
  wire U3__n0004_3_4;
  wire U3__n0004_3_5;
  wire U3__n0004_4_1;
  wire U3__n0004_4_2;
  wire U3__n0004_4_3;
  wire U3__n0004_4_4;
  wire U3__n0004_4_5;
  wire U3__n0004_5_1;
  wire U3__n0004_5_2;
  wire U3__n0004_5_3;
  wire U3__n0004_5_4;
  wire U3__n0004_5_5;
  wire U3__n0004_6_1;
  wire U3__n0004_6_2;
  wire U3__n0004_6_3;
  wire U3__n0004_6_4;
  wire U3__n0004_6_5;
  wire U3__n00031;
  wire U3__n00032;
  wire U3__n00021;
  wire U3__n00022;
  wire U3__n00023;
  wire U3__n00024;
  wire U3__n0001;
  wire U7_U3__n0000_1_1;
  wire U7_U3__n0000_1_2;
  wire U7_U3__n0000_1_3;
  wire U7_U3__n0000_1_4;
  wire U7_U3__n0000_1_5;
  wire U7_U3__n0000_1_6;
  wire U7_U3__n0000_1_7;
  wire U7_U3__n0000_1_8;
  wire U7_U3__n0000_1_9;
  wire U7_U3__n0000_1_10;
  wire U7_U3__n0000_1_11;
  wire U7_U3__n0000_1_12;
  wire U7_U3__n0005;
  wire U7_U3__n00051;
  wire U7_U3__n00052;
  wire U7_U3__n00053;
  wire U7_U3__n00054;
  wire U7_U3__n00055;
  wire U3_Mcompar__n0011__n00141;
  wire U3_Mcompar__n0011__n00142;
  wire U3_Mcompar__n0011__n00143;
  wire U3_Mcompar__n0011__n00144;
  wire U3_Mcompar__n0011__n00145;
  wire U3_Mcompar__n0011__n00146;
  wire U3_Mcompar__n0011__n00147;
  wire U3_Mcompar__n0011__n00148;
  wire U3_PC104reg_7__n00021;
  wire U3_PC104reg_7__n00022;
  wire N8852;
  wire N8854;
  wire N8856;
  wire N8858;
  wire N8860;
  wire N8862;
  wire N8864;
  wire N8866;
  wire N8868;
  wire N8870;
  wire N8872;
  wire SD_0_IOBUFE;
  wire SD_1_IOBUFE;
  wire SD_2_IOBUFE;
  wire SD_3_IOBUFE;
  wire SD_4_IOBUFE;
  wire SD_5_IOBUFE;
  wire SD_6_IOBUFE;
  wire SD_7_IOBUFE;
  wire N8890;
  wire N8892;
  wire N8894;
  wire N8896;
  wire N8898;
  wire N8900;
  wire [5 : 0] U7_U3__n0002;
  wire [0 : 0] U2_Madd__n0011__n0014;
  wire [0 : 0] U2_Madd__n0011__n0016;
  wire [7 : 0] U2_ADDR_reg;
  wire [7 : 0] outDATA;
  wire [5 : 0] U7_U3__n0000;
  wire [7 : 1] U2__n0011;
  wire [7 : 0] U3_PC104reg;
  wire [0 : 0] U3_Madd__n0000__n0005;
  wire [5 : 0] U7_U3_counterr;
  wire [1 : 0] U7_U3_Maddsub__n0002__n0028;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_5___n0002;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_2___n0002;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_1___n0002;
  wire [1 : 0] U7_U3_Maddsub__n0002__n0026;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_3___n0002;
  wire [1 : 0] U7_U3_Maddsub__n0002__n0030;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_4___n0002;
  wire [0 : 0] U2_Madd__n0011__n0008;
  wire [5 : 4] U7_U3__n0049;
  wire [3 : 1] U3__n0000;
  wire [0 : 0] U7_U3_Maddsub__n0002__n0032;
  wire [0 : 0] U7_U3_Madd__n0001__n0003;
  wire [0 : 0] U2_Madd__n0011__n0018;
  wire [0 : 0] U2_Madd__n0011__n0010;
  wire [0 : 0] U2_Madd__n0011__n0012;
  wire [1 : 0] U3_Madd__n0000__n0007;
  wire [3 : 3] U7_U3__n0003;
  wire [0 : 0] U7_U3_Maddsub__n0002__n0034;
  OBUFE IOCHCHK_OBUFE_808 (
    .E(IOCHCHK_OBUFE),
    .I(IOCHCHK_OBUFE),
    .O(IOCHCHK)
  );
  INV Reset1 (
    .I(CPLD_Reset_IBUF),
    .O(Reset)
  );
  AddDecode U1 (
    .AS(AS_IBUF),
    .RD(RD_IBUF),
    .WR(WR_IBUF),
    .Wslct0(NET2480),
    .Wslct2(NET1432),
    .Wslct3(NET1440),
    .Wslct4(NET1456),
    .Wslct5(NET1474),
    .Wslct6(NET1448),
    .Wslct7(NET3560),
    .Rslct0(NET1535),
    .Wslct8(NET4340),
    .Rslct1(NET2533),
    .Rslct6(NET1523),
    .ADDR({U2_ADDR_reg[7], U2_ADDR_reg[6], U2_ADDR_reg[5], U2_ADDR_reg[4], U2_ADDR_reg[3], U2_ADDR_reg[2], U2_ADDR_reg[1], U2_ADDR_reg[0]})
  );
  IOBUFE SCL_IOBUFE (
    .I(IOCHCHK_OBUFE),
    .E(NET1764),
    .O(N8892),
    .IO(SCL)
  );
  INV U3_PC104reg_0__n00031 (
    .I(SMCLK_IBUF),
    .O(U3_PC104reg_0__n0003)
  );
  GalvRelay U4 (
    .Reset(Reset),
    .SLPYLP(NET1440),
    .MCLK(SMCLK_IBUF),
    .SLPYCON(NET1432),
    .LOOPcon0(LOOPcon0_OBUF),
    .LOOPcon1(LOOPcon1_OBUF),
    .LOOPcon2(LOOPcon2_OBUF),
    .CONmodem(CONmodem_OBUF),
    .LOOPmodem(LOOPmodem_OBUF),
    .CONextr(CONextr_OBUF),
    .CONcon0(CONcon0_OBUF),
    .CONcon1(CONcon1_OBUF),
    .CONcon2(CONcon2_OBUF),
    .LOOPextr(LOOPextr_OBUF),
    .inDATA({N8856, N8854, N8852, N8900, N8898, N8896, N8894, N8890})
  );
  TransceiverControl U5 (
    .Reset(Reset),
    .SLPYEN(NET1456),
    .SLPYPD(NET1474),
    .MCLK(SMCLK_IBUF),
    .inDATA({N8856, N8854, N8852, N8900, N8898, N8896, N8894, N8890}),
    .PwrDwn({PD_7_OBUF, PD_6_OBUF, PD_5_OBUF, PD_4_OBUF, PD_3_OBUF, PD_2_OBUF, PD_1_OBUF, PD_0_OBUF}),
    .Enable({EN_7_OBUF, EN_6_OBUF, EN_5_OBUF, EN_4_OBUF, EN_3_OBUF, EN_2_OBUF, EN_1_OBUF, EN_0_OBUF})
  );
  PwrControl U6 (
    .AM2Status(AM2Status_IBUF),
    .AM1Status(AM1Status_IBUF),
    .Reset(Reset),
    .AM0Status(AM0Status_IBUF),
    .SLPYSYSEN(NET3560),
    .SystemStatus(SystemStatus_IBUF),
    .ExternalStatus(ExternalStatus_IBUF),
    .ModemStatus(ModemStatus_IBUF),
    .SLPYSTATUS(NET1523),
    .CameraStatus(CameraStatus_IBUF),
    .SLPYPWR(NET1448),
    .MCLK(SMCLK_IBUF),
    .ModemEN(ModemEN_OBUF),
    .AM2EN(AM2EN_OBUF),
    .CameraEN(CameraEN_OBUF),
    .ExternalEN(ExternalEN_OBUF),
    .DwarfEN(DwarfEN_OBUF),
    .AM0EN(AM0EN_OBUF),
    .SystemEN(SystemEN_OBUF),
    .AM1EN(AM1EN_OBUF),
    .SYSPWR(SYSPWR_OBUF),
    .inDATA({N8856, N8854, N8852, N8900, N8898, N8896, N8894, N8890}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_4__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_4___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0032[0]),
    .Result(U7_U3__n0002[4])
  );
  Interrupt U8 (
    .SCLint(NET1764),
    .AM2Status(AM2Status_IBUF),
    .AM1Status(AM1Status_IBUF),
    .Reset(Reset),
    .AM0Status(AM0Status_IBUF),
    .SystemStatus(SystemStatus_IBUF),
    .ExternalStatus(ExternalStatus_IBUF),
    .ModemStatus(ModemStatus_IBUF),
    .SLPYIEw(NET2480),
    .CameraStatus(CameraStatus_IBUF),
    .UARTint(UINT_IBUF),
    .SLPYIFGr(NET2533),
    .SystemEN(SystemEN_OBUF),
    .MCLK(SMCLK_IBUF),
    .INT(INT_OBUF),
    .inDATA({N8856, N8854, N8852, N8900, N8898, N8896, N8894, N8890}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  GND XST_GND (
    .G(IOCHCHK_OBUFE)
  );
  OBUFE ENDXFR_OBUFE (
    .E(IOCHCHK_OBUFE),
    .I(IOCHCHK_OBUFE),
    .O(ENDXFR)
  );
  AND2 U2_ADDR_reg_1__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_1__n00005),
    .O(U2_ADDR_reg_1__n0000)
  );
  AND2 U2_ADDR_reg_2__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_2__n00005),
    .O(U2_ADDR_reg_2__n0000)
  );
  BUFE U7_U3_I1_6 (
    .E(NET1535),
    .I(IOCHCHK_OBUFE),
    .O(outDATA[6])
  );
  AND2 U2_ADDR_reg_3__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_3__n00005),
    .O(U2_ADDR_reg_3__n0000)
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_1_ (
    .Data_0_(U2_ADDR_reg[0]),
    .Data_1_(U2_ADDR_reg[1]),
    .Result(U2__n0011[1])
  );
  AND2 U2_ADDR_reg_4__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_4__n00005),
    .O(U2_ADDR_reg_4__n0000)
  );
  AND2 U2_ADDR_reg_5__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_5__n00005),
    .O(U2_ADDR_reg_5__n0000)
  );
  AND2 U2_ADDR_reg_6__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_6__n00005),
    .O(U2_ADDR_reg_6__n0000)
  );
  AND2 U2_ADDR_reg_7__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_7__n00005),
    .O(U2_ADDR_reg_7__n0000)
  );
  INV U2__n00181 (
    .I(AS_IBUF),
    .O(U2__n0018)
  );
  AND2 U3_PC104reg_3__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8898),
    .O(U3_PC104reg_3__n0000)
  );
  AND2 U7_U3__n00428 (
    .I0(U7_U3__n00424),
    .I1(U7_U3__n00427),
    .O(U7_U3__n0042)
  );
  INV U7_U3__n0003_3_1 (
    .I(U7_U3__n0006),
    .O(U7_U3__n0003[3])
  );
  OR2 U2_ADDR_reg_0__n00029 (
    .I0(U2_ADDR_reg_0__n00028),
    .I1(U2_ADDR_reg_0__n00024),
    .O(U2_ADDR_reg_0__n0002)
  );
  OR2 U7_U3__n0000_2_11 (
    .I0(U7_U3__n0000_2_9),
    .I1(U7_U3__n0000_2_10),
    .O(U7_U3__n0000[2])
  );
  AND2 U2_ADDR_reg_0__n00006 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_0__n00005),
    .O(U2_ADDR_reg_0__n0000)
  );
  OR4 U7_U3__n0000_0_17 (
    .I3(U7_U3__n0000_0_14),
    .I0(U7_U3__n0000_0_1),
    .I1(U7_U3__n0000_0_15),
    .I2(U7_U3__n0000_0_16),
    .O(U7_U3__n0000[0])
  );
  BUFE U7_U3_I1_2 (
    .E(NET1535),
    .I(U7_U3_counterr[2]),
    .O(outDATA[2])
  );
  BUFE U7_U3_I1_4 (
    .E(NET1535),
    .I(U7_U3_counterr[4]),
    .O(outDATA[4])
  );
  AND2 U2__n00032 (
    .I0(U2_WRRDedge),
    .I1(U2__n00031),
    .O(U2__n0003)
  );
  FD U7_U3_counterr_4 (
    .D(U7_U3__n0000[4]),
    .C(U3_PC104reg_0__n0003),
    .Q(U7_U3_counterr[4])
  );
  FD U2_ASedge_809 (
    .D(AS_IBUF),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ASedge)
  );
  FD U2_WRRDedge_810 (
    .D(U2__n0000),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_WRRDedge)
  );
  BUFE U7_U3_I1_3 (
    .E(NET1535),
    .I(U7_U3_counterr[3]),
    .O(outDATA[3])
  );
  NegDetect U7_U1 (
    .Line(SCLinc_IBUF),
    .MCLK(SMCLK_IBUF),
    .Ndetect(U7_Incdetect)
  );
  IOBUFE AD_7_IOBUFE (
    .I(outDATA[7]),
    .E(U2_Enable_AD),
    .O(N8856),
    .IO(AD[7])
  );
  AND8 U2_Mcompar__n0006_ALB1 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_ADDR_reg[7]),
    .I2(U2_ADDR_reg[5]),
    .I3(U2_ADDR_reg[6]),
    .I4(U2_ADDR_reg[1]),
    .I5(U2_ADDR_reg[0]),
    .I6(U2_ADDR_reg[2]),
    .I7(U2_ADDR_reg[3]),
    .O(U2__n0006)
  );
  AND2 U2__n00054 (
    .I0(U2__n00051),
    .I1(U2__n00053),
    .O(U2__n0005)
  );
  AND2 U2_Enable_AD2 (
    .I0(WR_IBUF),
    .I1(U2_Enable_AD1),
    .O(U2_Enable_AD)
  );
  AND2 U2__n00001 (
    .I0(WR_IBUF),
    .I1(RD_IBUF),
    .O(U2__n0000)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_4__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[4]),
    .Data_1_(U7_U3__n0006),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_4___n0002[0])
  );
  IOBUFE AD_6_IOBUFE (
    .I(outDATA[6]),
    .E(U2_Enable_AD),
    .O(N8854),
    .IO(AD[6])
  );
  IOBUFE AD_5_IOBUFE (
    .I(outDATA[5]),
    .E(U2_Enable_AD),
    .O(N8852),
    .IO(AD[5])
  );
  FDCE U2_AutoInc_811 (
    .D(U2__n0018),
    .CE(U2__n0003),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_AutoInc)
  );
  IOBUFE AD_0_IOBUFE (
    .I(outDATA[0]),
    .E(U2_Enable_AD),
    .O(N8890),
    .IO(AD[0])
  );
  IOBUFE AD_1_IOBUFE (
    .I(outDATA[1]),
    .E(U2_Enable_AD),
    .O(N8894),
    .IO(AD[1])
  );
  IOBUFE AD_2_IOBUFE (
    .I(outDATA[2]),
    .E(U2_Enable_AD),
    .O(N8896),
    .IO(AD[2])
  );
  IOBUFE AD_3_IOBUFE (
    .I(outDATA[3]),
    .E(U2_Enable_AD),
    .O(N8898),
    .IO(AD[3])
  );
  IOBUFE AD_4_IOBUFE (
    .I(outDATA[4]),
    .E(U2_Enable_AD),
    .O(N8900),
    .IO(AD[4])
  );
  VCC XST_VCC (
    .P(N6204)
  );
  AND2 U2_Madd__n0011__n00051 (
    .I0(U2_ADDR_reg[6]),
    .I1(U2_Madd__n0011__n0016[0]),
    .O(U2_Madd__n0011__n0018[0])
  );
  AND2 U2_Madd__n0011__n00041 (
    .I0(U2_ADDR_reg[5]),
    .I1(U2_Madd__n0011__n0014[0]),
    .O(U2_Madd__n0011__n0016[0])
  );
  AND2 U2_Madd__n0011__n00031 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_Madd__n0011__n0012[0]),
    .O(U2_Madd__n0011__n0014[0])
  );
  AND2 U2_Madd__n0011__n00021 (
    .I0(U2_ADDR_reg[3]),
    .I1(U2_Madd__n0011__n0010[0]),
    .O(U2_Madd__n0011__n0012[0])
  );
  AND2 U2_Madd__n0011__n00011 (
    .I0(U2_ADDR_reg[2]),
    .I1(U2_Madd__n0011__n0008[0]),
    .O(U2_Madd__n0011__n0010[0])
  );
  AND2 U2_Madd__n0011__n00001 (
    .I0(U2_ADDR_reg[1]),
    .I1(U2_ADDR_reg[0]),
    .O(U2_Madd__n0011__n0008[0])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_7_ (
    .Data_0_(U2_Madd__n0011__n0018[0]),
    .Data_1_(U2_ADDR_reg[7]),
    .Result(U2__n0011[7])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_6_ (
    .Data_0_(U2_Madd__n0011__n0016[0]),
    .Data_1_(U2_ADDR_reg[6]),
    .Result(U2__n0011[6])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_5_ (
    .Data_0_(U2_Madd__n0011__n0014[0]),
    .Data_1_(U2_ADDR_reg[5]),
    .Result(U2__n0011[5])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_4_ (
    .Data_0_(U2_Madd__n0011__n0012[0]),
    .Data_1_(U2_ADDR_reg[4]),
    .Result(U2__n0011[4])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_3_ (
    .Data_0_(U2_Madd__n0011__n0010[0]),
    .Data_1_(U2_ADDR_reg[3]),
    .Result(U2__n0011[3])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_2_ (
    .Data_0_(U2_Madd__n0011__n0008[0]),
    .Data_1_(U2_ADDR_reg[2]),
    .Result(U2__n0011[2])
  );
  FDCE U2_ADDR_reg_7 (
    .D(U2_ADDR_reg_7__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[7])
  );
  FDCE U2_ADDR_reg_6 (
    .D(U2_ADDR_reg_6__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[6])
  );
  FDCE U2_ADDR_reg_0 (
    .D(U2_ADDR_reg_0__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[0])
  );
  FDCE U2_ADDR_reg_1 (
    .D(U2_ADDR_reg_1__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[1])
  );
  FDCE U2_ADDR_reg_2 (
    .D(U2_ADDR_reg_2__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[2])
  );
  FDCE U2_ADDR_reg_3 (
    .D(U2_ADDR_reg_3__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[3])
  );
  FDCE U2_ADDR_reg_4 (
    .D(U2_ADDR_reg_4__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[4])
  );
  FDCE U2_ADDR_reg_5 (
    .D(U2_ADDR_reg_5__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U2_ADDR_reg[5])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_1__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_1___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0026[0]),
    .Result(U7_U3__n0002[1])
  );
  OR2 U7_U3_Maddsub__n0002__n00027 (
    .I0(U7_U3_Maddsub__n0002__n0002),
    .I1(U7_U3_Maddsub__n0002__n00025),
    .O(U7_U3_Maddsub__n0002__n0030[1])
  );
  OR2 U7_U3_Maddsub__n0002__n00017 (
    .I0(U7_U3_Maddsub__n0002__n0001),
    .I1(U7_U3_Maddsub__n0002__n00015),
    .O(U7_U3_Maddsub__n0002__n0028[1])
  );
  BUFE U7_U3_I1_1 (
    .E(NET1535),
    .I(U7_U3_counterr[1]),
    .O(outDATA[1])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0023 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(U7_U3__n0003[3]),
    .Result(U7_U3_Maddsub__n0002__n0030[0])
  );
  AND2 U7_U3_Maddsub__n0002__n00181 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3_Maddsub__n0002__n0032[0]),
    .O(U7_U3_Maddsub__n0002__n0018)
  );
  BUFE U7_U3_I1_5 (
    .E(NET1535),
    .I(U7_U3_counterr[5]),
    .O(outDATA[5])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0022 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(IOCHCHK_OBUFE),
    .Result(U7_U3_Maddsub__n0002__n0028[0])
  );
  AND2 U3_PC104reg_5__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8852),
    .O(U3_PC104reg_5__n0000)
  );
  AND2 U7_U3__n00417 (
    .I0(U7_U3__n00411),
    .I1(U7_U3__n00416),
    .O(U7_U3__n0041)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0021 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(IOCHCHK_OBUFE),
    .Result(U7_U3_Maddsub__n0002__n0026[0])
  );
  OR2 U7_U3_Maddsub__n0002__n00037 (
    .I0(U7_U3_Maddsub__n0002__n0003),
    .I1(U7_U3_Maddsub__n0002__n00035),
    .O(U7_U3_Maddsub__n0002__n0032[0])
  );
  OR3 U7_U3__n0000_5_10 (
    .I0(U7_U3__n0000_5_9),
    .I1(U7_U3__n0000_5_1),
    .I2(U7_U3__n0000_5_7),
    .O(U7_U3__n0000[5])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0020 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(N6204),
    .Result(U7_U3_Maddsub__n0002__n0020)
  );
  AND3 U7_U3__n00063 (
    .I0(U7_U3__n00061),
    .I1(U7_SCLdetect),
    .I2(U7_U3__n00062),
    .O(U7_U3__n0006)
  );
  OR3 U7_U3__n0000_4_10 (
    .I0(U7_U3__n0000_4_9),
    .I1(U7_U3__n0000_4_1),
    .I2(U7_U3__n0000_4_7),
    .O(U7_U3__n0000[4])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_5__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[5]),
    .Data_1_(U7_U3__n0006),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_5___n0002[0])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_2__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_2___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0028[0]),
    .Result(U7_U3__n0002[2])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_3__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_3___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0030[0]),
    .Result(U7_U3__n0002[3])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_3__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[3]),
    .Data_1_(U7_U3_Maddsub__n0002__n0030[1]),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_3___n0002[0])
  );
  FD U7_U3_counterr_2 (
    .D(U7_U3__n0000[2]),
    .C(U3_PC104reg_0__n0003),
    .Q(U7_U3_counterr[2])
  );
  OR2 U3__n00615 (
    .I0(U3__n0061),
    .I1(U3__n00613),
    .O(UAD_4_OBUF)
  );
  OR2 U3__n00584 (
    .I0(U3__n00582),
    .I1(U3__n00581),
    .O(UAD_5_OBUF)
  );
  OR2 U3__n00554 (
    .I0(U3__n00552),
    .I1(U3__n00551),
    .O(UAD_6_OBUF)
  );
  OR2 U3__n00524 (
    .I0(U3__n00522),
    .I1(U3__n00521),
    .O(UAD_7_OBUF)
  );
  OR2 U3__n00494 (
    .I0(U3__n00492),
    .I1(U3__n00491),
    .O(UAD_0_OBUF)
  );
  OR2 U3__n00464 (
    .I0(U3__n00462),
    .I1(U3__n00461),
    .O(UAD_1_OBUF)
  );
  AND2 U7_U3_Maddsub__n0002__n00171 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3__n0006),
    .O(U7_U3_Maddsub__n0002__n0017)
  );
  OR2 U3__n00404 (
    .I0(U3__n00402),
    .I1(U3__n00401),
    .O(UAD_3_OBUF)
  );
  INV U3__n00321 (
    .I(U3__n0028),
    .O(U3__n0032)
  );
  AND2 U3__n00283 (
    .I0(U3__n00281),
    .I1(U3__n00282),
    .O(U3__n0028)
  );
  INV U7_U3_Maddsub__n0002__n00045 (
    .I(U7_U3_Maddsub__n0002__n00043),
    .O(U7_U3_Maddsub__n0002__n0034[0])
  );
  OR3 U7_U3__n0000_3_11 (
    .I0(U7_U3__n0000_3_10),
    .I1(SCLreset_IBUF),
    .I2(U7_U3__n0000_3_9),
    .O(U7_U3__n0000[3])
  );
  OR2 U3__n00158 (
    .I0(U3__n00157),
    .I1(U3__n00156),
    .O(U3__n0015)
  );
  NegDetect U7_U4 (
    .Line(SCLreset_IBUF),
    .MCLK(SMCLK_IBUF),
    .Ndetect(U7_ResetDetect)
  );
  FD U7_U3_counterr_3 (
    .D(U7_U3__n0000[3]),
    .C(U3_PC104reg_0__n0003),
    .Q(U7_U3_counterr[3])
  );
  IOBUFE UD_7_IOBUFE_812 (
    .I(UD_7_IOBUFE),
    .E(U3__n0032),
    .O(SD_7_IOBUFE),
    .IO(UD[7])
  );
  OR2 U7_U3_Maddsub__n0002__n00007 (
    .I0(U7_U3_Maddsub__n0002__n0000),
    .I1(U7_U3_Maddsub__n0002__n00005),
    .O(U7_U3_Maddsub__n0002__n0026[1])
  );
  AND2 U3_PC104reg_6__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8854),
    .O(U3_PC104reg_6__n0000)
  );
  OR2 U3__n00434 (
    .I0(U3__n00432),
    .I1(U3__n00431),
    .O(UAD_2_OBUF)
  );
  LPM_XOR2_1 U7_U3_Madd__n0001_Mxor_Result_1_ (
    .Data_0_(U7_U3_counterr[3]),
    .Data_1_(U7_U3_counterr[4]),
    .Result(U7_U3__n0049[4])
  );
  BUFE U3_I2_7 (
    .E(U3__n0003),
    .I(SD_7_IOBUFE),
    .O(outDATA[7])
  );
  AND2 U3_PC104reg_1__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8894),
    .O(U3_PC104reg_1__n0000)
  );
  AND2 U3_PC104reg_2__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8896),
    .O(U3_PC104reg_2__n0000)
  );
  BUFE U7_U3_I1_7 (
    .E(NET1535),
    .I(IOCHCHK_OBUFE),
    .O(outDATA[7])
  );
  AND3 U3__n0004_7_6 (
    .I0(U3__n0004_7_5),
    .I1(U3__n0015),
    .I2(U3__n0004_7_3),
    .O(UD_7_IOBUFE)
  );
  INV U3_UARTcs1 (
    .I(U3__n0015),
    .O(UCS_OBUF)
  );
  OR3 U3_Mmux_UIOR_Result5 (
    .I0(U3_Mmux_UIOR_Result3),
    .I1(U3_Mmux_UIOR_Result),
    .I2(U3_Mmux_UIOR_Result2),
    .O(UIOR_OBUF)
  );
  AND2 U7_U3_Maddsub__n0002__n00191 (
    .I0(U7_U3__n0006),
    .I1(U7_U3_Maddsub__n0002__n0032[0]),
    .O(U7_U3_Maddsub__n0002__n0019)
  );
  OR3 U3_Mmux_UIOW_Result5 (
    .I0(U3_Mmux_UIOW_Result3),
    .I1(U3_Mmux_UIOW_Result),
    .I2(U3_Mmux_UIOW_Result2),
    .O(UIOW_OBUF)
  );
  AND2 U3_PC104reg_4__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8900),
    .O(U3_PC104reg_4__n0000)
  );
  AND3 U3__n0004_0_6 (
    .I0(U3__n0004_0_5),
    .I1(U3__n0015),
    .I2(U3__n0004_0_3),
    .O(UD_0_IOBUFE)
  );
  AND3 U3__n0004_1_6 (
    .I0(U3__n0004_1_5),
    .I1(U3__n0015),
    .I2(U3__n0004_1_3),
    .O(UD_1_IOBUFE)
  );
  AND3 U3__n0004_2_6 (
    .I0(U3__n0004_2_5),
    .I1(U3__n0015),
    .I2(U3__n0004_2_3),
    .O(UD_2_IOBUFE)
  );
  AND3 U3__n0004_3_6 (
    .I0(U3__n0004_3_5),
    .I1(U3__n0015),
    .I2(U3__n0004_3_3),
    .O(UD_3_IOBUFE)
  );
  AND3 U3__n0004_4_6 (
    .I0(U3__n0004_4_5),
    .I1(U3__n0015),
    .I2(U3__n0004_4_3),
    .O(UD_4_IOBUFE)
  );
  AND3 U3__n0004_5_6 (
    .I0(U3__n0004_5_5),
    .I1(U3__n0015),
    .I2(U3__n0004_5_3),
    .O(UD_5_IOBUFE)
  );
  AND3 U3__n0004_6_6 (
    .I0(U3__n0004_6_5),
    .I1(U3__n0015),
    .I2(U3__n0004_6_3),
    .O(UD_6_IOBUFE)
  );
  FD U7_U3_counterr_1 (
    .D(U7_U3__n0000[1]),
    .C(U3_PC104reg_0__n0003),
    .Q(U7_U3_counterr[1])
  );
  AND3 U3__n00033 (
    .I0(U3__n00031),
    .I1(U3__n0015),
    .I2(U3__n00032),
    .O(U3__n0003)
  );
  AND2 U3__n00025 (
    .I0(U3__n00021),
    .I1(U3__n00024),
    .O(U3__n0002)
  );
  AND2 U3__n00012 (
    .I0(Bus_Select_IBUF),
    .I1(U3__n0001),
    .O(IRQ_OBUF)
  );
  IOBUFE SD_7_IOBUFE_813 (
    .I(SD_7_IOBUFE),
    .E(U3__n0002),
    .O(N8872),
    .IO(SD[7])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_5__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_5___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0034[0]),
    .Result(U7_U3__n0002[5])
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0006 (
    .Data_0_(U3_PC104reg[0]),
    .Data_1_(SA_8_IBUF),
    .Result(U3_Mcompar__n0011__n0006)
  );
  LPM_XOR2_1 U3_Madd__n0000_Mxor_Result_1_ (
    .Data_0_(U2_ADDR_reg[4]),
    .Data_1_(U2_ADDR_reg[5]),
    .Result(U3__n0000[1])
  );
  OR3 U7_U3__n0000_1_13 (
    .I0(U7_U3__n0000_1_12),
    .I1(U7_U3__n0000_1_11),
    .I2(U7_U3__n0000_1_8),
    .O(U7_U3__n0000[1])
  );
  AND2 U3_PC104reg_0__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8890),
    .O(U3_PC104reg_0__n0000)
  );
  IOBUFE UD_0_IOBUFE_814 (
    .I(UD_0_IOBUFE),
    .E(U3__n0032),
    .O(SD_0_IOBUFE),
    .IO(UD[0])
  );
  IOBUFE UD_1_IOBUFE_815 (
    .I(UD_1_IOBUFE),
    .E(U3__n0032),
    .O(SD_1_IOBUFE),
    .IO(UD[1])
  );
  IOBUFE UD_2_IOBUFE_816 (
    .I(UD_2_IOBUFE),
    .E(U3__n0032),
    .O(SD_2_IOBUFE),
    .IO(UD[2])
  );
  IOBUFE UD_3_IOBUFE_817 (
    .I(UD_3_IOBUFE),
    .E(U3__n0032),
    .O(SD_3_IOBUFE),
    .IO(UD[3])
  );
  IOBUFE UD_4_IOBUFE_818 (
    .I(UD_4_IOBUFE),
    .E(U3__n0032),
    .O(SD_4_IOBUFE),
    .IO(UD[4])
  );
  IOBUFE UD_5_IOBUFE_819 (
    .I(UD_5_IOBUFE),
    .E(U3__n0032),
    .O(SD_5_IOBUFE),
    .IO(UD[5])
  );
  IOBUFE UD_6_IOBUFE_820 (
    .I(UD_6_IOBUFE),
    .E(U3__n0032),
    .O(SD_6_IOBUFE),
    .IO(UD[6])
  );
  BUFE U3_I2_0 (
    .E(U3__n0003),
    .I(SD_0_IOBUFE),
    .O(outDATA[0])
  );
  BUFE U3_I2_1 (
    .E(U3__n0003),
    .I(SD_1_IOBUFE),
    .O(outDATA[1])
  );
  BUFE U3_I2_2 (
    .E(U3__n0003),
    .I(SD_2_IOBUFE),
    .O(outDATA[2])
  );
  BUFE U3_I2_3 (
    .E(U3__n0003),
    .I(SD_3_IOBUFE),
    .O(outDATA[3])
  );
  BUFE U3_I2_4 (
    .E(U3__n0003),
    .I(SD_4_IOBUFE),
    .O(outDATA[4])
  );
  BUFE U3_I2_5 (
    .E(U3__n0003),
    .I(SD_5_IOBUFE),
    .O(outDATA[5])
  );
  BUFE U3_I2_6 (
    .E(U3__n0003),
    .I(SD_6_IOBUFE),
    .O(outDATA[6])
  );
  IOBUFE SD_0_IOBUFE_821 (
    .I(SD_0_IOBUFE),
    .E(U3__n0002),
    .O(N8858),
    .IO(SD[0])
  );
  IOBUFE SD_1_IOBUFE_822 (
    .I(SD_1_IOBUFE),
    .E(U3__n0002),
    .O(N8860),
    .IO(SD[1])
  );
  IOBUFE SD_2_IOBUFE_823 (
    .I(SD_2_IOBUFE),
    .E(U3__n0002),
    .O(N8862),
    .IO(SD[2])
  );
  IOBUFE SD_3_IOBUFE_824 (
    .I(SD_3_IOBUFE),
    .E(U3__n0002),
    .O(N8864),
    .IO(SD[3])
  );
  IOBUFE SD_4_IOBUFE_825 (
    .I(SD_4_IOBUFE),
    .E(U3__n0002),
    .O(N8866),
    .IO(SD[4])
  );
  IOBUFE SD_5_IOBUFE_826 (
    .I(SD_5_IOBUFE),
    .E(U3__n0002),
    .O(N8868),
    .IO(SD[5])
  );
  IOBUFE SD_6_IOBUFE_827 (
    .I(SD_6_IOBUFE),
    .E(U3__n0002),
    .O(N8870),
    .IO(SD[6])
  );
  AND6 U7_U3__n00057 (
    .I0(U7_U3__n00051),
    .I1(U7_U3__n0005),
    .I2(U7_U3__n00052),
    .I3(U7_U3__n00054),
    .I4(U7_U3__n00053),
    .I5(U7_U3__n00055),
    .O(NET1764)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_0_ (
    .Data_0_(U7_U3_counterr[0]),
    .Data_1_(N6204),
    .Result(U7_U3__n0002[0])
  );
  FD U7_U3_counterr_5 (
    .D(U7_U3__n0000[5]),
    .C(U3_PC104reg_0__n0003),
    .Q(U7_U3_counterr[5])
  );
  AND2 U7_U3_Madd__n0001__n00001 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3_counterr[3]),
    .O(U7_U3_Madd__n0001__n0003[0])
  );
  LPM_XOR2_1 U7_U3_Madd__n0001_Mxor_Result_2_ (
    .Data_0_(U7_U3_Madd__n0001__n0003[0]),
    .Data_1_(U7_U3_counterr[5]),
    .Result(U7_U3__n0049[5])
  );
  BUFE U7_U3_I1_0 (
    .E(NET1535),
    .I(U7_U3_counterr[0]),
    .O(outDATA[0])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_2__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[2]),
    .Data_1_(U7_U3_Maddsub__n0002__n0028[1]),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_2___n0002[0])
  );
  AND8 U3_Mcompar__n0011__n00149 (
    .I0(U3_Mcompar__n0011__n00141),
    .I1(U3_Mcompar__n0011__n00142),
    .I2(U3_Mcompar__n0011__n00143),
    .I3(U3_Mcompar__n0011__n00144),
    .I4(U3_Mcompar__n0011__n00145),
    .I5(U3_Mcompar__n0011__n00146),
    .I6(U3_Mcompar__n0011__n00147),
    .I7(U3_Mcompar__n0011__n00148),
    .O(U3_Mcompar__n0011__n0014)
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0013 (
    .Data_0_(U3_PC104reg[7]),
    .Data_1_(SA_15_IBUF),
    .Result(U3_Mcompar__n0011__n0013)
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0012 (
    .Data_0_(U3_PC104reg[6]),
    .Data_1_(SA_14_IBUF),
    .Result(U3_Mcompar__n0011__n0012)
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0011 (
    .Data_0_(U3_PC104reg[5]),
    .Data_1_(SA_13_IBUF),
    .Result(U3_Mcompar__n0011__n0011)
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0010 (
    .Data_0_(U3_PC104reg[4]),
    .Data_1_(SA_12_IBUF),
    .Result(U3_Mcompar__n0011__n0010)
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0009 (
    .Data_0_(U3_PC104reg[3]),
    .Data_1_(SA_11_IBUF),
    .Result(U3_Mcompar__n0011__n0009)
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0008 (
    .Data_0_(U3_PC104reg[2]),
    .Data_1_(SA_10_IBUF),
    .Result(U3_Mcompar__n0011__n0008)
  );
  LPM_XOR2_1 U3_Mcompar__n0011_Mxor__n0007 (
    .Data_0_(U3_PC104reg[1]),
    .Data_1_(SA_9_IBUF),
    .Result(U3_Mcompar__n0011__n0007)
  );
  INV U3_Madd__n0000__n00141 (
    .I(U2_ADDR_reg[7]),
    .O(U3_Madd__n0000__n0007[1])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_1__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[1]),
    .Data_1_(U7_U3_Maddsub__n0002__n0026[1]),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_1___n0002[0])
  );
  AND2 U3_Madd__n0000__n00011 (
    .I0(U2_ADDR_reg[6]),
    .I1(U3_Madd__n0000__n0005[0]),
    .O(U3_Madd__n0000__n0007[0])
  );
  AND2 U3_Madd__n0000__n00001 (
    .I0(U2_ADDR_reg[5]),
    .I1(U2_ADDR_reg[4]),
    .O(U3_Madd__n0000__n0005[0])
  );
  LPM_XOR2_1 U3_Madd__n0000_Mxor_Result_3_ (
    .Data_0_(U3_Madd__n0000__n0007[0]),
    .Data_1_(U3_Madd__n0000__n0007[1]),
    .Result(U3__n0000[3])
  );
  LPM_XOR2_1 U3_Madd__n0000_Mxor_Result_2_ (
    .Data_0_(U3_Madd__n0000__n0005[0]),
    .Data_1_(U2_ADDR_reg[6]),
    .Result(U3__n0000[2])
  );
  FDCE U3_PC104reg_7 (
    .D(U3_PC104reg_7__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[7])
  );
  FDCE U3_PC104reg_6 (
    .D(U3_PC104reg_6__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[6])
  );
  FDCE U3_PC104reg_0 (
    .D(U3_PC104reg_0__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[0])
  );
  FDCE U3_PC104reg_1 (
    .D(U3_PC104reg_1__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[1])
  );
  FDCE U3_PC104reg_2 (
    .D(U3_PC104reg_2__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[2])
  );
  FDCE U3_PC104reg_3 (
    .D(U3_PC104reg_3__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[3])
  );
  FDCE U3_PC104reg_4 (
    .D(U3_PC104reg_4__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[4])
  );
  FDCE U3_PC104reg_5 (
    .D(U3_PC104reg_5__n0000),
    .CE(U3_PC104reg_7__n0002),
    .CLR(IOCHCHK_OBUFE),
    .C(U3_PC104reg_0__n0003),
    .Q(U3_PC104reg[5])
  );
  NegDetect U7_U2 (
    .Line(N8892),
    .MCLK(SMCLK_IBUF),
    .Ndetect(U7_SCLdetect)
  );
  INV U3_PC104reg_7__n00023 (
    .I(U3_PC104reg_7__n00022),
    .O(U3_PC104reg_7__n0002)
  );
  AND2 U3_PC104reg_7__n00001 (
    .I0(CPLD_Reset_IBUF),
    .I1(N8856),
    .O(U3_PC104reg_7__n0000)
  );
  FD U7_U3_counterr_0 (
    .D(U7_U3__n0000[0]),
    .C(U3_PC104reg_0__n0003),
    .Q(U7_U3_counterr[0])
  );
  AND2 U2_ADDR_reg_1__n00001_828 (
    .I0(U2__n0005),
    .I1(N8894),
    .O(U2_ADDR_reg_1__n00001)
  );
  INV U2_ADDR_reg_1__n00002_829 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_1__n00002)
  );
  INV U2_ADDR_reg_1__n00003_830 (
    .I(U2__n0006),
    .O(U2_ADDR_reg_1__n00003)
  );
  AND3 U2_ADDR_reg_1__n00004_831 (
    .I0(U2_ADDR_reg_1__n00002),
    .I1(U2__n0011[1]),
    .I2(U2_ADDR_reg_1__n00003),
    .O(U2_ADDR_reg_1__n00004)
  );
  OR2 U2_ADDR_reg_1__n00005_832 (
    .I0(U2_ADDR_reg_1__n00001),
    .I1(U2_ADDR_reg_1__n00004),
    .O(U2_ADDR_reg_1__n00005)
  );
  AND2 U2_ADDR_reg_2__n00001_833 (
    .I0(U2__n0005),
    .I1(N8896),
    .O(U2_ADDR_reg_2__n00001)
  );
  INV U2_ADDR_reg_2__n00002_834 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_2__n00002)
  );
  INV U2_ADDR_reg_2__n00003_835 (
    .I(U2__n0006),
    .O(U2_ADDR_reg_2__n00003)
  );
  AND3 U2_ADDR_reg_2__n00004_836 (
    .I0(U2_ADDR_reg_2__n00002),
    .I1(U2__n0011[2]),
    .I2(U2_ADDR_reg_2__n00003),
    .O(U2_ADDR_reg_2__n00004)
  );
  OR2 U2_ADDR_reg_2__n00005_837 (
    .I0(U2_ADDR_reg_2__n00001),
    .I1(U2_ADDR_reg_2__n00004),
    .O(U2_ADDR_reg_2__n00005)
  );
  AND2 U2_ADDR_reg_3__n00001_838 (
    .I0(U2__n0005),
    .I1(N8898),
    .O(U2_ADDR_reg_3__n00001)
  );
  INV U2_ADDR_reg_3__n00002_839 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_3__n00002)
  );
  INV U2_ADDR_reg_3__n00003_840 (
    .I(U2__n0006),
    .O(U2_ADDR_reg_3__n00003)
  );
  AND3 U2_ADDR_reg_3__n00004_841 (
    .I0(U2_ADDR_reg_3__n00002),
    .I1(U2__n0011[3]),
    .I2(U2_ADDR_reg_3__n00003),
    .O(U2_ADDR_reg_3__n00004)
  );
  OR2 U2_ADDR_reg_3__n00005_842 (
    .I0(U2_ADDR_reg_3__n00001),
    .I1(U2_ADDR_reg_3__n00004),
    .O(U2_ADDR_reg_3__n00005)
  );
  AND2 U2_ADDR_reg_4__n00001_843 (
    .I0(U2__n0005),
    .I1(N8900),
    .O(U2_ADDR_reg_4__n00001)
  );
  INV U2_ADDR_reg_4__n00002_844 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_4__n00002)
  );
  INV U2_ADDR_reg_4__n00003_845 (
    .I(U2__n0006),
    .O(U2_ADDR_reg_4__n00003)
  );
  AND3 U2_ADDR_reg_4__n00004_846 (
    .I0(U2_ADDR_reg_4__n00002),
    .I1(U2__n0011[4]),
    .I2(U2_ADDR_reg_4__n00003),
    .O(U2_ADDR_reg_4__n00004)
  );
  OR2 U2_ADDR_reg_4__n00005_847 (
    .I0(U2_ADDR_reg_4__n00001),
    .I1(U2_ADDR_reg_4__n00004),
    .O(U2_ADDR_reg_4__n00005)
  );
  AND2 U2_ADDR_reg_5__n00001_848 (
    .I0(U2__n0005),
    .I1(N8852),
    .O(U2_ADDR_reg_5__n00001)
  );
  INV U2_ADDR_reg_5__n00002_849 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_5__n00002)
  );
  INV U2_ADDR_reg_5__n00003_850 (
    .I(U2__n0006),
    .O(U2_ADDR_reg_5__n00003)
  );
  AND3 U2_ADDR_reg_5__n00004_851 (
    .I0(U2_ADDR_reg_5__n00002),
    .I1(U2__n0011[5]),
    .I2(U2_ADDR_reg_5__n00003),
    .O(U2_ADDR_reg_5__n00004)
  );
  OR2 U2_ADDR_reg_5__n00005_852 (
    .I0(U2_ADDR_reg_5__n00001),
    .I1(U2_ADDR_reg_5__n00004),
    .O(U2_ADDR_reg_5__n00005)
  );
  AND2 U2_ADDR_reg_6__n00001_853 (
    .I0(U2__n0005),
    .I1(N8854),
    .O(U2_ADDR_reg_6__n00001)
  );
  INV U2_ADDR_reg_6__n00002_854 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_6__n00002)
  );
  INV U2_ADDR_reg_6__n00003_855 (
    .I(U2__n0006),
    .O(U2_ADDR_reg_6__n00003)
  );
  AND3 U2_ADDR_reg_6__n00004_856 (
    .I0(U2_ADDR_reg_6__n00002),
    .I1(U2__n0011[6]),
    .I2(U2_ADDR_reg_6__n00003),
    .O(U2_ADDR_reg_6__n00004)
  );
  OR2 U2_ADDR_reg_6__n00005_857 (
    .I0(U2_ADDR_reg_6__n00001),
    .I1(U2_ADDR_reg_6__n00004),
    .O(U2_ADDR_reg_6__n00005)
  );
  AND2 U2_ADDR_reg_7__n00001_858 (
    .I0(U2__n0005),
    .I1(N8856),
    .O(U2_ADDR_reg_7__n00001)
  );
  INV U2_ADDR_reg_7__n00002_859 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_7__n00002)
  );
  INV U2_ADDR_reg_7__n00003_860 (
    .I(U2__n0006),
    .O(U2_ADDR_reg_7__n00003)
  );
  AND3 U2_ADDR_reg_7__n00004_861 (
    .I0(U2_ADDR_reg_7__n00002),
    .I1(U2__n0011[7]),
    .I2(U2_ADDR_reg_7__n00003),
    .O(U2_ADDR_reg_7__n00004)
  );
  OR2 U2_ADDR_reg_7__n00005_862 (
    .I0(U2_ADDR_reg_7__n00001),
    .I1(U2_ADDR_reg_7__n00004),
    .O(U2_ADDR_reg_7__n00005)
  );
  INV U7_U3__n00421_863 (
    .I(U7_SCLdetect),
    .O(U7_U3__n00421)
  );
  INV U7_U3__n00422_864 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n00422)
  );
  INV U7_U3__n00423_865 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n00423)
  );
  AND2 U7_U3__n00424_866 (
    .I0(U7_Incdetect),
    .I1(U7_U3__n00421),
    .O(U7_U3__n00424)
  );
  AND2 U7_U3__n00425_867 (
    .I0(U7_ResetDetect),
    .I1(U7_U3__n00423),
    .O(U7_U3__n00425)
  );
  INV U7_U3__n00426_868 (
    .I(U7_U3__n00425),
    .O(U7_U3__n00426)
  );
  AND2 U7_U3__n00427_869 (
    .I0(U7_U3__n00422),
    .I1(U7_U3__n00426),
    .O(U7_U3__n00427)
  );
  AND2 U2_ADDR_reg_0__n00021_870 (
    .I0(RD_IBUF),
    .I1(WR_IBUF),
    .O(U2_ADDR_reg_0__n00021)
  );
  INV U2_ADDR_reg_0__n00022_871 (
    .I(AS_IBUF),
    .O(U2_ADDR_reg_0__n00022)
  );
  INV U2_ADDR_reg_0__n00023_872 (
    .I(U2_WRRDedge),
    .O(U2_ADDR_reg_0__n00023)
  );
  INV U2_ADDR_reg_0__n00024_873 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_0__n00024)
  );
  AND2 U2_ADDR_reg_0__n00025_874 (
    .I0(U2_ASedge),
    .I1(U2_ADDR_reg_0__n00022),
    .O(U2_ADDR_reg_0__n00025)
  );
  AND2 U2_ADDR_reg_0__n00026_875 (
    .I0(U2_AutoInc),
    .I1(U2_ADDR_reg_0__n00023),
    .O(U2_ADDR_reg_0__n00026)
  );
  OR2 U2_ADDR_reg_0__n00027_876 (
    .I0(U2_ADDR_reg_0__n00025),
    .I1(U2_ADDR_reg_0__n00026),
    .O(U2_ADDR_reg_0__n00027)
  );
  AND2 U2_ADDR_reg_0__n00028_877 (
    .I0(U2_ADDR_reg_0__n00021),
    .I1(U2_ADDR_reg_0__n00027),
    .O(U2_ADDR_reg_0__n00028)
  );
  INV U7_U3__n0000_2_1_878 (
    .I(NET1764),
    .O(U7_U3__n0000_2_1)
  );
  INV U7_U3__n0000_2_2_879 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_2_2)
  );
  INV U7_U3__n0000_2_3_880 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_2_3)
  );
  INV U7_U3__n0000_2_4_881 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_2_4)
  );
  AND2 U7_U3__n0000_2_5_882 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_2_1),
    .O(U7_U3__n0000_2_5)
  );
  AND3 U7_U3__n0000_2_6_883 (
    .I0(U7_U3__n0000_2_3),
    .I1(U7_U3__n0000_2_2),
    .I2(U7_U3__n0000_2_4),
    .O(U7_U3__n0000_2_6)
  );
  OR2 U7_U3__n0000_2_7_884 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_2_5),
    .O(U7_U3__n0000_2_7)
  );
  OR2 U7_U3__n0000_2_8_885 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_2_6),
    .O(U7_U3__n0000_2_8)
  );
  AND2 U7_U3__n0000_2_9_886 (
    .I0(U7_U3__n0002[2]),
    .I1(U7_U3__n0000_2_7),
    .O(U7_U3__n0000_2_9)
  );
  AND2 U7_U3__n0000_2_10_887 (
    .I0(U7_U3_counterr[2]),
    .I1(U7_U3__n0000_2_8),
    .O(U7_U3__n0000_2_10)
  );
  AND2 U2_ADDR_reg_0__n00001_888 (
    .I0(U2__n0005),
    .I1(N8890),
    .O(U2_ADDR_reg_0__n00001)
  );
  INV U2_ADDR_reg_0__n00002_889 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_0__n00002)
  );
  INV U2_ADDR_reg_0__n00003_890 (
    .I(U2_ADDR_reg[0]),
    .O(U2_ADDR_reg_0__n00003)
  );
  AND2 U2_ADDR_reg_0__n00004_891 (
    .I0(U2_ADDR_reg_0__n00002),
    .I1(U2_ADDR_reg_0__n00003),
    .O(U2_ADDR_reg_0__n00004)
  );
  OR2 U2_ADDR_reg_0__n00005_892 (
    .I0(U2_ADDR_reg_0__n00001),
    .I1(U2_ADDR_reg_0__n00004),
    .O(U2_ADDR_reg_0__n00005)
  );
  AND2 U7_U3__n0000_0_1_893 (
    .I0(SCLreset_IBUF),
    .I1(SCLinc_IBUF),
    .O(U7_U3__n0000_0_1)
  );
  INV U7_U3__n0000_0_2_894 (
    .I(NET1764),
    .O(U7_U3__n0000_0_2)
  );
  INV U7_U3__n0000_0_3_895 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_0_3)
  );
  INV U7_U3__n0000_0_4_896 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_0_4)
  );
  INV U7_U3__n0000_0_5_897 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_0_5)
  );
  AND2 U7_U3__n0000_0_6_898 (
    .I0(U7_Incdetect),
    .I1(U7_ResetDetect),
    .O(U7_U3__n0000_0_6)
  );
  INV U7_U3__n0000_0_7_899 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_0_7)
  );
  INV U7_U3__n0000_0_8_900 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n0000_0_8)
  );
  AND2 U7_U3__n0000_0_9_901 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_0_2),
    .O(U7_U3__n0000_0_9)
  );
  AND3 U7_U3__n0000_0_10_902 (
    .I0(U7_U3__n0000_0_4),
    .I1(U7_U3__n0000_0_3),
    .I2(U7_U3__n0000_0_5),
    .O(U7_U3__n0000_0_10)
  );
  AND2 U7_U3__n0000_0_11_903 (
    .I0(U7_U3__n0000_0_7),
    .I1(U7_U3__n0000_0_8),
    .O(U7_U3__n0000_0_11)
  );
  OR2 U7_U3__n0000_0_12_904 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_0_9),
    .O(U7_U3__n0000_0_12)
  );
  OR2 U7_U3__n0000_0_13_905 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_0_10),
    .O(U7_U3__n0000_0_13)
  );
  AND2 U7_U3__n0000_0_14_906 (
    .I0(U7_U3__n0000_0_6),
    .I1(U7_U3__n0000_0_11),
    .O(U7_U3__n0000_0_14)
  );
  AND2 U7_U3__n0000_0_15_907 (
    .I0(U7_U3__n0002[0]),
    .I1(U7_U3__n0000_0_12),
    .O(U7_U3__n0000_0_15)
  );
  AND2 U7_U3__n0000_0_16_908 (
    .I0(U7_U3_counterr[0]),
    .I1(U7_U3__n0000_0_13),
    .O(U7_U3__n0000_0_16)
  );
  INV U2__n00031_909 (
    .I(U2__n0000),
    .O(U2__n00031)
  );
  AND2 U2__n00051_910 (
    .I0(RD_IBUF),
    .I1(WR_IBUF),
    .O(U2__n00051)
  );
  INV U2__n00052_911 (
    .I(AS_IBUF),
    .O(U2__n00052)
  );
  AND2 U2__n00053_912 (
    .I0(U2_ASedge),
    .I1(U2__n00052),
    .O(U2__n00053)
  );
  INV U2_Enable_AD1_913 (
    .I(RD_IBUF),
    .O(U2_Enable_AD1)
  );
  AND2 U7_U3_Maddsub__n0002__n00021_914 (
    .I0(U7_U3_Maddsub__n0002__n0028[1]),
    .I1(U7_U3_counterr[2]),
    .O(U7_U3_Maddsub__n0002__n0002)
  );
  INV U7_U3_Maddsub__n0002__n00022_915 (
    .I(U7_U3_Maddsub__n0002__n0028[1]),
    .O(U7_U3_Maddsub__n0002__n00021)
  );
  INV U7_U3_Maddsub__n0002__n00023_916 (
    .I(U7_U3_counterr[2]),
    .O(U7_U3_Maddsub__n0002__n00022)
  );
  AND2 U7_U3_Maddsub__n0002__n00024_917 (
    .I0(U7_U3_Maddsub__n0002__n00021),
    .I1(U7_U3_Maddsub__n0002__n00022),
    .O(U7_U3_Maddsub__n0002__n00023)
  );
  INV U7_U3_Maddsub__n0002__n00025_918 (
    .I(U7_U3_Maddsub__n0002__n00023),
    .O(U7_U3_Maddsub__n0002__n00024)
  );
  AND2 U7_U3_Maddsub__n0002__n00026 (
    .I0(U7_U3_Maddsub__n0002__n0028[0]),
    .I1(U7_U3_Maddsub__n0002__n00024),
    .O(U7_U3_Maddsub__n0002__n00025)
  );
  AND2 U7_U3_Maddsub__n0002__n00011_919 (
    .I0(U7_U3_Maddsub__n0002__n0026[1]),
    .I1(U7_U3_counterr[1]),
    .O(U7_U3_Maddsub__n0002__n0001)
  );
  INV U7_U3_Maddsub__n0002__n00012_920 (
    .I(U7_U3_Maddsub__n0002__n0026[1]),
    .O(U7_U3_Maddsub__n0002__n00011)
  );
  INV U7_U3_Maddsub__n0002__n00013_921 (
    .I(U7_U3_counterr[1]),
    .O(U7_U3_Maddsub__n0002__n00012)
  );
  AND2 U7_U3_Maddsub__n0002__n00014_922 (
    .I0(U7_U3_Maddsub__n0002__n00011),
    .I1(U7_U3_Maddsub__n0002__n00012),
    .O(U7_U3_Maddsub__n0002__n00013)
  );
  INV U7_U3_Maddsub__n0002__n00015_923 (
    .I(U7_U3_Maddsub__n0002__n00013),
    .O(U7_U3_Maddsub__n0002__n00014)
  );
  AND2 U7_U3_Maddsub__n0002__n00016 (
    .I0(U7_U3_Maddsub__n0002__n0026[0]),
    .I1(U7_U3_Maddsub__n0002__n00014),
    .O(U7_U3_Maddsub__n0002__n00015)
  );
  AND2 U7_U3__n00411_924 (
    .I0(U7_SCLdetect),
    .I1(U7_Incdetect),
    .O(U7_U3__n00411)
  );
  INV U7_U3__n00412_925 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n00412)
  );
  INV U7_U3__n00413_926 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n00413)
  );
  AND2 U7_U3__n00414_927 (
    .I0(U7_ResetDetect),
    .I1(U7_U3__n00413),
    .O(U7_U3__n00414)
  );
  INV U7_U3__n00415_928 (
    .I(U7_U3__n00414),
    .O(U7_U3__n00415)
  );
  AND2 U7_U3__n00416_929 (
    .I0(U7_U3__n00412),
    .I1(U7_U3__n00415),
    .O(U7_U3__n00416)
  );
  AND2 U7_U3_Maddsub__n0002__n00031_930 (
    .I0(U7_U3_Maddsub__n0002__n0030[1]),
    .I1(U7_U3_counterr[3]),
    .O(U7_U3_Maddsub__n0002__n0003)
  );
  INV U7_U3_Maddsub__n0002__n00032_931 (
    .I(U7_U3_Maddsub__n0002__n0030[1]),
    .O(U7_U3_Maddsub__n0002__n00031)
  );
  INV U7_U3_Maddsub__n0002__n00033_932 (
    .I(U7_U3_counterr[3]),
    .O(U7_U3_Maddsub__n0002__n00032)
  );
  AND2 U7_U3_Maddsub__n0002__n00034_933 (
    .I0(U7_U3_Maddsub__n0002__n00031),
    .I1(U7_U3_Maddsub__n0002__n00032),
    .O(U7_U3_Maddsub__n0002__n00033)
  );
  INV U7_U3_Maddsub__n0002__n00035_934 (
    .I(U7_U3_Maddsub__n0002__n00033),
    .O(U7_U3_Maddsub__n0002__n00034)
  );
  AND2 U7_U3_Maddsub__n0002__n00036 (
    .I0(U7_U3_Maddsub__n0002__n0030[0]),
    .I1(U7_U3_Maddsub__n0002__n00034),
    .O(U7_U3_Maddsub__n0002__n00035)
  );
  AND2 U7_U3__n0000_5_1_935 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0049[5]),
    .O(U7_U3__n0000_5_1)
  );
  INV U7_U3__n0000_5_2_936 (
    .I(NET1764),
    .O(U7_U3__n0000_5_2)
  );
  INV U7_U3__n0000_5_3_937 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_5_3)
  );
  INV U7_U3__n0000_5_4_938 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_5_4)
  );
  INV U7_U3__n0000_5_5_939 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_5_5)
  );
  AND2 U7_U3__n0000_5_6_940 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_5_2),
    .O(U7_U3__n0000_5_6)
  );
  AND4 U7_U3__n0000_5_7_941 (
    .I0(U7_U3_counterr[5]),
    .I1(U7_U3__n0000_5_3),
    .I2(U7_U3__n0000_5_4),
    .I3(U7_U3__n0000_5_5),
    .O(U7_U3__n0000_5_7)
  );
  OR2 U7_U3__n0000_5_8_942 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_5_6),
    .O(U7_U3__n0000_5_8)
  );
  AND2 U7_U3__n0000_5_9_943 (
    .I0(U7_U3__n0002[5]),
    .I1(U7_U3__n0000_5_8),
    .O(U7_U3__n0000_5_9)
  );
  INV U7_U3__n00061_944 (
    .I(U7_Incdetect),
    .O(U7_U3__n00061)
  );
  INV U7_U3__n00062_945 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n00062)
  );
  AND2 U7_U3__n0000_4_1_946 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0049[4]),
    .O(U7_U3__n0000_4_1)
  );
  INV U7_U3__n0000_4_2_947 (
    .I(NET1764),
    .O(U7_U3__n0000_4_2)
  );
  INV U7_U3__n0000_4_3_948 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_4_3)
  );
  INV U7_U3__n0000_4_4_949 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_4_4)
  );
  INV U7_U3__n0000_4_5_950 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_4_5)
  );
  AND2 U7_U3__n0000_4_6_951 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_4_2),
    .O(U7_U3__n0000_4_6)
  );
  AND4 U7_U3__n0000_4_7_952 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3__n0000_4_3),
    .I2(U7_U3__n0000_4_4),
    .I3(U7_U3__n0000_4_5),
    .O(U7_U3__n0000_4_7)
  );
  OR2 U7_U3__n0000_4_8_953 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_4_6),
    .O(U7_U3__n0000_4_8)
  );
  AND2 U7_U3__n0000_4_9_954 (
    .I0(U7_U3__n0002[4]),
    .I1(U7_U3__n0000_4_8),
    .O(U7_U3__n0000_4_9)
  );
  AND3 U3__n00611_955 (
    .I0(Bus_Select_IBUF),
    .I1(SA_4_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n0061)
  );
  INV U3__n00612_956 (
    .I(Bus_Select_IBUF),
    .O(U3__n00611)
  );
  INV U3__n00613_957 (
    .I(U2_ADDR_reg[4]),
    .O(U3__n00612)
  );
  AND2 U3__n00614 (
    .I0(U3__n00611),
    .I1(U3__n00612),
    .O(U3__n00613)
  );
  INV U3__n00581_958 (
    .I(Bus_Select_IBUF),
    .O(U3__n0058)
  );
  AND3 U3__n00582_959 (
    .I0(Bus_Select_IBUF),
    .I1(SA_5_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n00581)
  );
  AND2 U3__n00583 (
    .I0(U3__n0000[1]),
    .I1(U3__n0058),
    .O(U3__n00582)
  );
  INV U3__n00551_960 (
    .I(Bus_Select_IBUF),
    .O(U3__n0055)
  );
  AND3 U3__n00552_961 (
    .I0(Bus_Select_IBUF),
    .I1(SA_6_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n00551)
  );
  AND2 U3__n00553 (
    .I0(U3__n0000[2]),
    .I1(U3__n0055),
    .O(U3__n00552)
  );
  INV U3__n00521_962 (
    .I(Bus_Select_IBUF),
    .O(U3__n0052)
  );
  AND3 U3__n00522_963 (
    .I0(Bus_Select_IBUF),
    .I1(SA_7_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n00521)
  );
  AND2 U3__n00523 (
    .I0(U3__n0000[3]),
    .I1(U3__n0052),
    .O(U3__n00522)
  );
  INV U3__n00491_964 (
    .I(Bus_Select_IBUF),
    .O(U3__n0049)
  );
  AND3 U3__n00492_965 (
    .I0(Bus_Select_IBUF),
    .I1(SA_0_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n00491)
  );
  AND2 U3__n00493 (
    .I0(U2_ADDR_reg[0]),
    .I1(U3__n0049),
    .O(U3__n00492)
  );
  INV U3__n00461_966 (
    .I(Bus_Select_IBUF),
    .O(U3__n0046)
  );
  AND3 U3__n00462_967 (
    .I0(Bus_Select_IBUF),
    .I1(SA_1_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n00461)
  );
  AND2 U3__n00463 (
    .I0(U2_ADDR_reg[1]),
    .I1(U3__n0046),
    .O(U3__n00462)
  );
  INV U3__n00401_968 (
    .I(Bus_Select_IBUF),
    .O(U3__n0040)
  );
  AND3 U3__n00402_969 (
    .I0(Bus_Select_IBUF),
    .I1(SA_3_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n00401)
  );
  AND2 U3__n00403 (
    .I0(U2_ADDR_reg[3]),
    .I1(U3__n0040),
    .O(U3__n00402)
  );
  AND2 U3__n00281_970 (
    .I0(UIOW_OBUF),
    .I1(U3__n0015),
    .O(U3__n00281)
  );
  INV U3__n00282_971 (
    .I(UIOR_OBUF),
    .O(U3__n00282)
  );
  INV U7_U3_Maddsub__n0002__n00041_972 (
    .I(U7_U3_Maddsub__n0002__n0019),
    .O(U7_U3_Maddsub__n0002__n0004)
  );
  INV U7_U3_Maddsub__n0002__n00042_973 (
    .I(U7_U3_Maddsub__n0002__n0018),
    .O(U7_U3_Maddsub__n0002__n00041)
  );
  INV U7_U3_Maddsub__n0002__n00043_974 (
    .I(U7_U3_Maddsub__n0002__n0017),
    .O(U7_U3_Maddsub__n0002__n00042)
  );
  AND3 U7_U3_Maddsub__n0002__n00044 (
    .I0(U7_U3_Maddsub__n0002__n00041),
    .I1(U7_U3_Maddsub__n0002__n0004),
    .I2(U7_U3_Maddsub__n0002__n00042),
    .O(U7_U3_Maddsub__n0002__n00043)
  );
  INV U7_U3__n0000_3_1_975 (
    .I(NET1764),
    .O(U7_U3__n0000_3_1)
  );
  INV U7_U3__n0000_3_2_976 (
    .I(U7_U3_counterr[3]),
    .O(U7_U3__n0000_3_2)
  );
  INV U7_U3__n0000_3_3_977 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_3_3)
  );
  INV U7_U3__n0000_3_4_978 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_3_4)
  );
  AND2 U7_U3__n0000_3_5_979 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_3_1),
    .O(U7_U3__n0000_3_5)
  );
  AND2 U7_U3__n0000_3_6_980 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_3_2),
    .O(U7_U3__n0000_3_6)
  );
  AND3 U7_U3__n0000_3_7_981 (
    .I0(U7_U3__n0000_3_3),
    .I1(U7_U3_counterr[3]),
    .I2(U7_U3__n0000_3_4),
    .O(U7_U3__n0000_3_7)
  );
  OR2 U7_U3__n0000_3_8_982 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_3_5),
    .O(U7_U3__n0000_3_8)
  );
  OR2 U7_U3__n0000_3_9_983 (
    .I0(U7_U3__n0000_3_6),
    .I1(U7_U3__n0000_3_7),
    .O(U7_U3__n0000_3_9)
  );
  AND2 U7_U3__n0000_3_10_984 (
    .I0(U7_U3__n0002[3]),
    .I1(U7_U3__n0000_3_8),
    .O(U7_U3__n0000_3_10)
  );
  AND3 U3__n00151_985 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_ADDR_reg[5]),
    .I2(U2_ADDR_reg[6]),
    .O(U3__n00151)
  );
  INV U3__n00152_986 (
    .I(Bus_Select_IBUF),
    .O(U3__n00152)
  );
  AND2 U3__n00153_987 (
    .I0(U3_Mcompar__n0011__n0014),
    .I1(Bus_Select_IBUF),
    .O(U3__n00153)
  );
  INV U3__n00154_988 (
    .I(AEN_IBUF),
    .O(U3__n00154)
  );
  OR2 U3__n00155_989 (
    .I0(U2_ADDR_reg[7]),
    .I1(U3__n00151),
    .O(U3__n00155)
  );
  AND2 U3__n00156_990 (
    .I0(U3__n00153),
    .I1(U3__n00154),
    .O(U3__n00156)
  );
  AND2 U3__n00157_991 (
    .I0(U3__n00155),
    .I1(U3__n00152),
    .O(U3__n00157)
  );
  AND2 U7_U3_Maddsub__n0002__n00001_992 (
    .I0(U7_U3__n0006),
    .I1(U7_U3_counterr[0]),
    .O(U7_U3_Maddsub__n0002__n0000)
  );
  INV U7_U3_Maddsub__n0002__n00002_993 (
    .I(U7_U3__n0006),
    .O(U7_U3_Maddsub__n0002__n00001)
  );
  INV U7_U3_Maddsub__n0002__n00003_994 (
    .I(U7_U3_counterr[0]),
    .O(U7_U3_Maddsub__n0002__n00002)
  );
  AND2 U7_U3_Maddsub__n0002__n00004_995 (
    .I0(U7_U3_Maddsub__n0002__n00001),
    .I1(U7_U3_Maddsub__n0002__n00002),
    .O(U7_U3_Maddsub__n0002__n00003)
  );
  INV U7_U3_Maddsub__n0002__n00005_996 (
    .I(U7_U3_Maddsub__n0002__n00003),
    .O(U7_U3_Maddsub__n0002__n00004)
  );
  AND2 U7_U3_Maddsub__n0002__n00006 (
    .I0(U7_U3_Maddsub__n0002__n0020),
    .I1(U7_U3_Maddsub__n0002__n00004),
    .O(U7_U3_Maddsub__n0002__n00005)
  );
  INV U3__n00431_997 (
    .I(Bus_Select_IBUF),
    .O(U3__n0043)
  );
  AND3 U3__n00432_998 (
    .I0(Bus_Select_IBUF),
    .I1(SA_2_IBUF),
    .I2(U3_Mcompar__n0011__n0014),
    .O(U3__n00431)
  );
  AND2 U3__n00433 (
    .I0(U2_ADDR_reg[2]),
    .I1(U3__n0043),
    .O(U3__n00432)
  );
  AND2 U3__n0004_7_1_999 (
    .I0(Bus_Select_IBUF),
    .I1(N8872),
    .O(U3__n0004_7_1)
  );
  INV U3__n0004_7_2_1000 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_7_2)
  );
  INV U3__n0004_7_3_1001 (
    .I(UIOW_OBUF),
    .O(U3__n0004_7_3)
  );
  AND2 U3__n0004_7_4_1002 (
    .I0(N8856),
    .I1(U3__n0004_7_2),
    .O(U3__n0004_7_4)
  );
  OR2 U3__n0004_7_5_1003 (
    .I0(U3__n0004_7_1),
    .I1(U3__n0004_7_4),
    .O(U3__n0004_7_5)
  );
  AND2 U3_Mmux_UIOR_Result1_1004 (
    .I0(Bus_Select_IBUF),
    .I1(IORD_IBUF),
    .O(U3_Mmux_UIOR_Result)
  );
  INV U3_Mmux_UIOR_Result2_1005 (
    .I(Bus_Select_IBUF),
    .O(U3_Mmux_UIOR_Result1)
  );
  INV U3_Mmux_UIOR_Result3_1006 (
    .I(U3__n0015),
    .O(U3_Mmux_UIOR_Result2)
  );
  AND2 U3_Mmux_UIOR_Result4 (
    .I0(RD_IBUF),
    .I1(U3_Mmux_UIOR_Result1),
    .O(U3_Mmux_UIOR_Result3)
  );
  AND2 U3_Mmux_UIOW_Result1_1007 (
    .I0(Bus_Select_IBUF),
    .I1(IOWR_IBUF),
    .O(U3_Mmux_UIOW_Result)
  );
  INV U3_Mmux_UIOW_Result2_1008 (
    .I(Bus_Select_IBUF),
    .O(U3_Mmux_UIOW_Result1)
  );
  INV U3_Mmux_UIOW_Result3_1009 (
    .I(U3__n0015),
    .O(U3_Mmux_UIOW_Result2)
  );
  AND2 U3_Mmux_UIOW_Result4 (
    .I0(WR_IBUF),
    .I1(U3_Mmux_UIOW_Result1),
    .O(U3_Mmux_UIOW_Result3)
  );
  AND2 U3__n0004_0_1_1010 (
    .I0(Bus_Select_IBUF),
    .I1(N8858),
    .O(U3__n0004_0_1)
  );
  INV U3__n0004_0_2_1011 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_0_2)
  );
  INV U3__n0004_0_3_1012 (
    .I(UIOW_OBUF),
    .O(U3__n0004_0_3)
  );
  AND2 U3__n0004_0_4_1013 (
    .I0(N8890),
    .I1(U3__n0004_0_2),
    .O(U3__n0004_0_4)
  );
  OR2 U3__n0004_0_5_1014 (
    .I0(U3__n0004_0_1),
    .I1(U3__n0004_0_4),
    .O(U3__n0004_0_5)
  );
  AND2 U3__n0004_1_1_1015 (
    .I0(Bus_Select_IBUF),
    .I1(N8860),
    .O(U3__n0004_1_1)
  );
  INV U3__n0004_1_2_1016 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_1_2)
  );
  INV U3__n0004_1_3_1017 (
    .I(UIOW_OBUF),
    .O(U3__n0004_1_3)
  );
  AND2 U3__n0004_1_4_1018 (
    .I0(N8894),
    .I1(U3__n0004_1_2),
    .O(U3__n0004_1_4)
  );
  OR2 U3__n0004_1_5_1019 (
    .I0(U3__n0004_1_1),
    .I1(U3__n0004_1_4),
    .O(U3__n0004_1_5)
  );
  AND2 U3__n0004_2_1_1020 (
    .I0(Bus_Select_IBUF),
    .I1(N8862),
    .O(U3__n0004_2_1)
  );
  INV U3__n0004_2_2_1021 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_2_2)
  );
  INV U3__n0004_2_3_1022 (
    .I(UIOW_OBUF),
    .O(U3__n0004_2_3)
  );
  AND2 U3__n0004_2_4_1023 (
    .I0(N8896),
    .I1(U3__n0004_2_2),
    .O(U3__n0004_2_4)
  );
  OR2 U3__n0004_2_5_1024 (
    .I0(U3__n0004_2_1),
    .I1(U3__n0004_2_4),
    .O(U3__n0004_2_5)
  );
  AND2 U3__n0004_3_1_1025 (
    .I0(Bus_Select_IBUF),
    .I1(N8864),
    .O(U3__n0004_3_1)
  );
  INV U3__n0004_3_2_1026 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_3_2)
  );
  INV U3__n0004_3_3_1027 (
    .I(UIOW_OBUF),
    .O(U3__n0004_3_3)
  );
  AND2 U3__n0004_3_4_1028 (
    .I0(N8898),
    .I1(U3__n0004_3_2),
    .O(U3__n0004_3_4)
  );
  OR2 U3__n0004_3_5_1029 (
    .I0(U3__n0004_3_1),
    .I1(U3__n0004_3_4),
    .O(U3__n0004_3_5)
  );
  AND2 U3__n0004_4_1_1030 (
    .I0(Bus_Select_IBUF),
    .I1(N8866),
    .O(U3__n0004_4_1)
  );
  INV U3__n0004_4_2_1031 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_4_2)
  );
  INV U3__n0004_4_3_1032 (
    .I(UIOW_OBUF),
    .O(U3__n0004_4_3)
  );
  AND2 U3__n0004_4_4_1033 (
    .I0(N8900),
    .I1(U3__n0004_4_2),
    .O(U3__n0004_4_4)
  );
  OR2 U3__n0004_4_5_1034 (
    .I0(U3__n0004_4_1),
    .I1(U3__n0004_4_4),
    .O(U3__n0004_4_5)
  );
  AND2 U3__n0004_5_1_1035 (
    .I0(Bus_Select_IBUF),
    .I1(N8868),
    .O(U3__n0004_5_1)
  );
  INV U3__n0004_5_2_1036 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_5_2)
  );
  INV U3__n0004_5_3_1037 (
    .I(UIOW_OBUF),
    .O(U3__n0004_5_3)
  );
  AND2 U3__n0004_5_4_1038 (
    .I0(N8852),
    .I1(U3__n0004_5_2),
    .O(U3__n0004_5_4)
  );
  OR2 U3__n0004_5_5_1039 (
    .I0(U3__n0004_5_1),
    .I1(U3__n0004_5_4),
    .O(U3__n0004_5_5)
  );
  AND2 U3__n0004_6_1_1040 (
    .I0(Bus_Select_IBUF),
    .I1(N8870),
    .O(U3__n0004_6_1)
  );
  INV U3__n0004_6_2_1041 (
    .I(Bus_Select_IBUF),
    .O(U3__n0004_6_2)
  );
  INV U3__n0004_6_3_1042 (
    .I(UIOW_OBUF),
    .O(U3__n0004_6_3)
  );
  AND2 U3__n0004_6_4_1043 (
    .I0(N8854),
    .I1(U3__n0004_6_2),
    .O(U3__n0004_6_4)
  );
  OR2 U3__n0004_6_5_1044 (
    .I0(U3__n0004_6_1),
    .I1(U3__n0004_6_4),
    .O(U3__n0004_6_5)
  );
  INV U3__n00031_1045 (
    .I(UIOR_OBUF),
    .O(U3__n00031)
  );
  INV U3__n00032_1046 (
    .I(Bus_Select_IBUF),
    .O(U3__n00032)
  );
  AND2 U3__n00021_1047 (
    .I0(Bus_Select_IBUF),
    .I1(U3_Mcompar__n0011__n0014),
    .O(U3__n00021)
  );
  INV U3__n00022_1048 (
    .I(AEN_IBUF),
    .O(U3__n00022)
  );
  INV U3__n00023_1049 (
    .I(IORD_IBUF),
    .O(U3__n00023)
  );
  AND2 U3__n00024_1050 (
    .I0(U3__n00022),
    .I1(U3__n00023),
    .O(U3__n00024)
  );
  INV U3__n00011 (
    .I(UINT_IBUF),
    .O(U3__n0001)
  );
  INV U7_U3__n0000_1_1_1051 (
    .I(NET1764),
    .O(U7_U3__n0000_1_1)
  );
  INV U7_U3__n0000_1_2_1052 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_1_2)
  );
  INV U7_U3__n0000_1_3_1053 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_1_3)
  );
  INV U7_U3__n0000_1_4_1054 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_1_4)
  );
  INV U7_U3__n0000_1_5_1055 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n0000_1_5)
  );
  AND2 U7_U3__n0000_1_6_1056 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_1_1),
    .O(U7_U3__n0000_1_6)
  );
  AND3 U7_U3__n0000_1_7_1057 (
    .I0(U7_U3__n0000_1_3),
    .I1(U7_U3__n0000_1_2),
    .I2(U7_U3__n0000_1_4),
    .O(U7_U3__n0000_1_7)
  );
  AND2 U7_U3__n0000_1_8_1058 (
    .I0(SCLreset_IBUF),
    .I1(U7_U3__n0000_1_5),
    .O(U7_U3__n0000_1_8)
  );
  OR2 U7_U3__n0000_1_9_1059 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_1_6),
    .O(U7_U3__n0000_1_9)
  );
  OR2 U7_U3__n0000_1_10_1060 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_1_7),
    .O(U7_U3__n0000_1_10)
  );
  AND2 U7_U3__n0000_1_11_1061 (
    .I0(U7_U3__n0002[1]),
    .I1(U7_U3__n0000_1_9),
    .O(U7_U3__n0000_1_11)
  );
  AND2 U7_U3__n0000_1_12_1062 (
    .I0(U7_U3_counterr[1]),
    .I1(U7_U3__n0000_1_10),
    .O(U7_U3__n0000_1_12)
  );
  INV U7_U3__n00051_1063 (
    .I(U7_U3_counterr[1]),
    .O(U7_U3__n0005)
  );
  INV U7_U3__n00052_1064 (
    .I(U7_U3_counterr[0]),
    .O(U7_U3__n00051)
  );
  INV U7_U3__n00053_1065 (
    .I(U7_U3_counterr[2]),
    .O(U7_U3__n00052)
  );
  INV U7_U3__n00054_1066 (
    .I(U7_U3_counterr[4]),
    .O(U7_U3__n00053)
  );
  INV U7_U3__n00055_1067 (
    .I(U7_U3_counterr[3]),
    .O(U7_U3__n00054)
  );
  INV U7_U3__n00056 (
    .I(U7_U3_counterr[5]),
    .O(U7_U3__n00055)
  );
  INV U3_Mcompar__n0011__n00141_1068 (
    .I(U3_Mcompar__n0011__n0011),
    .O(U3_Mcompar__n0011__n00141)
  );
  INV U3_Mcompar__n0011__n00142_1069 (
    .I(U3_Mcompar__n0011__n0010),
    .O(U3_Mcompar__n0011__n00142)
  );
  INV U3_Mcompar__n0011__n00143_1070 (
    .I(U3_Mcompar__n0011__n0013),
    .O(U3_Mcompar__n0011__n00143)
  );
  INV U3_Mcompar__n0011__n00144_1071 (
    .I(U3_Mcompar__n0011__n0008),
    .O(U3_Mcompar__n0011__n00144)
  );
  INV U3_Mcompar__n0011__n00145_1072 (
    .I(U3_Mcompar__n0011__n0007),
    .O(U3_Mcompar__n0011__n00145)
  );
  INV U3_Mcompar__n0011__n00146_1073 (
    .I(U3_Mcompar__n0011__n0006),
    .O(U3_Mcompar__n0011__n00146)
  );
  INV U3_Mcompar__n0011__n00147_1074 (
    .I(U3_Mcompar__n0011__n0009),
    .O(U3_Mcompar__n0011__n00147)
  );
  INV U3_Mcompar__n0011__n00148_1075 (
    .I(U3_Mcompar__n0011__n0012),
    .O(U3_Mcompar__n0011__n00148)
  );
  INV U3_PC104reg_7__n00021_1076 (
    .I(NET4340),
    .O(U3_PC104reg_7__n00021)
  );
  AND2 U3_PC104reg_7__n00022_1077 (
    .I0(CPLD_Reset_IBUF),
    .I1(U3_PC104reg_7__n00021),
    .O(U3_PC104reg_7__n00022)
  );
  IBUF SMCLK_IBUF_1078 (
    .I(SMCLK),
    .O(SMCLK_IBUF)
  );
  IBUF AS_IBUF_1079 (
    .I(AS),
    .O(AS_IBUF)
  );
  IBUF AM2Status_IBUF_1080 (
    .I(AM2Status),
    .O(AM2Status_IBUF)
  );
  IBUF IOWR_IBUF_1081 (
    .I(IOWR),
    .O(IOWR_IBUF)
  );
  IBUF AM1Status_IBUF_1082 (
    .I(AM1Status),
    .O(AM1Status_IBUF)
  );
  IBUF AM0Status_IBUF_1083 (
    .I(AM0Status),
    .O(AM0Status_IBUF)
  );
  IBUF SystemStatus_IBUF_1084 (
    .I(SystemStatus),
    .O(SystemStatus_IBUF)
  );
  IBUF ExternalStatus_IBUF_1085 (
    .I(ExternalStatus),
    .O(ExternalStatus_IBUF)
  );
  IBUF ModemStatus_IBUF_1086 (
    .I(ModemStatus),
    .O(ModemStatus_IBUF)
  );
  IBUF RD_IBUF_1087 (
    .I(RD),
    .O(RD_IBUF)
  );
  IBUF Bus_Select_IBUF_1088 (
    .I(Bus_Select),
    .O(Bus_Select_IBUF)
  );
  IBUF AEN_IBUF_1089 (
    .I(AEN),
    .O(AEN_IBUF)
  );
  IBUF WR_IBUF_1090 (
    .I(WR),
    .O(WR_IBUF)
  );
  IBUF CameraStatus_IBUF_1091 (
    .I(CameraStatus),
    .O(CameraStatus_IBUF)
  );
  IBUF SCLreset_IBUF_1092 (
    .I(SCLreset),
    .O(SCLreset_IBUF)
  );
  IBUF CPLD_Reset_IBUF_1093 (
    .I(CPLD_Reset),
    .O(CPLD_Reset_IBUF)
  );
  IBUF SCLinc_IBUF_1094 (
    .I(SCLinc),
    .O(SCLinc_IBUF)
  );
  IBUF UINT_IBUF_1095 (
    .I(UINT),
    .O(UINT_IBUF)
  );
  IBUF IORD_IBUF_1096 (
    .I(IORD),
    .O(IORD_IBUF)
  );
  IBUF SA_15_IBUF_1097 (
    .I(SA[15]),
    .O(SA_15_IBUF)
  );
  IBUF SA_14_IBUF_1098 (
    .I(SA[14]),
    .O(SA_14_IBUF)
  );
  IBUF SA_13_IBUF_1099 (
    .I(SA[13]),
    .O(SA_13_IBUF)
  );
  IBUF SA_12_IBUF_1100 (
    .I(SA[12]),
    .O(SA_12_IBUF)
  );
  IBUF SA_11_IBUF_1101 (
    .I(SA[11]),
    .O(SA_11_IBUF)
  );
  IBUF SA_10_IBUF_1102 (
    .I(SA[10]),
    .O(SA_10_IBUF)
  );
  IBUF SA_9_IBUF_1103 (
    .I(SA[9]),
    .O(SA_9_IBUF)
  );
  IBUF SA_8_IBUF_1104 (
    .I(SA[8]),
    .O(SA_8_IBUF)
  );
  IBUF SA_7_IBUF_1105 (
    .I(SA[7]),
    .O(SA_7_IBUF)
  );
  IBUF SA_6_IBUF_1106 (
    .I(SA[6]),
    .O(SA_6_IBUF)
  );
  IBUF SA_5_IBUF_1107 (
    .I(SA[5]),
    .O(SA_5_IBUF)
  );
  IBUF SA_4_IBUF_1108 (
    .I(SA[4]),
    .O(SA_4_IBUF)
  );
  IBUF SA_3_IBUF_1109 (
    .I(SA[3]),
    .O(SA_3_IBUF)
  );
  IBUF SA_2_IBUF_1110 (
    .I(SA[2]),
    .O(SA_2_IBUF)
  );
  IBUF SA_1_IBUF_1111 (
    .I(SA[1]),
    .O(SA_1_IBUF)
  );
  IBUF SA_0_IBUF_1112 (
    .I(SA[0]),
    .O(SA_0_IBUF)
  );
  OBUF IRQ_OBUF_1113 (
    .I(IRQ_OBUF),
    .O(IRQ)
  );
  OBUF UIOW_OBUF_1114 (
    .I(UIOW_OBUF),
    .O(UIOW)
  );
  OBUF ModemEN_OBUF_1115 (
    .I(ModemEN_OBUF),
    .O(ModemEN)
  );
  OBUF AM2EN_OBUF_1116 (
    .I(AM2EN_OBUF),
    .O(AM2EN)
  );
  OBUF LOOPcon0_OBUF_1117 (
    .I(LOOPcon0_OBUF),
    .O(LOOPcon0)
  );
  OBUF LOOPcon1_OBUF_1118 (
    .I(LOOPcon1_OBUF),
    .O(LOOPcon1)
  );
  OBUF LOOPcon2_OBUF_1119 (
    .I(LOOPcon2_OBUF),
    .O(LOOPcon2)
  );
  OBUF UCS_OBUF_1120 (
    .I(UCS_OBUF),
    .O(UCS)
  );
  OBUF CONmodem_OBUF_1121 (
    .I(CONmodem_OBUF),
    .O(CONmodem)
  );
  OBUF CameraEN_OBUF_1122 (
    .I(CameraEN_OBUF),
    .O(CameraEN)
  );
  OBUF LOOPmodem_OBUF_1123 (
    .I(LOOPmodem_OBUF),
    .O(LOOPmodem)
  );
  OBUF ExternalEN_OBUF_1124 (
    .I(ExternalEN_OBUF),
    .O(ExternalEN)
  );
  OBUF CONextr_OBUF_1125 (
    .I(CONextr_OBUF),
    .O(CONextr)
  );
  OBUF DwarfEN_OBUF_1126 (
    .I(DwarfEN_OBUF),
    .O(DwarfEN)
  );
  OBUF AM0EN_OBUF_1127 (
    .I(AM0EN_OBUF),
    .O(AM0EN)
  );
  OBUF CONcon0_OBUF_1128 (
    .I(CONcon0_OBUF),
    .O(CONcon0)
  );
  OBUF CONcon1_OBUF_1129 (
    .I(CONcon1_OBUF),
    .O(CONcon1)
  );
  OBUF CONcon2_OBUF_1130 (
    .I(CONcon2_OBUF),
    .O(CONcon2)
  );
  OBUF LOOPextr_OBUF_1131 (
    .I(LOOPextr_OBUF),
    .O(LOOPextr)
  );
  OBUF SystemEN_OBUF_1132 (
    .I(SystemEN_OBUF),
    .O(SystemEN)
  );
  OBUF AM1EN_OBUF_1133 (
    .I(AM1EN_OBUF),
    .O(AM1EN)
  );
  OBUF INT_OBUF_1134 (
    .I(INT_OBUF),
    .O(INT)
  );
  OBUF SYSPWR_OBUF_1135 (
    .I(SYSPWR_OBUF),
    .O(SYSPWR)
  );
  OBUF UIOR_OBUF_1136 (
    .I(UIOR_OBUF),
    .O(UIOR)
  );
  OBUF UAD_7_OBUF_1137 (
    .I(UAD_7_OBUF),
    .O(UAD[7])
  );
  OBUF UAD_6_OBUF_1138 (
    .I(UAD_6_OBUF),
    .O(UAD[6])
  );
  OBUF UAD_5_OBUF_1139 (
    .I(UAD_5_OBUF),
    .O(UAD[5])
  );
  OBUF UAD_4_OBUF_1140 (
    .I(UAD_4_OBUF),
    .O(UAD[4])
  );
  OBUF UAD_3_OBUF_1141 (
    .I(UAD_3_OBUF),
    .O(UAD[3])
  );
  OBUF UAD_2_OBUF_1142 (
    .I(UAD_2_OBUF),
    .O(UAD[2])
  );
  OBUF UAD_1_OBUF_1143 (
    .I(UAD_1_OBUF),
    .O(UAD[1])
  );
  OBUF UAD_0_OBUF_1144 (
    .I(UAD_0_OBUF),
    .O(UAD[0])
  );
  OBUF EN_7_OBUF_1145 (
    .I(EN_7_OBUF),
    .O(EN[7])
  );
  OBUF EN_6_OBUF_1146 (
    .I(EN_6_OBUF),
    .O(EN[6])
  );
  OBUF EN_5_OBUF_1147 (
    .I(EN_5_OBUF),
    .O(EN[5])
  );
  OBUF EN_4_OBUF_1148 (
    .I(EN_4_OBUF),
    .O(EN[4])
  );
  OBUF EN_3_OBUF_1149 (
    .I(EN_3_OBUF),
    .O(EN[3])
  );
  OBUF EN_2_OBUF_1150 (
    .I(EN_2_OBUF),
    .O(EN[2])
  );
  OBUF EN_1_OBUF_1151 (
    .I(EN_1_OBUF),
    .O(EN[1])
  );
  OBUF EN_0_OBUF_1152 (
    .I(EN_0_OBUF),
    .O(EN[0])
  );
  OBUF PD_7_OBUF_1153 (
    .I(PD_7_OBUF),
    .O(PD[7])
  );
  OBUF PD_6_OBUF_1154 (
    .I(PD_6_OBUF),
    .O(PD[6])
  );
  OBUF PD_5_OBUF_1155 (
    .I(PD_5_OBUF),
    .O(PD[5])
  );
  OBUF PD_4_OBUF_1156 (
    .I(PD_4_OBUF),
    .O(PD[4])
  );
  OBUF PD_3_OBUF_1157 (
    .I(PD_3_OBUF),
    .O(PD[3])
  );
  OBUF PD_2_OBUF_1158 (
    .I(PD_2_OBUF),
    .O(PD[2])
  );
  OBUF PD_1_OBUF_1159 (
    .I(PD_1_OBUF),
    .O(PD[1])
  );
  OBUF PD_0_OBUF_1160 (
    .I(PD_0_OBUF),
    .O(PD[0])
  );
endmodule