[Project]
Current Flow=Multivendor
VCS=0
version=1
Current Config=compile

[Configurations]
compile=sleeptTB

[Library]
sleeptTB=.\sleeptTB.lib

[$LibMap$]
sleeptTB=.
Active_lib=

[Settings]
FLOW_TYPE=HDL
LANGUAGE=VERILOG
REFRESH_FLOW=1
SYNTH_TOOL=<none>
IMPL_TOOL=<none>
FAMILY=
FLOWTOOLS=ONLY_IMPL
HESPrepare=0

[IMPLEMENTATION]
UCF=

[Files]
/c:\projects\genosensor\2g\cplds\sleepy\sleepypld\implement\time_sim.v=-1
/C:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\SleepyTB.bde=-1
/C:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\msp.v=-1

[Files.Data]
c:\projects\genosensor\2g\cplds\sleepy\sleepypld\implement\time_sim.v=Verilog Source Code
C:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\SleepyTB.bde=Block Diagram
.\compile\SleepyTB.v=Verilog Source Code
C:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\msp.v=Verilog Source Code

[HierarchyViewer]
SortInfo=u
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=

[file_out:/C:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\SleepyTB.bde]
/\compile\SleepyTB.v=-1