<Project ModBy="Inserter" SigType="0" Name="C:/Users/rawa/Desktop/FPGA_PC104/Reveal/pc104_debug.rvl" Date="2015-03-17">
    <IP Version="1_5_062609"/>
    <Design DesignEntry="Schematic/VHDL" Synthesis="lse" DeviceFamily="MachXO2" DesignName="PC104"/>
    <Core InsertDataset="0" Insert="1" Reveal_sig="2095271517" Name="top_level_LA0" ID="0">
        <Setting>
            <Clock SampleClk="clock" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="1024"/>
            <Capture Mode="0" MinSamplesPerTrig="8"/>
            <Event CntEnable="0" MaxEventCnt="8"/>
            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_top_level_LA0_net"/>
            <DistRAM Disable="0"/>
        </Setting>
        <Dataset Name="Base">
            <Trace>
                <Sig Type="SIG" Name="lpc3141_b_n_stcs1_ipad"/>
                <Sig Type="SIG" Name="lpc3141_b_n_oe_ipad"/>
                <Sig Type="SIG" Name="lpc3141_b_n_we_ipad"/>
                <Bus Name="lpc3141_ba_ipads">
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:0"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:1"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:2"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:3"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:4"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:5"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:6"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:7"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:8"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:9"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:10"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:11"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:12"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:13"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:14"/>
                    <Sig Type="SIG" Name="lpc3141_ba_ipads:15"/>
                </Bus>
                <Sig Type="SIG" Name="drive_cpu_bus"/>
                <Sig Type="SIG" Name="drive_enet_bus"/>
                <Sig Type="SIG" Name="enet_cs_n_opad"/>
                <Sig Type="SIG" Name="enet_cmd_opad"/>
                <Sig Type="SIG" Name="enet_rd_n_opad"/>
                <Sig Type="SIG" Name="enet_wr_n_opad"/>
                <Sig Type="SIG" Name="select_enet"/>
                <Bus Name="from_enet">
                    <Sig Type="SIG" Name="from_enet:0"/>
                    <Sig Type="SIG" Name="from_enet:1"/>
                    <Sig Type="SIG" Name="from_enet:2"/>
                    <Sig Type="SIG" Name="from_enet:3"/>
                    <Sig Type="SIG" Name="from_enet:4"/>
                    <Sig Type="SIG" Name="from_enet:5"/>
                    <Sig Type="SIG" Name="from_enet:6"/>
                    <Sig Type="SIG" Name="from_enet:7"/>
                    <Sig Type="SIG" Name="from_enet:8"/>
                    <Sig Type="SIG" Name="from_enet:9"/>
                    <Sig Type="SIG" Name="from_enet:10"/>
                    <Sig Type="SIG" Name="from_enet:11"/>
                    <Sig Type="SIG" Name="from_enet:12"/>
                    <Sig Type="SIG" Name="from_enet:13"/>
                    <Sig Type="SIG" Name="from_enet:14"/>
                    <Sig Type="SIG" Name="from_enet:15"/>
                </Bus>
                <Bus Name="to_lpc3141">
                    <Sig Type="SIG" Name="to_lpc3141:0"/>
                    <Sig Type="SIG" Name="to_lpc3141:1"/>
                    <Sig Type="SIG" Name="to_lpc3141:2"/>
                    <Sig Type="SIG" Name="to_lpc3141:3"/>
                    <Sig Type="SIG" Name="to_lpc3141:4"/>
                    <Sig Type="SIG" Name="to_lpc3141:5"/>
                    <Sig Type="SIG" Name="to_lpc3141:6"/>
                    <Sig Type="SIG" Name="to_lpc3141:7"/>
                    <Sig Type="SIG" Name="to_lpc3141:8"/>
                    <Sig Type="SIG" Name="to_lpc3141:9"/>
                    <Sig Type="SIG" Name="to_lpc3141:10"/>
                    <Sig Type="SIG" Name="to_lpc3141:11"/>
                    <Sig Type="SIG" Name="to_lpc3141:12"/>
                    <Sig Type="SIG" Name="to_lpc3141:13"/>
                    <Sig Type="SIG" Name="to_lpc3141:14"/>
                    <Sig Type="SIG" Name="to_lpc3141:15"/>
                </Bus>
                <Bus Name="from_lpc3141">
                    <Sig Type="SIG" Name="from_lpc3141:0"/>
                    <Sig Type="SIG" Name="from_lpc3141:1"/>
                    <Sig Type="SIG" Name="from_lpc3141:2"/>
                    <Sig Type="SIG" Name="from_lpc3141:3"/>
                    <Sig Type="SIG" Name="from_lpc3141:4"/>
                    <Sig Type="SIG" Name="from_lpc3141:5"/>
                    <Sig Type="SIG" Name="from_lpc3141:6"/>
                    <Sig Type="SIG" Name="from_lpc3141:7"/>
                    <Sig Type="SIG" Name="from_lpc3141:8"/>
                    <Sig Type="SIG" Name="from_lpc3141:9"/>
                    <Sig Type="SIG" Name="from_lpc3141:10"/>
                    <Sig Type="SIG" Name="from_lpc3141:11"/>
                    <Sig Type="SIG" Name="from_lpc3141:12"/>
                    <Sig Type="SIG" Name="from_lpc3141:13"/>
                    <Sig Type="SIG" Name="from_lpc3141:14"/>
                    <Sig Type="SIG" Name="from_lpc3141:15"/>
                </Bus>
            </Trace>
            <Trigger>
                <TU Serialbits="0" Type="0" ID="1" Sig="lpc3141_b_n_stcs1_ipad,"/>
                <TU Serialbits="0" Type="0" ID="2" Sig="lpc3141_b_n_stcs0_ipad,"/>
                <TU Serialbits="0" Type="0" ID="3" Sig="lpc3141_b_n_oe_ipad,"/>
                <TU Serialbits="0" Type="0" ID="4" Sig="lpc3141_b_n_we_ipad,"/>
                <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
            </Trigger>
        </Dataset>
    </Core>
</Project>
