#-- Lattice Semiconductor Corporation Ltd.
#-- Bali Reveal project file

#device options
[Device]
part = LCMXO2-7000ZE-1BG256C
family = MachXO2
device = LCMXO2-7000ZE
speed = 1
package = CABGA256
operation = Commercial

#design options
[Design]
title = PC104
path = C:/Users/rawa/Desktop/FPGA_PC104/impl1
core_generate = C:/Users/rawa/Desktop/FPGA_PC104/impl1
search_path = C:/Users/rawa/Desktop/FPGA_PC104
top = top_level
lpf = C:/Users/rawa/Desktop/FPGA_PC104/PC104.lpf
synthesis = lse

#strategy options
VHDL2008 = false

#HDLs options
[HDLs]
C:/Users/rawa/Desktop/FPGA_PC104/pc104/src/bidi_ts_buffer.vhd = VHDL, work
C:/Users/rawa/Desktop/FPGA_PC104/pc104/src/reset_synchronizer.vhd = VHDL, work
C:/Users/rawa/Desktop/FPGA_PC104/pc104/src/top_level.vhd = VHDL, work
[HDL_Defines]
SBP_SYNTHESIS=
[HDL_Param]
[Generated]
C:/Users/rawa/Desktop/FPGA_PC104/impl1/reveal_workspace/tmpreveal/top_level_la0_trig_gen.v=Verilog
C:/Users/rawa/Desktop/FPGA_PC104/impl1/reveal_workspace/tmpreveal/top_level_la0_gen.v=Verilog
C:/Users/rawa/Desktop/FPGA_PC104/impl1/reveal_workspace/tmpreveal/top_level_rvl_top.vhd=VHDL,work