[Project]
Current Flow=Generic
VCS=0
version=3
Current Config=compile

[Configurations]
compile=pc104

[Library]
pc104=.\pc104\pc104.lib

[Settings]
AccessRead=0
AccessReadWrite=0
AccessACCB=0
AccessACCR=0
AccessReadWriteSLP=0
AccessReadTopLevel=1
DisableC=1
ENABLE_ADV_DATAFLOW=0
FLOW_TYPE=HDL
LANGUAGE=VHDL
REFRESH_FLOW=1
FLOWTOOLS=NONE
FAMILY=
fileopenfolder=C:\Users\rawa\Desktop\FPGA_PC104_OLD\FPGA_PC104\FPGA_PC104\src

[LocalVerilogSets]
EnableSLP=1
EnableDebug=0

[LocalVhdlSets]
CompileWithDebug=0

[$LibMap$]
pc104=.
Active_lib=

[Files]
/bidi_ts_buffer.vhd=-1
/reset_synchronizer.vhd=-1
/top_level.vhd=-1

[Files.Data]
.\src\bidi_ts_buffer.vhd=VHDL Source Code
.\src\reset_synchronizer.vhd=VHDL Source Code
.\src\top_level.vhd=VHDL Source Code

[SpecTracer]
WindowVisible=0
[HierarchyViewer]
HierarchyInformation=top_level|synthesis|0 
ShowHide=ShowTopLevel
Selected=