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Report for cell top_level.synthesis
Register bits:  20 of 6864 (0.291%)
I/O cells:      174
                                  Cell usage:
                               cell     count   Res Usage(%)
                                 BB        48          100.0
                            EHXPLLJ         1          100.0
                            FD1S3AX        20          100.0
                                GSR         1          100.0
                                 IB        54          100.0
                               LUT4        55          100.0
                                 OB        55          100.0
                                OBZ        17          100.0
SUB MODULES
                                pll         1
                              TOTAL       252
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Report for cell pll.v1
Instance Path : clock_generator
                                  Cell usage:
                               cell     count   Res Usage(%)
                            EHXPLLJ         1          100.0
                              TOTAL         1