[ActiveSupport MAP]
Device = LCMXO2-7000ZE;
Package = CABGA256;
Performance = 1;
LUTS_avail = 6864;
LUTS_used = 57;
FF_avail = 7071;
FF_used = 20;
INPUT_LVCMOS33 = 54;
OUTPUT_LVCMOS33 = 72;
BIDI_LVCMOS33 = 48;
IO_avail = 207;
IO_used = 174;
EBR_avail = 26;
EBR_used = 0;
; Begin PLL Section
Instance_Name = clock_generator/PLLInst_0;
Type = EHXPLLJ;
CLKOP_Post_Divider_A_Input = DIVA;
CLKOS_Post_Divider_B_Input = DIVB;
CLKOS2_Post_Divider_C_Input = DIVC;
CLKOS3_Post_Divider_D_Input = DIVD;
Pre_Divider_A_Input = VCO_PHASE;
Pre_Divider_B_Input = VCO_PHASE;
Pre_Divider_C_Input = VCO_PHASE;
Pre_Divider_D_Input = VCO_PHASE;
VCO_Bypass_A_Input = VCO_PHASE;
VCO_Bypass_B_Input = VCO_PHASE;
VCO_Bypass_C_Input = VCO_PHASE;
VCO_Bypass_D_Input = VCO_PHASE;
FB_MODE = INT_OP;
CLKI_Divider = 1;
CLKFB_Divider = 1;
CLKOP_Divider = 38;
CLKOS_Divider = 68;
CLKOS2_Divider = 34;
CLKOS3_Divider = 1;
Fractional_N_Divider = 0;
CLKOP_Desired_Phase_Shift(degree) = 0;
CLKOP_Trim_Option_Rising/Falling = RISING;
CLKOP_Trim_Option_Delay = 0;
CLKOS_Desired_Phase_Shift(degree) = 0;
CLKOS_Trim_Option_Rising/Falling = RISING;
CLKOS_Trim_Option_Delay = 0;
CLKOS2_Desired_Phase_Shift(degree) = 0;
CLKOS3_Desired_Phase_Shift(degree) = 0;
; End PLL Section